Power detection circuit of three-phase inverter

Abstract

The utility model relates to the technical field of inverters, in particular to a power detection circuit of a three-phase inverter, which comprises the three-phase inverter, a voltage detection module, a first analog-to-digital conversion chip, a current detection module, a second analog-to-digital conversion chip and a calculation chip, the voltage detection module, the first analog-to-digital conversion chip and the calculation chip are electrically connected in sequence, the current detection module is used for measuring the three-phase current of the three-phase inverter, and the current detection module, the second analog-to-digital conversion chip and the calculation chip are electrically connected in sequence. According to the utility model, the voltage detection module and the current detection module obtain voltage and current data of the three-phase inverter, isolation acquisition is realized, interference is reduced, data accuracy is ensured, signals are amplified, data processing by a subsequent circuit is facilitated, power is calculated in real time by the calculation chip, and reference is provided for control of the three-phase inverter.

Description

Technical Field

[0001] This utility model relates to the field of inverter technology, and more specifically, to a power detection circuit for a three-phase inverter. Background Technology

[0002] In the field of inverter technology, three-phase inverters are widely used in many fields such as industrial production, power systems, and new energy power generation. Accurate detection of the power of three-phase inverters is crucial for the stable operation of the system, efficiency optimization, and fault diagnosis. However, existing power detection methods and circuits have many shortcomings.

[0003] Some traditional power detection circuits have complex structures involving a large number of discrete components, which not only increases the difficulty of circuit design and debugging, but also increases production costs. Furthermore, the complex circuit layout is prone to introducing more interference signals, affecting detection accuracy. Some detection circuits have low detection accuracy and cannot meet the requirements of high-precision power measurement. Utility Model Content

[0004] The purpose of this invention is to provide a power detection circuit for a three-phase inverter to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] The power detection circuit of a three-phase inverter includes a three-phase inverter, a voltage detection module, a first analog-to-digital converter (ADC) chip, a current detection module, a second ADC chip, and a calculation chip. The voltage detection module is used to measure the three-phase voltage of the three-phase inverter. The voltage detection module, the first ADC chip, and the calculation chip are electrically connected in sequence. The current detection module is used to measure the three-phase current of the three-phase inverter. The current detection module, the second ADC chip, and the calculation chip are electrically connected in sequence.

[0007] Preferably, the three-phase inverter includes a DC power supply, capacitor C1, capacitor C2, transistor Q1, diode D1, transistor Q2, diode D2, transistor Q3, diode D3, transistor Q4, diode D4, transistor Q5, diode D5, transistor Q6, and diode D6.

[0008] The first terminal of capacitor C1 is connected to the positive terminal of the DC power supply. The second terminal of capacitor C1 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the negative terminal of the DC power supply. The collector of transistor Q1 is connected to the first terminal of capacitor C1. The emitter of transistor Q1 is connected to the collector of transistor Q2. The emitter of transistor Q2 is connected to the second terminal of capacitor C2. The anode of diode D1 is connected to the emitter of transistor Q1. The cathode of diode D1 is connected to the collector of transistor Q1. The anode of diode D2 is connected to the emitter of transistor Q2. The cathode of diode D2 is connected to the collector of transistor Q2. The collector of transistor Q3 is connected to the first terminal of capacitor C1. The emitter of transistor Q3 is connected to the collector of transistor Q4. The emitter of transistor Q4 is connected to the second terminal of capacitor C2. The anode of diode D3 is connected to the emitter of transistor Q3, and the cathode of diode D3 is connected to the collector of transistor Q3. The anode of diode D4 is connected to the emitter of transistor Q4, and the cathode of diode D4 is connected to the collector of transistor Q4. The collector of transistor Q5 is connected to the first terminal of capacitor C1. The emitter of transistor Q5 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to the second terminal of capacitor C2. The anode of diode D5 is connected to the emitter of transistor Q5, and the cathode of diode D5 is connected to the collector of transistor Q5. The anode of diode D6 is connected to the emitter of transistor Q6, and the cathode of diode D6 is connected to the collector of transistor Q6.

[0009] Preferably, the voltage detection module includes switch S1, resistor R1, voltage transformer TV1, switch S2, resistor R2, voltage transformer TV2, switch S3, resistor R3, voltage transformer TV3, amplifier chip U1, capacitor C3, resistor R4, capacitor C4, resistor R5, capacitor C5 and resistor R6, and the amplifier chip U1 is model OPA2227;

[0010] The first terminal of switch S1 is connected to the emitter of transistor Q1, the second terminal of switch S1 is connected to the first terminal of resistor R1, the second terminal of resistor R1 is connected to the first input terminal of voltage transformer TV1, the second input terminal of voltage transformer TV1 is grounded, the first output terminal of voltage transformer TV1 is connected to the -InA port of amplifier chip U1, the second output terminal of voltage transformer TV1 is grounded, the +InA port of amplifier chip U1 is grounded, the first terminal of capacitor C3 is connected to the OutA port of amplifier chip U1, the second terminal of capacitor C3 is connected to the -InA port of amplifier chip U1, the first terminal of resistor R4 is connected to the first terminal of capacitor C3, and the second terminal of resistor R4 is connected to the second terminal of capacitor C3.

[0011] The first terminal of switch S2 is connected to the emitter of transistor Q3. The second terminal of switch S2 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first input terminal of voltage transformer TV2. The second input terminal of voltage transformer TV2 is grounded. The first output terminal of voltage transformer TV2 is connected to the -InB port of amplifier chip U1. The second output terminal of voltage transformer TV2 is grounded. The +InB port of amplifier chip U1 is grounded. The first terminal of capacitor C4 is connected to the -InB port of amplifier chip U1. The second terminal of capacitor C4 is connected to the OutB port of amplifier chip U1. The first terminal of resistor R5 is connected to the first terminal of capacitor C4. The second terminal of resistor R5 is connected to the second terminal of capacitor C4.

[0012] The first terminal of switch S3 is connected to the emitter of transistor Q5. The second terminal of switch S3 is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the first input terminal of voltage transformer TV3. The second input terminal of voltage transformer TV3 is grounded. The first output terminal of voltage transformer TV3 is connected to the -InC port of amplifier chip U1. The second output terminal of voltage transformer TV3 is grounded. The +InC port of amplifier chip U1 is grounded. The first terminal of capacitor C5 is connected to the -InC port of amplifier chip U1. The second terminal of capacitor C5 is connected to the OutC port of amplifier chip U1. The first terminal of resistor R6 is connected to the first terminal of capacitor C5. The second terminal of resistor R6 is connected to the second terminal of capacitor C5.

[0013] Preferably, the current detection module includes current transformer TA1, current transformer TA2, current transformer TA3, amplifier chip U2, capacitor C6, resistor R7, capacitor C7, resistor R8, capacitor C8 and resistor R9, and the amplifier chip U2 is model OPA2227.

[0014] Current transformers TA1, TA2, and TA3 are respectively installed outside different three-phase output lines of the three-phase inverter. The first output terminal of current transformer TA1 is connected to the -InA port of amplifier chip U2, the second output terminal of current transformer TA1 is grounded, the +InA port of amplifier chip U2 is grounded, the first terminal of capacitor C6 is connected to the OutA port of amplifier chip U2, the second terminal of capacitor C6 is connected to the -InA port of amplifier chip U2, the first terminal of resistor R7 is connected to the first terminal of capacitor C6, and the second terminal of resistor R7 is connected to the second terminal of capacitor C6.

[0015] The first output terminal of current transformer TA2 is connected to the -InB port of amplifier chip U2, the second output terminal of current transformer TA2 is grounded, the +InB port of amplifier chip U2 is grounded, the first terminal of capacitor C7 is connected to the -InB port of amplifier chip U2, the second terminal of capacitor C7 is connected to the OutB port of amplifier chip U2, the first terminal of resistor R8 is connected to the first terminal of capacitor C7, and the second terminal of resistor R8 is connected to the second terminal of capacitor C7.

[0016] The first output terminal of current transformer TA3 is connected to the -InC port of amplifier chip U2. The second output terminal of current transformer TA3 is grounded. The +InC port of amplifier chip U2 is grounded. The first terminal of capacitor C8 is connected to the -InC port of amplifier chip U2. The second terminal of capacitor C8 is connected to the OutC port of amplifier chip U2. The first terminal of resistor R9 is connected to the first terminal of capacitor C8. The second terminal of resistor R9 is connected to the second terminal of capacitor C8.

[0017] Preferably, the OutA, OutB and OutC ports of the amplifier chip U1 are connected to different input terminals of the first analog-to-digital converter chip, and the first analog-to-digital converter chip is signal-connected to the computing chip.

[0018] Preferably, the OutA, OutB, and OutC ports of the amplifier chip U2 are connected to different input terminals of the second analog-to-digital converter chip, and the second analog-to-digital converter chip is signal-connected to the computing chip.

[0019] Preferably, a communication chip is also included, and the computing chip and the communication chip are signal-connected.

[0020] Compared with the prior art, the beneficial effects of this utility model are:

[0021] This invention acquires voltage and current data of a three-phase inverter by setting up voltage detection modules and current detection modules, isolates the acquisition, reduces interference, and ensures data accuracy. At the same time, the signals are amplified to facilitate subsequent circuit processing of the data, and the power is calculated in real time by the computing chip, providing a reference for the control of the three-phase inverter. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall structure of the utility model;

[0023] Figure 2 The circuit diagram of the three-phase inverter in the utility model is shown below.

[0024] Figure 3 This is a circuit diagram of the voltage detection module in the utility model.

[0025] Figure 4 This is a circuit diagram of the current detection module in the utility model.

[0026] Figure 5 This is a schematic diagram showing the connection of the first analog-to-digital converter chip, the second analog-to-digital converter chip, the computing chip, and the communication chip in the utility model.

[0027] In the picture:

[0028] 1. Three-phase inverter;

[0029] 2. Voltage detection module;

[0030] 3. First analog-to-digital converter chip;

[0031] 4. Current detection module;

[0032] 5. Second analog-to-digital converter chip;

[0033] 6. Computing chip;

[0034] 7. Communication chip. Detailed Implementation

[0035] The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0036] Please see Figures 1-5 The present invention provides the following technical solution:

[0037] The power detection circuit of the three-phase inverter includes a three-phase inverter 1, a voltage detection module 2, a first analog-to-digital converter chip 3, a current detection module 4, a second analog-to-digital converter chip 5, and a calculation chip 6. The voltage detection module 2 is used to measure the three-phase voltage of the three-phase inverter 1. The voltage detection module 2, the first analog-to-digital converter chip 3, and the calculation chip 6 are electrically connected in sequence. The current detection module 4 is used to measure the three-phase current of the three-phase inverter 1. The current detection module 4, the second analog-to-digital converter chip 5, and the calculation chip 6 are electrically connected in sequence. The calculation chip 6 can calculate power data in real time. The calculation chip 6 uses a common microprocessor, such as a microcontroller, a DSP signal processor, or an FPGA.

[0038] In this embodiment, the three-phase inverter 1 includes a DC power supply, capacitor C1, capacitor C2, transistor Q1, diode D1, transistor Q2, diode D2, transistor Q3, diode D3, transistor Q4, diode D4, transistor Q5, diode D5, transistor Q6, and diode D6.

[0039] The first terminal of capacitor C1 is connected to the positive terminal of the DC power supply. The second terminal of capacitor C1 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the negative terminal of the DC power supply. The collector of transistor Q1 is connected to the first terminal of capacitor C1. The emitter of transistor Q1 is connected to the collector of transistor Q2. The emitter of transistor Q2 is connected to the second terminal of capacitor C2. The anode of diode D1 is connected to the emitter of transistor Q1. The cathode of diode D1 is connected to the collector of transistor Q1. The anode of diode D2 is connected to the emitter of transistor Q2. The cathode of diode D2 is connected to the collector of transistor Q2. The collector of transistor Q3 is connected to the first terminal of capacitor C1. The emitter of transistor Q3 is connected to the collector of transistor Q4. The emitter of transistor Q4 is connected to the second terminal of capacitor C2. The anode of diode D3 is connected to the emitter of transistor Q3, and the cathode of diode D3 is connected to the collector of transistor Q3. The anode of diode D4 is connected to the emitter of transistor Q4, and the cathode of diode D4 is connected to the collector of transistor Q4. The collector of transistor Q5 is connected to the first terminal of capacitor C1. The emitter of transistor Q5 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to the second terminal of capacitor C2. The anode of diode D5 is connected to the emitter of transistor Q5, and the cathode of diode D5 is connected to the collector of transistor Q5. The anode of diode D6 is connected to the emitter of transistor Q6, and the cathode of diode D6 is connected to the collector of transistor Q6.

[0040] Specifically, the voltage detection module 2 includes switch S1, resistor R1, voltage transformer TV1, switch S2, resistor R2, voltage transformer TV2, switch S3, resistor R3, voltage transformer TV3, amplifier chip U1, capacitor C3, resistor R4, capacitor C4, resistor R5, capacitor C5, and resistor R6. The amplifier chip U1 is an OPA2227. Switches S1, S2, and S3 in the voltage detection module 2 are connected to the emitters of transistors Q1, Q3, and Q5 in the three-phase inverter 1, respectively, to acquire the three-phase output voltage signal. After current limiting by resistors R1, R2, and R3, the signal is input to the input terminals of voltage transformers TV1, TV2, and TV3. The voltage transformers convert the high voltage into a low voltage signal suitable for subsequent circuit processing and achieve electrical isolation to prevent high voltage from damaging or interfering with subsequent circuits.

[0041] The first terminal of switch S1 is connected to the emitter of transistor Q1, the second terminal of switch S1 is connected to the first terminal of resistor R1, the second terminal of resistor R1 is connected to the first input terminal of voltage transformer TV1, the second input terminal of voltage transformer TV1 is grounded, the first output terminal of voltage transformer TV1 is connected to the -InA port of amplifier chip U1, the second output terminal of voltage transformer TV1 is grounded, the +InA port of amplifier chip U1 is grounded, the first terminal of capacitor C3 is connected to the OutA port of amplifier chip U1, the second terminal of capacitor C3 is connected to the -InA port of amplifier chip U1, the first terminal of resistor R4 is connected to the first terminal of capacitor C3, and the second terminal of resistor R4 is connected to the second terminal of capacitor C3.

[0042] The first terminal of switch S2 is connected to the emitter of transistor Q3. The second terminal of switch S2 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first input terminal of voltage transformer TV2. The second input terminal of voltage transformer TV2 is grounded. The first output terminal of voltage transformer TV2 is connected to the -InB port of amplifier chip U1. The second output terminal of voltage transformer TV2 is grounded. The +InB port of amplifier chip U1 is grounded. The first terminal of capacitor C4 is connected to the -InB port of amplifier chip U1. The second terminal of capacitor C4 is connected to the OutB port of amplifier chip U1. The first terminal of resistor R5 is connected to the first terminal of capacitor C4. The second terminal of resistor R5 is connected to the second terminal of capacitor C4.

[0043] The first terminal of switch S3 is connected to the emitter of transistor Q5. The second terminal of switch S3 is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the first input terminal of voltage transformer TV3. The second input terminal of voltage transformer TV3 is grounded. The first output terminal of voltage transformer TV3 is connected to the -InC port of amplifier chip U1. The second output terminal of voltage transformer TV3 is grounded. The +InC port of amplifier chip U1 is grounded. The first terminal of capacitor C5 is connected to the -InC port of amplifier chip U1. The second terminal of capacitor C5 is connected to the OutC port of amplifier chip U1. The first terminal of resistor R6 is connected to the first terminal of capacitor C5. The second terminal of resistor R6 is connected to the second terminal of capacitor C5.

[0044] Specifically, the current detection module 4 includes current transformers TA1, TA2, and TA3, an amplifier chip U2, a capacitor C6, a resistor R7, a capacitor C7, a resistor R8, a capacitor C8, and a resistor R9. The amplifier chip U2 is model OPA2227. The current transformers use the principle of electromagnetic induction to isolate and acquire current signals, while also providing electrical isolation to improve safety.

[0045] Current transformers TA1, TA2, and TA3 are respectively installed outside different three-phase output lines of three-phase inverter 1. The first output terminal of current transformer TA1 is connected to the -InA port of amplifier chip U2, the second output terminal of current transformer TA1 is grounded, the +InA port of amplifier chip U2 is grounded, the first terminal of capacitor C6 is connected to the OutA port of amplifier chip U2, the second terminal of capacitor C6 is connected to the -InA port of amplifier chip U2, the first terminal of resistor R7 is connected to the first terminal of capacitor C6, and the second terminal of resistor R7 is connected to the second terminal of capacitor C6.

[0046] The first output terminal of current transformer TA2 is connected to the -InB port of amplifier chip U2, the second output terminal of current transformer TA2 is grounded, the +InB port of amplifier chip U2 is grounded, the first terminal of capacitor C7 is connected to the -InB port of amplifier chip U2, the second terminal of capacitor C7 is connected to the OutB port of amplifier chip U2, the first terminal of resistor R8 is connected to the first terminal of capacitor C7, and the second terminal of resistor R8 is connected to the second terminal of capacitor C7.

[0047] The first output terminal of current transformer TA3 is connected to the -InC port of amplifier chip U2. The second output terminal of current transformer TA3 is grounded. The +InC port of amplifier chip U2 is grounded. The first terminal of capacitor C8 is connected to the -InC port of amplifier chip U2. The second terminal of capacitor C8 is connected to the OutC port of amplifier chip U2. The first terminal of resistor R9 is connected to the first terminal of capacitor C8. The second terminal of resistor R9 is connected to the second terminal of capacitor C8.

[0048] Furthermore, the OutA, OutB, and OutC ports of the amplifier chip U1 are respectively connected to different input terminals of the first analog-to-digital converter chip 3. The first analog-to-digital converter chip 3 is connected to the computing chip 6 via signal. The first analog-to-digital converter chip 3 converts the voltage analog signal into a digital signal and then transmits it to the computing chip 6.

[0049] It is worth noting that the OutA, OutB, and OutC ports of the amplifier chip U2 are connected to different input terminals of the second analog-to-digital converter chip 5. The second analog-to-digital converter chip 5 is connected to the computing chip 6 via signal. The second analog-to-digital converter chip 5 converts the current analog signal into a digital signal and then transmits it to the computing chip 6.

[0050] It is worth noting that it also includes a communication chip 7, and the computing chip 6 and the communication chip 7 are connected by a signal. The communication chip 7 uses wireless communication to achieve data interaction with external devices.

[0051] In use, the power detection circuit of the three-phase inverter of this utility model obtains the voltage and current data of the three-phase inverter 1 through voltage transformers and current transformers. Then, the signal is amplified by amplifier chips U1 and U2, and the analog signal is converted into a digital signal by the first analog-to-digital converter chip 3 and the second analog-to-digital converter chip 5. The calculation chip 6 can quickly detect the power and communicate with external devices through the communication chip 7, effectively isolating data measurement and ensuring the accuracy of calculation.

[0052] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A power detection circuit for a three-phase inverter, characterized in that: The system includes a three-phase inverter (1), a voltage detection module (2), a first analog-to-digital converter (3), a current detection module (4), a second analog-to-digital converter (5), and a computing chip (6). The voltage detection module (2) is used to measure the three-phase voltage of the three-phase inverter (1). The voltage detection module (2), the first analog-to-digital converter (3), and the computing chip (6) are electrically connected in sequence. The current detection module (4) is used to measure the three-phase current of the three-phase inverter (1). The current detection module (4), the second analog-to-digital converter (5), and the computing chip (6) are electrically connected in sequence.

2. The power detection circuit of the three-phase inverter according to claim 1, characterized in that: The three-phase inverter (1) includes a DC power supply, capacitor C1, capacitor C2, transistor Q1, diode D1, transistor Q2, diode D2, transistor Q3, diode D3, transistor Q4, diode D4, transistor Q5, diode D5, transistor Q6 and diode D6. The first terminal of capacitor C1 is connected to the positive terminal of the DC power supply. The second terminal of capacitor C1 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the negative terminal of the DC power supply. The collector of transistor Q1 is connected to the first terminal of capacitor C1. The emitter of transistor Q1 is connected to the collector of transistor Q2. The emitter of transistor Q2 is connected to the second terminal of capacitor C2. The anode of diode D1 is connected to the emitter of transistor Q1. The cathode of diode D1 is connected to the collector of transistor Q1. The anode of diode D2 is connected to the emitter of transistor Q2. The cathode of diode D2 is connected to the collector of transistor Q2. The collector of transistor Q3 is connected to the first terminal of capacitor C1. The emitter of transistor Q3 is connected to the collector of transistor Q4. The emitter of transistor Q4 is connected to the second terminal of capacitor C2. The anode of diode D3 is connected to the emitter of transistor Q3, and the cathode of diode D3 is connected to the collector of transistor Q3. The anode of diode D4 is connected to the emitter of transistor Q4, and the cathode of diode D4 is connected to the collector of transistor Q4. The collector of transistor Q5 is connected to the first terminal of capacitor C1. The emitter of transistor Q5 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to the second terminal of capacitor C2. The anode of diode D5 is connected to the emitter of transistor Q5, and the cathode of diode D5 is connected to the collector of transistor Q5. The anode of diode D6 is connected to the emitter of transistor Q6, and the cathode of diode D6 is connected to the collector of transistor Q6.

3. The power detection circuit of the three-phase inverter according to claim 2, characterized in that: The voltage detection module (2) includes switch S1, resistor R1, voltage transformer TV1, switch S2, resistor R2, voltage transformer TV2, switch S3, resistor R3, voltage transformer TV3, amplifier chip U1, capacitor C3, resistor R4, capacitor C4, resistor R5, capacitor C5 and resistor R6. The amplifier chip U1 is model OPA2227. The first terminal of switch S1 is connected to the emitter of transistor Q1, the second terminal of switch S1 is connected to the first terminal of resistor R1, the second terminal of resistor R1 is connected to the first input terminal of voltage transformer TV1, the second input terminal of voltage transformer TV1 is grounded, the first output terminal of voltage transformer TV1 is connected to the -InA port of amplifier chip U1, the second output terminal of voltage transformer TV1 is grounded, the +InA port of amplifier chip U1 is grounded, the first terminal of capacitor C3 is connected to the OutA port of amplifier chip U1, the second terminal of capacitor C3 is connected to the -InA port of amplifier chip U1, the first terminal of resistor R4 is connected to the first terminal of capacitor C3, and the second terminal of resistor R4 is connected to the second terminal of capacitor C3. The first terminal of switch S2 is connected to the emitter of transistor Q3. The second terminal of switch S2 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first input terminal of voltage transformer TV2. The second input terminal of voltage transformer TV2 is grounded. The first output terminal of voltage transformer TV2 is connected to the -InB port of amplifier chip U1. The second output terminal of voltage transformer TV2 is grounded. The +InB port of amplifier chip U1 is grounded. The first terminal of capacitor C4 is connected to the -InB port of amplifier chip U1. The second terminal of capacitor C4 is connected to the OutB port of amplifier chip U1. The first terminal of resistor R5 is connected to the first terminal of capacitor C4. The second terminal of resistor R5 is connected to the second terminal of capacitor C4. The first terminal of switch S3 is connected to the emitter of transistor Q5. The second terminal of switch S3 is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the first input terminal of voltage transformer TV3. The second input terminal of voltage transformer TV3 is grounded. The first output terminal of voltage transformer TV3 is connected to the -InC port of amplifier chip U1. The second output terminal of voltage transformer TV3 is grounded. The +InC port of amplifier chip U1 is grounded. The first terminal of capacitor C5 is connected to the -InC port of amplifier chip U1. The second terminal of capacitor C5 is connected to the OutC port of amplifier chip U1. The first terminal of resistor R6 is connected to the first terminal of capacitor C5. The second terminal of resistor R6 is connected to the second terminal of capacitor C5.

4. The power detection circuit of the three-phase inverter according to claim 2, characterized in that: The current detection module (4) includes current transformer TA1, current transformer TA2, current transformer TA3, amplifier chip U2, capacitor C6, resistor R7, capacitor C7, resistor R8, capacitor C8 and resistor R9. The amplifier chip U2 is model OPA2227. Current transformers TA1, TA2 and TA3 are respectively installed outside the different three-phase output lines of the three-phase inverter (1). The first output terminal of current transformer TA1 is connected to the -InA port of amplifier chip U2, the second output terminal of current transformer TA1 is grounded, the +InA port of amplifier chip U2 is grounded, the first terminal of capacitor C6 is connected to the OutA port of amplifier chip U2, the second terminal of capacitor C6 is connected to the -InA port of amplifier chip U2, the first terminal of resistor R7 is connected to the first terminal of capacitor C6, and the second terminal of resistor R7 is connected to the second terminal of capacitor C6. The first output terminal of current transformer TA2 is connected to the -InB port of amplifier chip U2, the second output terminal of current transformer TA2 is grounded, the +InB port of amplifier chip U2 is grounded, the first terminal of capacitor C7 is connected to the -InB port of amplifier chip U2, the second terminal of capacitor C7 is connected to the OutB port of amplifier chip U2, the first terminal of resistor R8 is connected to the first terminal of capacitor C7, and the second terminal of resistor R8 is connected to the second terminal of capacitor C7. The first output terminal of current transformer TA3 is connected to the -InC port of amplifier chip U2. The second output terminal of current transformer TA3 is grounded. The +InC port of amplifier chip U2 is grounded. The first terminal of capacitor C8 is connected to the -InC port of amplifier chip U2. The second terminal of capacitor C8 is connected to the OutC port of amplifier chip U2. The first terminal of resistor R9 is connected to the first terminal of capacitor C8. The second terminal of resistor R9 is connected to the second terminal of capacitor C8.

5. The power detection circuit for a three-phase inverter according to claim 3, characterized in that: The OutA, OutB and OutC ports of the amplifier chip U1 are respectively connected to different input terminals of the first analog-to-digital converter chip (3), and the first analog-to-digital converter chip (3) is signal connected to the computing chip (6).

6. The power detection circuit of the three-phase inverter according to claim 4, characterized in that: The OutA, OutB and OutC ports of the amplifier chip U2 are respectively connected to different input terminals of the second analog-to-digital converter chip (5), and the second analog-to-digital converter chip (5) is signal connected to the computing chip (6).

7. The power detection circuit of the three-phase inverter according to claim 1, characterized in that: It also includes a communication chip (7), and the computing chip (6) and the communication chip (7) are connected by signals.

Images