Resistance sensor structure

Abstract

The embodiment of the utility model provides a resistance sensor structure which comprises a first thin film resistor, a plurality of second thin film resistors electrically coupled with the first thin film resistor in series and a plurality of control grids electrically coupled with the first thin film resistor in series, the plurality of control gates are electrically coupled in series, and a respective one of the plurality of control gates is electrically coupled in parallel with a respective one of the plurality of second thin film resistors. The resistance of the resistive sensor structure may be tuned or trimmed to compensate for semiconductor fabrication variations and / or to enable flexible use of the resistive sensor structure.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor structure, and more particularly to a resistance sensor structure. Background Technology

[0002] Semiconductor-based integrated circuits can include a variety of semiconductor devices. These semiconductor devices can include active semiconductor devices and / or passive semiconductor devices. Active semiconductor devices can include transistors and other semiconductor devices that operate using a power supply. Passive semiconductor devices include sensors, capacitors, resistors, and / or other semiconductor devices that can operate without a power supply. Utility Model Content

[0003] An embodiment of this utility model provides a resistance sensor structure including a first thin-film resistor, a plurality of second thin-film resistors electrically coupled in series with the first thin-film resistor, and a plurality of control gates electrically coupled in series with the first thin-film resistor. The plurality of second thin-film resistors are electrically connected in series, the plurality of control gates are electrically coupled in series, and a corresponding one of the plurality of control gates is electrically coupled in parallel with a corresponding one of the plurality of second thin-film resistors.

[0004] An embodiment of this utility model provides a resistance sensor structure including a thin-film resistor, a resistance trimming structure electrically coupled to the thin-film resistor through a plurality of electrically conductive sensing lines, and a plurality of control gates electrically coupled to the resistance trimming structure.

[0005] Based on the above, the embodiments of this utility model enable the resistance temperature coefficient of the resistance sensor structure to be tuned or fine-tuned without having to manufacture the resistance sensor structure to have a single specific resistance temperature coefficient. The resistance of the resistance sensor structure described herein can be tuned or fine-tuned to compensate for semiconductor manufacturing variations and / or to achieve flexible use of the resistance sensor structure.

[0006] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a diagram of an exemplary environment in which the systems and / or methods described herein can be implemented.

[0008] Figure 2A-2C This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0009] Figure 3A and Figure 3B This is a diagram illustrating an example operational configuration of the resistance sensor structure described in this article.

[0010] Figures 4A-4D This is a diagram illustrating an example of the structure for forming a resistance sensor as described in this article.

[0011] Figure 5A-5I This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0012] Figures 6A-6C This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0013] Figure 7A and Figure 7B This is a diagram illustrating an example operational configuration of the resistance sensor structure described in this article.

[0014] Figure 8A and Figure 8B This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0015] Figures 9A-9C This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0016] Figure 10A and Figure 10B This is a diagram illustrating an example operational configuration of the resistance sensor structure described in this article.

[0017] Figure 11A and Figure 11B This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0018] Figures 12A-12C This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0019] Figure 13A and Figure 13B This is a diagram illustrating an example operational configuration of the resistance sensor structure described in this article.

[0020] Figures 14A-14H This is a diagram illustrating an example of the structure for forming a resistance sensor as described in this article.

[0021] Figure 15A and Figure 15B This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0022] Figures 16A-16C This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0023] Figure 17A-17I This is a diagram illustrating an example of the structure for forming a resistance sensor as described in this article.

[0024] Figure 18A and Figure 18B This is a diagram of an example implementation of the tunable resistive sensor structure described herein.

[0025] Figure 19 This is a diagram of an example component of the device described herein.

[0026] Figure 20 This is a flowchart of an example process related to forming the resistance sensor structure described herein. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0028] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0029] Resistor structures (such as thin-film resistors (TFRs) and / or other types of resistor structures) are used in many applications, including resistor-capacitor (RC) circuits, power drivers, power amplifiers, thermal sensors, current meters, and / or radio frequency (RF) applications. Some applications of resistor structures are sensitive to one or more parameters of the resistor structure. For example, when measuring circuits such as thermal sensor circuits or current meter circuits, the temperature coefficient of resistance (TCR) can directly affect the measurement accuracy of the circuit. The TCR of a resistor structure is a numerical expression of how sensitive the resistor structure's resistance is to temperature changes. The TCR of a resistor structure is typically expressed in parts per million (ppm / °C) or parts per million (ppm / °K). Resistor structures with high TCR (e.g., high sensitivity of resistance to temperature changes) enable more accurate temperature measurements in thermal sensor circuits compared to resistor structures with low TCR. However, resistor structures with high TCR can cause ambient temperature to have a greater impact on current measurements in current meter circuits because the resistor structure is more susceptible to resistance changes. Compared to using resistor structures with low TCR in current meter circuits (which are less susceptible to resistance changes caused by temperature), resistor structures with high TCR result in lower current measurement accuracy.

[0030] In some cases, resistor structures can be manufactured with a specific resistance coefficient (TCR) (or a specific range of TCRs). However, the TCR of a resistor structure cannot be modified after manufacturing. This can limit the use of the resistor structure for a particular purpose. Manufacturing resistor structures on semiconductor devices with different TCRs for different applications or purposes increases the cost and complexity of semiconductor design and manufacturing. Furthermore, due to process variations in semiconductor manufacturing after fabrication, the TCR may vary across multiple resistor structures, leading to errors in resistance and / or TCR measurements based on the resistor structure.

[0031] The various embodiments described herein include resistive sensor structures with tunable resistances after manufacturing. One or more of the resistive sensor structures described herein can be implemented as measurement circuits, such as current meter circuits, thermal sensor circuits, and / or other types of measurement circuits. By enabling the TCR of the resistive sensor structure to be tuned or fine-tuned without having to manufacture the resistive sensor structure with a single specific TCR, the resistance of the resistive sensor structures described herein can be tuned or fine-tuned to compensate for semiconductor manufacturing variations and / or to achieve flexible use of the resistive sensor structures.

[0032] Some of the resistance sensor structures described herein include a primary thin-film resistor segment and one or more selectable thin-film resistor segments connected in series (e.g., connected together and connected to the primary thin-film resistor). The selectable thin-film resistor segments of the resistance sensor structures described herein can be selectively activated and / or deactivated based on the desired resistance and / or TCR of each resistance sensor structure. Various structural embodiments of control gates for selectively activating and / or deactivating one or more selectable thin-film resistors are disclosed herein. Examples of such control gates include transfer gates, programmable gates (e.g., switches, memory structures, other logic structures), and / or trim pads and / or combinations thereof.

[0033] In this manner, the resistance sensor structure in the semiconductor device described herein can be configured for a specific type of measurement circuit without having to manufacture the resistance sensor structure with a single, specific TCR. This reduces the manufacturing complexity of the resistance sensor structure and / or enables the resistance sensor structure to be used for more than one type of measurement circuit. Specifically, the TCR of the resistance sensor structure described herein can be modified during the operation of the semiconductor device, allowing the resistance sensor structure to be reused for different types of measurements, rather than (or additionally) including different measurement circuits for different types of measurements. Additionally and / or alternatively, the resistance and / or TCR of the resistance sensor structure can be modified after the manufacture of the resistance sensor structure to correct for or compensate for semiconductor process variations during the manufacture of the resistance sensor structure.

[0034] Figure 1 This is a diagram of an exemplary environment 100 that can implement the systems and / or methods described herein. Figure 1 As shown, the exemplary environment 100 may include a plurality of semiconductor processing stations (e.g., 102-112) and a wafer / die transfer station 114. The plurality of semiconductor processing stations (e.g., 102-112) may include a deposition station 102, an exposure station 104, a developing station 106, an etching station 108, a planarization station 110, a plating station 112, and / or another type of semiconductor processing station. The stations included in the exemplary environment 100 may be included in semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities and / or manufacturing facilities, and other examples.

[0035] Deposition station 102 is a semiconductor processing station that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, deposition station 102 includes a spin coater capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, deposition station 102 includes a chemical vapor deposition (CVD) station, such as a plasma-enhanced CVD (PECVD) station, a high-density plasma CVD (HDP-CVD) station, a sub-atmospheric CVD (SACVD) station, a low-pressure CVD (LPCVD) station, an atomic layer deposition (ALD) station, a plasma-enhanced atomic layer deposition (PEALD) station, or another type of CVD station. In some embodiments, the deposition equipment 102 includes a physical vapor deposition (PVD) equipment, such as a sputtering equipment or another type of PVD equipment. In some embodiments, the deposition equipment 102 includes an epitaxial equipment configured to form layers and / or regions of a device through epitaxial growth. In some embodiments, the exemplary environment 100 includes various types of deposition equipment 102.

[0036] Exposure station 104 is a semiconductor processing equipment capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., deep UV, extreme UV, and / or similar), an X-ray source, an electron beam (e-beam) source, and / or similar. Exposure station 104 exposes the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and / or similar patterns. In some embodiments, exposure station 104 includes a scanner, stepper, or similar type of exposure equipment.

[0037] The developing station 106 is a semiconductor processing equipment capable of developing a photoresist layer that has been exposed to a radiation source, in order to develop a pattern transferred from the exposure station 104 to the photoresist layer. In some embodiments, the developing station 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing station 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing station 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0038] Etching station 108 is a semiconductor processing equipment capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching station 108 may include a wet etching station, a dry etching station, and / or the like. In some embodiments, etching station 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, etching station 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gases to isotropically or directionally etch the one or more portions.

[0039] Planarization equipment 110 is a semiconductor processing equipment capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, planarization equipment 110 may include a chemical mechanical planarization (CMP) equipment and / or another type of planarization equipment for polishing or planarizing layers or surfaces of deposited or electroplated materials. Planarization equipment 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of a semiconductor device. Planarization equipment 110 may combine polishing pads and retaining rings (e.g., typically having a larger diameter than the semiconductor device) to utilize abrasives and corrosive chemical slurries. The polishing pads and semiconductor device can be pressed together by a dynamic polishing head and secured in place by the retaining rings. The dynamic polishing head can be rotated with different axes of rotation to remove material and flatten any irregularities in the topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0040] The plating machine 112 is a semiconductor processing machine capable of plating a substrate (e.g., a wafer, semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the plating machine 112 may include a copper plating apparatus, an aluminum plating apparatus, a nickel plating apparatus, a tin plating apparatus, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating apparatus, and / or an apparatus for plating one or more other types of conductive materials, metals, and / or similar materials.

[0041] The wafer / die transport station 114 includes mobile robots, robotic arms, trolleys or railcars, overhead hoist transport (OHT) systems, automated materially handling systems (AMHS), and / or other types of devices configured to transport substrates and / or semiconductor devices between semiconductor processing stations (e.g., 102-112), to transfer substrates and / or semiconductor devices between processing chambers of the same semiconductor processing station, and / or to transfer substrates and / or semiconductor devices to and from other locations (e.g., wafer racks, storage rooms, and / or the like). In some embodiments, the wafer / die transport station 114 may be a programmed device configured to travel a specific path and / or be semi-automatic or automatic. In some embodiments, exemplary environment 100 includes multiple wafer / die transport stations 114.

[0042] For example, wafer / die transfer station 114 may be included in a cluster station or another type of station comprising multiple processing chambers, and may be configured to transfer substrates and / or semiconductor devices between said multiple processing chambers, transfer substrates and / or semiconductor devices between processing chambers and buffers, transfer substrates and / or semiconductor devices between processing chambers and interface stations (e.g., equipment front end modules, EFEMs), and / or transfer substrates and / or semiconductor devices between processing chambers and transport carriers (e.g., front opening unified pods, FOUPs), and other examples. In some embodiments, wafer / die transfer station 114 may be included in a multi-chamber (or cluster) deposition station 102, which may include pre-cleaning processing chambers (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of ... In these embodiments, the wafer / die transfer stage 114 is configured to transfer substrates and / or semiconductor devices between processing chambers of the deposition stage 102 without disrupting or removing the vacuum (or at least a partial vacuum) between processing chambers and / or processing operations in the deposition stage 102, as described herein.

[0043] In some embodiments, one or more of the semiconductor processing station (e.g., 102-112) and / or wafer / die transfer station 114 may be used to perform one or more of the semiconductor processing operations described herein. For example, one or more of the semiconductor processing station (e.g., 102-112) and / or wafer / die transfer station 114 may be used to form a thin-film resistor and / or a resistor trimming structure forming a resistor sensor structure, wherein the resistor trimming structure is electrically coupled in series with the thin-film resistor, etc. In some embodiments, one or more of the semiconductor processing station (e.g., 102-112) and / or wafer / die transfer station 114 may be used to perform a combination Figures 4A-4D , Figures 14A-14H , Figure 17A-17I and / or Figure 20 One or more of the semiconductor processing operations described in other examples.

[0044] Figure 1 The number and arrangement of the devices shown are provided as one or more examples. In fact, with... Figure 1 Compared to the apparatus shown, there may be additional devices, fewer devices, different devices, or devices with different arrangements. Furthermore, Figure 1 The two or more devices shown can be implemented in a single device or Figure 1 The single device shown can be implemented as multiple distributed devices. Alternatively, a group of devices (e.g., one or more devices) in the exemplary environment 100 can perform one or more functions described as being performed by another group of devices in the exemplary environment 100.

[0045] Figure 2A-2C This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 2A Example 200 illustrates a circuit implementation of a resistance sensor structure 202. The resistance sensor structure 202 includes one or more inputs 204a, 204b and one or more sensing terminals 206a, 206b. The resistance sensor structure 202 can be configured as a current meter (e.g., a sensor configured to sense the amplitude of current on inputs 204a, 204b based on the resistance of the resistance sensor structure 202), a thermal sensor (e.g., a sensor configured to sense temperature based on the current on inputs 204a, 204b), and / or another type of resistance-based sensor.

[0046] The resistance sensor structure 202 is a tunable resistance sensor structure because it includes a main thin-film resistor 208 electrically coupled to a plurality of selectable thin-film resistors 210a-210n. The selectable thin-film resistors 210a-210n can be selectively activated or deactivated to achieve a specific total resistance (or a specific total TCR) and / or modify the resistance (or TCR) of the resistance sensor structure 202. The selectable thin-film resistors 210a-210n are electrically coupled in series, and are electrically coupled in series with the main thin-film resistor 208. Therefore, the total resistance of the resistance sensor structure 202 corresponds to the resistance of the main thin-film resistor 208 plus the resistance of any of the activated selectable thin-film resistors 210a-210n. For example, if the selectable thin-film resistors 210a and 210b are activated, the total resistance of the resistance sensor structure 202 corresponds to the combination of the resistance of the main thin-film resistor 208 and the resistances of the selectable thin-film resistors 210a and 210b, and the same applies to the total TCR of the resistance sensor structure 202.

[0047] The selectable thin-film resistors 210a-210n can be selected using the control gates 212a-212n included in the resistance sensor structure 202. Therefore, the selectable thin-film resistors 210a-210n and the control gates 212a-212n can correspond to the resistance trimming structure of the resistance sensor structure 202. Each of the selectable thin-film resistors 210a-210n can be electrically coupled in parallel with a control gate in the control gates 212a-212n. For example, selectable thin-film resistor 210a can be electrically coupled in parallel with control gate 212a, selectable thin-film resistor 210b can be electrically coupled in parallel with control gate 212b, and so on. Furthermore, the control gates 212a-212n are electrically connected in series with each other.

[0048] Control gates 212a-212n are configured to selectively control the flow of current between inputs 204a, 204b and sensing terminals 206a, 206b. For example, control gate 212a is configured to selectively control the flow of current between inputs 204a, 204b and sensing terminals 206a, 206b through a selectable thin-film resistor 210a (in this case, the selectable thin-film resistor 210a is considered selected or activated) or through control gate 212a (in this case, the selectable thin-film resistor 210a is considered deselected or disabled).

[0049] When the selectable thin-film resistor 210a is activated, the control gate 212a is in the off state, causing the control gate 212a to act as an open circuit. Therefore, the path of minimum resistance passes through the selectable thin-film resistor 210a, and the resistance (and TCR) of the selectable thin-film resistor 210a contributes to the total resistance (and total TCR) of the resistance sensor structure 202.

[0050] When the selectable thin-film resistor 210a is deactivated, the control gate 212a is in the ON state, causing it to function as a short circuit. Therefore, the path of minimum resistance passes through the control gate 212a, and current flows through the control gate 212a around the selectable thin-film resistor 210a. When the selectable thin-film resistor 210a is deactivated, it does not contribute to the total resistance (or total TCR) of the resistance sensor structure 202.

[0051] The optional thin-film resistors 210b-210n and control gates 212b-212n operate in a similar manner to those described above in combination with the optional thin-film resistors 210a and control gates 212a.

[0052] Each of the control gates 212b-212n includes a transfer gate, which is a complementary metal-oxide-semiconductor (CMOS) based switch comprising an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., an NMOS field-effect transistor or NFET) 214 electrically coupled in parallel to a p-type metal-oxide-semiconductor (PMOS) transistor (e.g., a PMOS field-effect transistor or PFET) 216. An input (e.g., a voltage input) can be provided to the gate of the NMOS transistor 214 of the transfer gate, and an inverting input (e.g., an inverted voltage input) can be provided to the gate of the PMOS transistor 216 to switch the transfer gate to an on (e.g., conductive) state. The absence of an input on the transfer gate causes the transfer gate to be in an off (e.g., non-conductive) state.

[0053] Figure 2B Example 218 of a structural implementation of the resistance sensor structure 202 is shown. For example... Figure 2BAs shown, the primary thin-film resistor 208 includes an active region 220 (e.g., an electrically resistive layer), a resistive protective oxide (RPO) layer 222 above the active region 220, a plurality of contacts 224 and 226 on opposite sides of the active region 220, and metallization layers 228 and 230 coupled to the contacts 224 and 226, respectively. Each of the alternative thin-film resistors 210b-210n similarly includes an active region 232 (e.g., an electrically resistive layer), an RPO layer 234 above the active region 232, a plurality of contacts 236 and 238 on opposite sides of the active region 232, and metallization layers 240 and 242 coupled to the contacts 236 and 238, respectively. In some embodiments, inputs 204a, 204b and / or sensing terminals 206a, 206b may be electrically connected to metallization layers 228 and / or 230.

[0054] Selectable thin-film resistors 210a-210n are electrically coupled in series through their active regions 232. For example, selectable thin-film resistors 210a and 210b are electrically connected in series through their active regions 232, selectable thin-film resistors 210b and 210c are electrically connected in series through their active regions 232, and so on. The main thin-film resistor 208 is electrically coupled in series with the selectable thin-film resistors 210a-210n through their active regions 232 and 220.

[0055] Metallization layers 240 and 242 can electrically connect selectable thin-film resistors 210a-210n to associated control gates 212a-212n. For example, metallization layers 240 and 242 can electrically connect selectable thin-film resistor 210a to control gate 212a, metallization layers 240 and 242 can electrically connect selectable thin-film resistor 210b to control gate 212b, and so on. Each of the control gates 212a-212n includes an NMOS transistor 214 and a PMOS transistor 216 connected in series.

[0056] NMOS transistor 214 may include an active region 244, a gate structure 246, and a plurality of contacts 248 and 250 connected to the active region 244 on the opposite side of the gate structure 246. The active region 244, the gate structure 246, and / or another region of NMOS transistor 214 may be doped with one or more n-type dopants, such as phosphorus (P) and / or arsenic (As) and other examples.

[0057] PMOS transistor 216 may include an active region 252, a gate structure 254, and a plurality of contacts 256 and 258 connected to the active region 252 on the opposite side of the gate structure 254. The active region 252, the gate structure 254, and / or another region of PMOS transistor 216 may be doped with one or more p-type dopants, such as boron (B) and / or gallium (Ga) and other examples.

[0058] Contacts 248 and 256 can connect NMOS transistor 214 and PMOS transistor 216 to metallization layer 240, respectively. Contacts 250 and 258 can connect NMOS transistor 214 and PMOS transistor 216 to metallization layer 242, respectively.

[0059] The active region 220 of the primary thin-film resistor 208 and the active region 232 of the optional thin-film resistors 210a-210n may each comprise a layer of electrically resistive material. Examples of such materials include nickel-chromium (nickel-chromium alloy or NiCr), tantalum nitride (TaN), polycrystalline silicon, and / or another suitable electrically resistive thin-film material. The active regions 244 and 252 of the NMOS transistor 214 and PMOS transistor 216 may each comprise silicon (Si), silicon-germanium (SiGe), and / or another suitable channel material.

[0060] The RPO layer 222 of the main thin-film resistor 208 and the RPO layer 234 of the optional thin-film resistors 210a-210n may each comprise, for example, silicon oxide (SiO2). x ), silicon nitride (Si x N y Layers of dielectric materials such as silicon oxynitride (SiON) and / or silicon oxynitride (SiON) may be included. RPO layers 222 and 234 may be included to prevent or reduce the possibility of silicide formation in active regions 220 and 232, respectively. Otherwise, silicide formation may occur during the formation of metal silicide layers during the processes of forming contacts 236, 238, 240 and / or metallization layer 242. RPO layers 222 and 234 may optionally be referred to as silicide barrier layers or silicide alignment blocks.

[0061] The gate structures 246 and 254 of NMOS transistor 214 and PMOS transistor 216 may each include polysilicon, one or more metals (e.g., tungsten (W), cobalt (Co), titanium (Ti)) and / or one or more high-k materials (e.g., hafnium oxide (HfO)). xOther examples. In some embodiments, the gate structure 246 of the NMOS transistor 214 includes one or more n-type work function materials for tuning the work function of the NMOS transistor 214. In some embodiments, the gate structure 254 of the PMOS transistor 216 includes one or more p-type work function materials for adjusting the work function of the PMOS transistor 216.

[0062] Figure 2C Example 260 illustrates a structural embodiment of a semiconductor device 262, which may include a resistive sensor structure 202. The semiconductor device 262 may include a system-on-chip (SoC) device, a logic device such as a central processing unit (CPU) or graphics processing unit (GPU), a memory device (e.g., a high bandwidth memory (HBM) device), a CMOS image sensing device, and / or other types of semiconductor devices.

[0063] like Figure 2C As shown, semiconductor device 262 includes substrate 264. Substrate 264 may correspond to a portion of a semiconductor wafer on which semiconductor device 262 is formed. Substrate 264 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, or another type of semiconductor substrate. Substrate 264 may extend in semiconductor device 262 along the x-direction and / or y-direction (not shown).

[0064] Device 268 may be contained within and / or on substrate 264. Device 268 includes transistors (e.g., planar transistors, fin field-effect transistors (finFETs), gate all-around (GAA) transistors), pixel sensors, capacitors, resistors, sensors, photodetectors, transceivers, transmitters, receivers, optical circuitry, and / or other types of semiconductor devices. In some embodiments, NMOS transistors 214 and / or PMOS transistors 216 controlling gates 212a-212n are also contained within and / or on substrate 264. Alternatively and additionally, NMOS transistors 214 and / or PMOS transistors 216 controlling gates 212a-212n may be contained in one or more dielectric layers on substrate 264.

[0065] A dielectric layer 270 is contained on the substrate 264. The dielectric layer 270 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 270 includes one or more dielectric materials that allow portions of the substrate 264 to be selectively etched or undisturbed and / or electrically isolate devices 268 within and / or on the substrate 264. The dielectric layer 270 includes silicon nitride (Si). x N y ), oxides (e.g., silicon oxide (SiO) x (and / or another oxide material) and / or another type of dielectric material. The dielectric layer 270 may extend in the semiconductor device 262 along the x-direction and / or y-direction (not shown).

[0066] The semiconductor device 262 also includes a plurality of dielectric layers disposed in a direction generally perpendicular to the substrate 264 (e.g., the z-direction). The dielectric layers may include a plurality of dielectric layers 272 and a plurality of ESLs 274 disposed alternately in the z-direction. The dielectric layers 272 and ESLs 274 may extend in the x-direction and / or y-direction (not shown) in the semiconductor device 262.

[0067] Dielectric layers 272 may each include oxides (e.g., silicon oxide (SiO2)). x The dielectric layer 272 comprises an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogensilsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, the dielectric layer 272 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous phase fluorinated carbon (aC) x F y), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silica (SiO2). x Examples include ).

[0068] ESL 274 may each include silicon nitride (Si) x N y The dielectric material may be silicon carbide (SiC), silicon oxynitride (SiON), or another suitable dielectric material. In some embodiments, dielectric layers 272 and ESL 274 comprise different dielectric materials to provide etching selectivity, enabling the formation of various structures.

[0069] The NMOS transistor 214, controlling gates 212a-212n, may include a gate structure 246 between source / drain regions 276. The PMOS transistor 216, controlling gates 212a-212n, may similarly include a gate structure 254 between source / drain regions 276. One or more “source / drain regions” may individually or collectively refer to the source or drain, depending on the context. The active region 244 of the NMOS transistor 214 may include a portion of a substrate 264 between the source / drain regions 276 and beneath the gate structure 246. The active region 252 of the PMOS transistor 216 may include a portion of a substrate 264 between the source / drain regions 276 and beneath the gate structure 254.

[0070] A gate dielectric layer 278 may be contained between the gate structure 246 and the substrate 264. Similarly, a gate dielectric layer 278 may be contained between the gate structure 254 and the substrate 264. In some embodiments, the gate dielectric layer 278 comprises a low-k dielectric material, such as silicon oxide (SiO2). x In some embodiments, the gate dielectric layer 278 comprises a high dielectric constant dielectric material, such as hafnium oxide (HfO). x ).

[0071] Sidewall separator 280 may be included on the sidewall of gate structure 246 to provide electrical isolation for gate structure 246, etc. Similarly, sidewall separator 280 may be included on the sidewall of gate structure 254 to provide electrical isolation for gate structure 254, etc. Sidewall separator 280 may include silicon oxide (SiO2). x ), silicon nitride (Si xN y ), silicon oxycarbonate (SiOC), silicon oxycarbonitrile (SiOCN) and / or other suitable materials.

[0072] The source / drain region 276 of the NMOS transistor 214 may be electrically coupled and / or physically coupled to the contacts 248 and 250 of the NMOS transistor 214. The source / drain region 276 of the PMOS transistor 216 may be electrically coupled and / or physically coupled to the contacts 256 and 258 of the PMOS transistor 216. Contacts 248, 250, 256, and 258 may each include a contact via, a contact plug, and / or another type of contact structure. Contacts 248, 250, 256, and 258 may include cobalt (Co), ruthenium (Ru), and / or another electrically conductive material or metallic material. In some embodiments, one or more substrates may be included on the sidewalls of contacts 248, 250, 256, and / or 258. The liner may include a barrier layer, an adhesive layer or glue layer and / or another type of liner, wherein the barrier layer is included to prevent or minimize the diffusion of material from contacts 248, 250, 256 and / or 258 to the surrounding dielectric layer, and the adhesive layer is included to facilitate adhesion between contacts 248, 250, 256 and / or 258 and the surrounding dielectric layer. Example materials for the liner include titanium nitride (TiN), tantalum nitride (TaN) and / or another suitable liner material.

[0073] Gate structures 246 and 254 may each be electrically and / or physically coupled to gate contact 282. Gate contact 282 may include contact vias, contact plugs, and / or other types of contact structures. Gate contact 282 may each include cobalt (Co), ruthenium (Ru), and / or another electrically conductive material or metallic material. One or more liner layers may be included on the sidewalls of gate contact 282. The liner layer may include a barrier layer, an adhesive layer, or a glue layer and / or another type of liner, wherein the barrier layer is included to prevent or minimize material diffusion from gate contact 282 to the surrounding dielectric layer, and the adhesive layer is included to facilitate adhesion between gate contact 282 and the surrounding dielectric layer. Example materials for the liner layer include titanium nitride (TiN), tantalum nitride (TaN), and / or another suitable liner material.

[0074] like Figure 2CAs further shown, metallization layers 240 and 242 may extend in the z-direction through dielectric layers 272 and ESL 274. Metallization layers 240 and 242 may each include trenches, vias, interconnects, and / or combinations of other types of conductive structures. Metallization layers 240 and 242 may each include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of electrically conductive materials. In some embodiments, one or more liner layers are contained between metallization layers 240, 242 and the surrounding dielectric layer. The one or more liner layers may include barrier liner layers, adhesive liner layers, and / or another type of liner layer. Example materials for one or more liner layers include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0075] As mentioned above, providing Figure 2A-2C For example. Other examples can be found with reference to... Figure 2A-2C The differences mentioned above.

[0076] Figure 3A and 3B This is a diagram of an example operational configuration of the resistance sensor structure 202 described herein. Figure 3A An exemplary configuration 300 is shown, in which the control gates 212a-212n of the resistance sensor structure 202 are all in the off state. Therefore, the selectable thin-film resistors 210a-210n of the resistance sensor structure 202 are activated, and the current path 302 through the resistance sensor structure 202 passes through the selectable thin-film resistors 210a-210n in addition to the main thin-film resistor 208. Therefore, the total resistance (and total TCR) of the resistance sensor structure 202 corresponds to the sum of the individual resistances (and individual TCRs) of the selectable thin-film resistors 210a-210n and the main thin-film resistor 208.

[0077] Figure 3B An exemplary configuration 304 is shown, in which all control gates 212a-212c of the resistance sensor structure 202 are in the ON state and control gates 212d-212n of the resistance sensor structure 202 are in the OFF state. Therefore, the selectable thin-film resistors 210a-210c of the resistance sensor structure 202 are deactivated, while the selectable thin-film resistors 210d-210n of the resistance sensor structure 202 are activated. A voltage input 306 can be applied to the control gates 212a-212c to switch them to the ON state. The voltage input 306 may include a voltage applied to the NMOS transistor 214 and an inverted voltage applied to the PMOS transistor 216.

[0078] In the exemplary configuration 304, the current path 302 through the resistive sensor structure 202 passes through optional thin-film resistors 210d-210n in addition to the main thin-film resistor 208, and bypasses optional thin-film resistors 210a-210c, such that the current path 302 passes through control gates 212a-212c. Therefore, the total resistance (and total TCR) of the resistive sensor structure 202 alone corresponds to the sum of the individual resistances (and individual TCRs) of the optional thin-film resistors 210d-210n and the main thin-film resistor 208.

[0079] In this way, Figure 3A and Figure 3B The example operating configuration shown illustrates the use of selectable thin-film resistors 210d-210n to tune the resistance and / or TCR of the resistance sensor structure 202. Figure 3A and Figure 3B The example operating configuration shown is merely an example, and other example operating configurations for tuning the resistor and / or TCR of the resistor sensor structure 202 are also within the scope of this disclosure.

[0080] As mentioned above, providing Figure 3A and Figure 3B For example. Other examples can be found with reference to... Figure 3A and Figure 3B The differences mentioned above.

[0081] Figures 4A-4D This is a diagram of an example 400 of the formation of the resistance sensor structure 202 described herein. In some embodiments, a combination of... Figures 4A-4D One or more of the semiconductor processing techniques and / or operations described herein are used to form one or more of the other resistive sensor structures described herein. In some embodiments, one or more of semiconductor processing stations (e.g., 102-112) and / or wafer / die transfer stations 114 are used to perform the combination. Figures 4A-4D The one or more semiconductor processing operations described herein. In some embodiments, combined with... Figures 4A-4D One or more of the semiconductor processing operations are performed using another semiconductor processing machine.

[0082] like Figure 4AAs shown, the active region 220 of the primary thin-film resistor 208, the active region 232 of the selectable thin-film resistors 210a-210n, the active region 244 of the NMOS transistors 214 controlling gates 212a-212n, and the active region 252 of the PMOS transistors 216 controlling gates 212a-212n can be formed. In some embodiments, the active regions 220, 232, 244, and / or 252 are formed in the substrate of the semiconductor device (e.g., the substrate 264 of the semiconductor device 262). In some embodiments, the deposition stage 102 can be used with PVD technology, ALD technology, CVD technology, epitaxial technology, oxidation technology, bonding technology, etc. Figure 1 The other type of deposition technique and / or another suitable deposition technique are used to deposit the active regions 220, 232, 244 and / or 252.

[0083] like Figure 4B As shown, RPO layers 222 and 234 can be formed above active regions 220 and 232, respectively. In some embodiments, the deposition stage 102 can be used with PVD, ALD, CVD, oxidation, or bonding technologies. Figure 1 The other type of deposition technique and / or another suitable deposition technique are used to deposit RPO layers 222 and 234. In some embodiments, a planarization station 110 can be used to planarize RPO layers 222 and 234.

[0084] like Figure 4B As further shown, gate structure 246 of NMOS transistor 214 and gate structure 254 of PMOS transistor 216 can be formed. Deposition stage 102 and / or plating stage 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, combined with the above... Figure 1 The other deposition technique and / or another suitable deposition method are used to deposit gate structures 246 and / or 254.

[0085] like Figure 4C As shown, contacts 224, 226, 236, 238, 248, 250, 256 and / or 258 can be formed. The deposition equipment 102 and / or plating equipment 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and bonding technology. Figure 1 The other deposition technique and / or another suitable deposition technique are used to deposit contacts 224, 226, 236, 238, 248, 250, 256 and / or 258.

[0086] like Figure 4D As shown, metallization layers 228, 230, 240, and / or 242 can be formed. The deposition equipment 102 and / or plating equipment 112 can be used with CVD, PVD, ALD, electroplating, and in combination with the above-mentioned technologies. Figure 1 The other deposition technique and / or other suitable deposition techniques are used to deposit metallization layers 228, 230, 240 and / or 242.

[0087] As mentioned above, providing Figures 4A-4D For example. Other examples can be found with reference to... Figures 4A-4D The differences mentioned above.

[0088] Figure 5A-5I This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 5A Example 500 of a circuit implementation of a resistance sensor structure 502 is shown. The resistance sensor structure 502 is similar to resistance sensor structure 202 in that it includes one or more inputs 504a, 504b, one or more sensing terminals 506a, 506b, a main thin-film resistor 508, a plurality of selectable thin-film resistors 510a-510n electrically connected in series with and in series with the main thin-film resistor 508, and a plurality of control gates 512a-512n electrically connected in series with each other. Each of the control gates 512a-512n is electrically connected in parallel with a corresponding selectable thin-film resistor 510a-510n, and the control gates 512a-512n can be used to selectively activate or deactivate one or more selectable thin-film resistors 510a-510n in a manner similar to that of resistance sensor structure 202. However, unlike the transmission gate in the resistive sensor structure 502, the control gates 512a-512n include programmable control gates (e.g., electrically programmable control gates). Figure 5B-5I Various example circuit and / or structural implementations of a programmable control gate are illustrated. In some implementations, the resistive sensor structure may include a combination of a programmable control gate and a transfer gate for controlling an associated, selectable thin-film resistor of the resistive sensor structure.

[0089] like Figure 5B As shown, example 514 of the circuit implementation of the control gate 512 includes an NMOS switch. The NMOS switch may include an NMOS transistor, and the gate of the NMOS transistor may be coupled to a control input for selectively switching the NMOS transistor between an on-state and an off-state. Figure 5C As shown, example 516 of the circuit implementation of the control gate 512 includes a PMOS switch. The PMOS switch may include a PMOS transistor, and the gate of the PMOS transistor may be coupled to a control input for selectively switching the PMOS transistor between an on state and an off state. Figure 5DAs shown, example 518 of the circuit implementation of the control gate 512 includes a negative-positive-negative (NPN) switch. The NPN switch may include an NPN bipolar junction transistor (BJT), and the base of the NPN BJT may be coupled to a control input. Figure 5E As shown, Example 520 of the circuit implementation of the control gate 512 includes a positive-negative-positive (PNP) switch. The PNP switch may include a PNP BJT, and the base of the PNP BJT may be coupled to a control input.

[0090] Figure 5F Example 522 of a structural embodiment of a resistance sensor structure 502 is shown, wherein the control gates 512a-512n of the resistance sensor structure 502 are implemented as floating gate transistors (e.g., flash memory transistors). The main thin-film resistor 508 includes an active region 524, an RPO layer 526, and contacts 528 and 530 coupled to metallization layers 532 and 534, respectively. Alternative thin-film resistors 510a-510n each include an active region 536, an RPO layer 538, and contacts 540 and 542 coupled to metallization layers 544 and 546, respectively.

[0091] Each of the control gates 512a-512n includes active regions 548a and 548b, word line structures 550a and 550b, control gate structures 552a and 552b, and erase gate structure 554. Active regions 548a and 548b may be located on opposite sides of the erase gate structure 554. Word line structure 550a and control gate structure 552a may be located above active region 548a, and word line structure 550b and control gate structure 552b may be located above active region 548b.

[0092] The control gate 512a can be electrically coupled to the selectable thin-film resistor 510a in parallel via the active region 536 of the selectable thin-film resistor 510a and via the active regions 548a and 548b of the control gate 512a. The control gates 512b-512n can be electrically coupled to the selectable thin-film resistors 510b-510n in a similar manner.

[0093] exist Figure 5FIn Example 522 shown, active regions 524, 536, 548a, and 548b may each be located in oxide diffusion within the substrate of the semiconductor device. The word line structures 550a and 550b of the control gates 512a-512n, the control gate structures 552a and 552b, and the erase gate structure 554 may include polysilicon structures, metal structures, and / or another type of electrically conductive structure.

[0094] Figure 5G Example 556 of a structural embodiment of a resistance sensor structure 502 is shown, wherein the control gates 512a-512n of the resistance sensor structure 502 are implemented as floating gate transistors. Except that the primary thin-film resistor 508 and optional thin-film resistors 510a-510n in example 556 of the structural embodiment of the resistance sensor structure 502 can be included in the interconnect structure or interconnect region (e.g., the back-end region) of the semiconductor device, example 556... Figure 5F Similar to Example 522. Therefore, in an example of the structural embodiment of the resistor sensor structure 502, the active region 524 of the main thin-film resistor 508 and the active regions 536 of the optional thin-film resistors 510a-510n may include a polysilicon resistive layer. Therefore, the RPO layer 526 can be omitted. The main thin-film resistor 508, the optional thin-film resistors 510a-510n, and the control gates 512a-512n can be interconnected via metallization layers 532, 534, 544, and 546 in the interconnect structure of the semiconductor device. For example, the main thin-film resistor 508 can be electrically connected in series with the optional thin-film resistor 510n via metallization layers 532 and 546, and the optional thin-film resistor 510n can be electrically connected in series with the optional thin-film resistor 510b via metallization layers 544 and 546, and so on. As another example, an optional thin-film resistor 510a can be electrically connected in parallel with the control gate 512a via metallization layers 544 and 546. Control gates 512a-512n can also be electrically connected in series via metallization layers 544 and 546. Control gates 512a-512n can be electrically connected to metallization layer 544 via contact 558, and control gates 512a-512n can be electrically connected to metallization layer 546 via contact 560.

[0095] Figure 5HExample 562 of a structural embodiment of the resistance sensor structure 502 is shown. Except that the control gates 512a-512n of the resistance sensor structure 502 are implemented by the resistive random access memory (RRAM) cell 564 in example 562 of the structural embodiment of the resistance sensor structure 502, example 562 of the structural embodiment of the resistance sensor structure 502 is similar to example 556 of the structural embodiment of the resistance sensor structure 502.

[0096] Figure 5I Example 566 illustrates a structural embodiment of a semiconductor device 568 that may include a resistive sensor structure 502. The semiconductor device 568 may include multiple dielectric layers 570 (similar to dielectric layer 272) and multiple ESLs 572 (similar to ESL 274), wherein the resistive sensor structure 502 may be included. A selectable thin-film resistor 510 of the resistive sensor structure 502 may be electrically coupled to metallization layers 544 and 546 extending through the dielectric layers 570 and ESLs 572. Metallization layers 544 and 546 electrically connect the selectable thin-film resistor 510 to a control gate 512, which may be implemented as the RRAM structure 564 in example 562. The RRAM structure 564 includes a bottom electrode (BE) 574, a switching layer 576 on the bottom electrode 574, and a top electrode (TE) 578 on the switching layer 576. A voltage or another type of electrical input can be applied to the switching layer 576 to modify the resistance of the switching layer 576, thereby selectively activating or deactivating the selectable thin-film resistor 510.

[0097] In some embodiments, the switching layer 576 comprises a transition metal oxide (TMO), such as hafnium oxide (HfO). x Titanium oxide (TiO) x The switching layer 576 comprises chalcogenides, such as silver selenide (AgSe) and / or copper sulfide (CuS) and other examples. In some embodiments, the switching layer 576 comprises another type of material.

[0098] As mentioned above, providing Figure 5A-5I For example. Other examples can be found with reference to... Figure 5A-5I The differences mentioned above.

[0099] Figures 6A-6C This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 6AExample 600 of a structural embodiment of a resistance sensor structure 602 is shown. The resistance sensor structure 602 includes one or more inputs 604a, 604b and one or more sensing terminals 606a, 606b. The resistance sensor structure 602 can be configured as a current meter (e.g., a sensor configured to sense the amplitude of current on inputs 604a, 604b based on the resistance of the resistance sensor structure 602), a thermal sensor (e.g., a sensor configured to sense temperature based on the current in inputs 604a, 604b), and / or another type of resistance-based sensor.

[0100] like Figure 6A As shown, the resistance sensor structure 602 includes a main thin-film resistor 608 and a resistance trimming structure 610 electrically coupled to the main thin-film resistor 608. The resistance trimming structure 610 includes a plurality of resistance trimming pads 612 connected in series. Each of the resistance trimming pads 612 is electrically coupled to the main thin-film resistor 608 via an electrically conductive sensing line 614. The length of the resistance trimming structure 610 (in...) Figure 6A The size indicated by D1 can be smaller than the length of the main thin-film resistor 608 (in Figure 6B The middle indicator is size D2).

[0101] The resistor trimming pads 612 can be used to tune or fine-tune the total resistance (or total TCR) of the resistor sensor structure 602. Specifically, the electrical continuity between the resistor trimming pads 612 can be modified to alter the effective length of the resistor sensor structure 602. Burn-out regions 616 are located between adjacent resistor trimming pads 612. When the burn-out regions 616 are intact, they provide electrical continuity between adjacent resistor trimming pads 612. An input current can be supplied through the sensing terminal 606a to cause one or more burn-out regions 616 to be burned out or damaged, resulting in an electrical break between adjacent resistor trimming pads 612. Breaking the electrical continuity between two or more resistor trimming pads 612 increases the effective length of the resistor sensor structure 602 because current propagates a longer distance through the main thin-film resistor 608 between the inputs 604a, 604b and the sensing terminals 606a, 606b compared to when all resistor trimming pads 612 are electrically connected. Combination Figure 7A and Figure 7B An example of the current path in the resistive sensor structure 602 is shown and described.

[0102] Figure 6BExample 618 of a resistive sensor structure 602 is shown, including a control gate 620 electrically connected to a resistor trimming pad 612. The control gate 620 can be used to selectively provide input current to specific resistor trimming pads 612, causing a burn-out region 616 between adjacent resistor trimming pads 612 to burn out and disconnect. In example 618, the control gate 620 is implemented as a transfer gate, each transfer gate including an NMOS transistor 622 and a PMOS transistor 624.

[0103] Figure 6C Example 626 illustrates a structural embodiment 620 of the control gate 620 of the resistance sensor structure 602. (See example 626.) Figure 6C As shown, the control gate 620 may include an NMOS transistor 622 and a PMOS transistor 624. The NMOS transistor 622 may be similar to the NMOS transistor 214, as it may include an active region 628 and a gate structure 630. The PMOS transistor 624 may be similar to the PMOS transistor 216, as it may include an active region 632 and a gate structure 634. The NMOS transistor 622 and the PMOS transistor 624 may be electrically coupled to the sensing terminal 606a via the metallization layer 636 and to the resistor trimming pad 612 via the metallization layer 638.

[0104] As mentioned above, providing Figures 6A-6C As an example. Other examples may be found related to... Figures 6A-6C The differences mentioned above.

[0105] Figure 7A and Figure 7B This is a diagram of an example operational configuration of the resistance sensor structure 602 described herein. Figure 7A An exemplary configuration 700 is shown, in which the burn-out region 616 between the resistor trimming pads 612 is intact. Therefore, the effective length of the resistor sensor structure 602 (in...) Figure 7A The value (D3) corresponds to the distance of the current path 702 between one or more of the inputs 604a, 604b and sensing terminal 606a.

[0106] Figure 7B An exemplary configuration 704 is shown, wherein the burn-out region 616 between two or more resistor trimming pads 612 (e.g., between resistor trimming pads 612a and 612b) is intact, and the burn-out region 616 between two or more resistor trimming pads 612 (e.g., between resistor trimming pads 612c and 612d) is broken. Therefore, the effective length of the resistance sensor structure 602 (in...) Figure 7BThe length (represented as size D4) can be greater than the effective length in the exemplary configuration 700, resulting in a larger total resistance of the resistance sensor structure 602.

[0107] As mentioned above, providing Figure 7A and Figure 7B For example. Other examples can be found with reference to... Figure 7A and Figure 7B The differences mentioned above.

[0108] Figure 8A and Figure 8B This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 8A Example 800 of an embodiment of a resistance sensor structure 802 is shown. The resistance sensor structure 802 is similar to the resistance sensor structure 602 and includes one or more inputs 804a, 804b, one or more sensing terminals 806a, 806b, a main thin-film resistor 808, a resistance trimming structure 810 including a plurality of resistance trimming pads 812 coupled to the main thin-film resistor 808 via electrically conductive sensing lines 814, and burn-out regions 816 between adjacent resistance trimming pads 812. However, the control gate 818 of the resistance sensor structure 802 differs from the control gate 620 of the resistance sensor structure 602 in that the control gate 818 includes a programmable gate structure similar to the control gates 512a-512n of the resistance sensor structure 502. The control gate 818 can be combined with... Figure 5A-5I One or more examples of programmable control gates are shown and described to implement this.

[0109] Figure 8B Example 820 illustrates a structural embodiment of the control gate 818 of the resistance sensor structure 802. (See example 820.) Figure 8B As shown, the control gate 818 may include a floating gate transistor structure, which includes active regions 822a and 822b, word line structures 824a and 824b, control gate structures 826a and 826b, and an erase gate structure 828. The control gate 818 can be electrically coupled to the sensing terminal 806a through the metallization layer 830, and can be electrically coupled to the resistor trimming pad 812 through the metallization layer 832.

[0110] As mentioned above, providing Figure 8A and Figure 8B For example. Other examples can be found with reference to... Figure 8A and Figure 8B The differences mentioned above.

[0111] Figures 9A-9C This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 9AExample 900 of a structural embodiment of a resistance sensor structure 902 is shown. The resistance sensor structure 902 is similar to the resistance sensor structure 602 and includes one or more inputs 904a, 904b, one or more sensing terminals 906a, 906b, a main thin-film resistor 908, and a resistance trimming structure 910 including a plurality of resistance trimming pads 912 coupled to the main thin-film resistor 908 via electrically conductive sensing lines 914. However, the burn-out region between adjacent resistance trimming pads 912 is omitted in the resistance sensor structure 902.

[0112] like Figure 9B As shown in Example 916, the conductivity between the resistor trimming pads 912 and the sensing terminal 906a is directly controlled by the control gate 918. Each of the resistor trimming pads 912 can be electrically coupled to the associated control gate 918, which is implemented as a transfer gate including an NMOS transistor 920 and a PMOS transistor 922, similar to control gates 212a-212n. Instead of using the control gate 918 to selectively damage the burn-out region to control the effective length of the resistance sensor structure 902, the control gate 918 can be activated to allow current to flow through the associated resistor trimming pads 912 from the primary thin-film resistor 908 to the sensing terminal 906a to control the effective length of the resistance sensor structure 902. Therefore, the resistor trimming structure 910 is reprogrammable, allowing the total resistance and / or total TCR of the resistance sensor structure 902 to be programmed multiple times.

[0113] Figure 9C Example 924 illustrates a structural embodiment of the control gate 918 of the resistance sensor structure 902. (See example 924.) Figure 9C As shown, the control gate 918 may include an NMOS transistor 920 and a PMOS transistor 922. The NMOS transistor 920 may be similar to the NMOS transistor 214, as it may include an active region 926 and a gate structure 928. The PMOS transistor 922 may be similar to the PMOS transistor 216, as it may include an active region 930 and a gate structure 932. The NMOS transistor 920 and the PMOS transistor 922 are electrically coupled to the sensing terminal 906a via the metallization layer 934 and to the resistance trimming pad 912 via the metallization layer 936.

[0114] As mentioned above, providing Figures 9A-9C For example. Other examples can be found with reference to... Figures 9A-9C The differences mentioned above.

[0115] Figure 10A and Figure 10B This is a diagram of an example operational configuration of the resistance sensor structure 902 described herein. Figure 10AAn exemplary configuration 1000 is shown, in which the resistance trimming pad 912e (among resistance trimming pads 912a-912f) is activated via the associated control gate 918. Therefore, the effective length of the resistance sensor structure 902 (in...) Figure 10A The value (D5) corresponds to the distance of the current path 1002 between one or more of the inputs 904a, 904b and sensing terminals 906a via the resistor trimming pad 912e.

[0116] Figure 10B An exemplary configuration 1004 is shown, in which the resistance trimming pad 912b (among resistance trimming pads 912a-912f) is activated via the associated control gate 918. Therefore, the effective length of the resistance sensor structure 902 (in...) Figure 10B The size D6 indicates the distance of the current path 1002 between one or more of the inputs 904a, 904b and sensing terminals 906a via the resistor trimming pad 912b, which may be greater than the effective length of the resistor sensor structure 902 in the exemplary configuration 1000.

[0117] As mentioned above, providing Figure 10A and Figure 10B For example. Other examples can be found with reference to... Figure 10A and Figure 10B The differences mentioned above.

[0118] Figure 11A and Figure 11B This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 11A Example 1100 of an embodiment of a resistance sensor structure 1102 is shown. The resistance sensor structure 1102 is similar to the resistance sensor structure 902 and includes one or more inputs 1104a, 1104b, one or more sensing terminals 1106a, 1106b, a main thin-film resistor 1108, a resistance trimming structure 1110 including a plurality of resistance trimming pads 1112 coupled to the main thin-film resistor 1108 via electrically conductive sensing lines 1114, and a control gate 1116 coupled to the resistance trimming pads 1112. However, the control gate 1116 of the resistance sensor structure 1102 differs from the control gate 918 of the resistance sensor structure 902 in that the control gate 1116 includes a programmable gate structure similar to the control gates 512a-512n of the resistance sensor structure 502. The control gate 1116 can be combined with... Figure 5A-5I One or more examples of programmable control gates are shown and described to implement this.

[0119] Figure 11B Example 1118 illustrates a structural embodiment of the control gate 1116 of the resistance sensor structure 1102. (See example 1118.) Figure 11BAs shown, the control gate 1116 may include a floating gate transistor structure, which includes active regions 1120a and 1120b, word line structures 1122a and 1122b, control gate structures 1124a and 1124b, and an erase gate structure 1126. The control gate 1116 can be electrically coupled to the sensing terminal 1106a through the metallization layer 1128, and can be electrically coupled to the resistor trimming pad 1112 through the metallization layer 1130.

[0120] As mentioned above, providing Figure 11A and Figure 11B For example. Other examples can be found with reference to... Figure 11A and Figure 11B The differences mentioned above.

[0121] Figures 12A-12C This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 12A Example 1200 of a circuit implementation of a resistance sensor structure 502 is shown. The resistance sensor structure 1202 is similar to the resistance sensor structure 202, wherein the resistance sensor structure 1202 includes one or more inputs 1204a, 1204b, one or more sensing terminals 1206a, 1206b, a main thin-film resistor 1208, a plurality of selectable thin-film resistors 1210a-1210n and 1212a-1212m electrically connected in series with and in series with the main thin-film resistor 1208, and a plurality of control gates 1214a-1214x electrically connected in series with each other. Each of the control gates 1214a-1214x is electrically connected in parallel with a corresponding selectable thin-film resistor, and the control gates 1214a-1214x can be used to selectively activate or deactivate one or more selectable thin-film resistors in a manner similar to that of the resistance sensor structure 202. Furthermore, the control gate may be implemented as a transmission gate, each of which includes an NMOS transistor 1216 (e.g., similar to NMOS transistor 214) electrically coupled in parallel with the PMOS transistor 1218 (e.g., similar to PMOS transistor 216).

[0122] However, the selectable thin-film resistors 1210a-1210n affect the overall TCR of the resistance sensor structure 1202 differently than the selectable thin-film resistors 1212a-1212m. Specifically, activating the selectable thin-film resistors 1210a-1210n via the associated control gates 1214a-1214x increases the overall TCR of the resistance sensor structure 1202, while activating the selectable thin-film resistors 1212a-1212m via the associated control gates 1214a-1214x decreases the overall TCR of the resistance sensor structure 1202. The more selectable thin-film resistors 1210a-1210n that are activated, the greater the increase in the overall TCR of the resistance sensor structure 1202. Conversely, the more selectable thin-film resistors 1212a-1212m that are activated, the greater the decrease in the overall TCR of the resistance sensor structure 1202.

[0123] Figure 12B Example 1220 of a structural embodiment of the resistance sensor structure 1202 is shown. For example... Figure 12B As shown, example 1220 of the structural embodiment of the resistance sensor structure 1202 can be similar to example 218 of the structural embodiment of the resistance sensor structure 202. For example, the main thin-film resistor 1208 includes an active region 1222, contacts 1224 and 1226, and metallization layers 1228 and 1230, which are similar to the active region 220, contacts 224 and 226, and metallization layers 228 and 230 of the main thin-film resistor 208, respectively. Alternative thin-film resistors 1210a-1210n and 1212a-1212m can each include an active region 1232, contacts 1234 and 1236, and metallization layers 1238 and 1240, which are similar to the active region 232, contacts 236 and 238, and metallization layers 240 and 242 of the alternative thin-film resistors 210a-210n, respectively. Each of the control gates 1214 includes an NMOS transistor 1216 and a PMOS transistor 1218, wherein the NMOS transistor 1216 includes an active region 1242, a gate structure 1244, and contacts 1246 and 1248, and the PMOS transistor 1218 includes an active region 1250, a gate structure 1252, and contacts 1256 and 1258.

[0124] However, the active region 1232 of the optional thin-film resistors 1210a-1210n includes one or more materials that enhance TCR. Examples of materials that enhance TCR include platinum (Pt), titanium nitride (TiN), and ruthenium oxide (RuO₂). xExamples include tantalum (Ta) and / or nickel-chromium (NiCr). Conversely, the active region 1232 of the alternative thin-film resistors 1212a-1212m includes one or more materials that reduce TCR. Examples of materials that reduce TCR include tantalum nitride (TaN), nickel-chromium-aluminum (NiCrAl) alloys, copper-nickel (CuNi) alloys, and / or binary and ternary oxides (e.g., indium tin oxide (ITO) and / or zinc-doped aluminum oxide (AZO)).

[0125] The active regions 1232 of the selectable thin-film resistors 1210a-1210n are connected in series. The active regions 1232 of the selectable thin-film resistors 1212a-1212m are connected in series. The active region 1222 of the main thin-film resistor 1208 is coupled in series with the active regions 1232 of the selectable thin-film resistors 1210a-1210n and 1212a-1212m. Each of the first subset of control gates 1214a-1214x is coupled in parallel with a corresponding one of the selectable thin-film resistors 1210a-1210n. Each of the second subset of control gates 1214a-1214x is coupled in parallel with a corresponding one of the selectable thin-film resistors 1212a-1212m. The control gates 1214a-1214x are also coupled in series with the main thin-film resistor 1208.

[0126] Figure 12C Example 1260 illustrates a structural embodiment of a semiconductor device 1262 that may include a resistance sensor structure 1202. The semiconductor device 1262 may include a substrate 1264 and multiple dielectric layers 1266, 1268, and 1270. The resistance sensor structure 1202 may include a primary thin-film resistor 1208, which may include one or more resistive segments 1272 and 1274 vertically arranged within the semiconductor device 1262. In some embodiments, segment 1272 is a segment that reduces the resistance coefficient (TCR), and segment 1274 is a segment that increases the TCR. The primary thin-film resistor 1208 is electrically coupled to contacts 1224 and 1226.

[0127] Optional thin-film resistor 1210 includes a material that increases TCR and is electrically coupled to a set of contacts 1234 and 1236. Optional thin-film resistor 1212 may be located between optional thin-film resistor 1210 and the main thin-film resistor 1208 and may include a material that reduces TCR. Optional thin-film resistor 1212 may be electrically coupled to another set of contacts 1234 and 1236.

[0128] As mentioned above, providing Figures 12A-12C For example. Other examples can be found with reference to... Figures 12A-12C The differences mentioned above.

[0129] Figure 13A and Figure 13B This is a diagram of an example operational configuration of the resistance sensor structure 1202 described herein. Figure 13A An exemplary configuration 1300 is shown, in which all control gates 1214a-1214x of the resistive sensor structure 1202 are in the ON state, and the associated current path 1302 passes through the resistive sensor structure 1202. The control gates 1214a-1214x can be switched to the ON state by applying a voltage input 1304 to the control gates 1214a-1214x.

[0130] When the control gates 1214a-1214x are in the ON state, the selectable thin-film resistors 1210a-1210n and 1212a-1212m of the resistance sensor structure 1202 are deactivated and bypassed. Therefore, the current path 1302 through the resistance sensor structure 1202 passes through the main thin-film resistor 1208 and then through the control gates 1214a-1214x. Consequently, the selectable thin-film resistors 1210a-1210n and 1212a-1212m do not contribute to the total TCR of the resistance sensor structure 1202.

[0131] Figure 13B An exemplary configuration 1306 is shown, in which only the control gates 1214a and 1214d of the resistance sensor structure 1202 are both in the ON state. Therefore, the selectable thin-film resistors 1210b-1210n of the resistance sensor structure 1202 are activated, and the selectable thin-film resistors 1212b-1212m of the resistance sensor structure 1202 are activated. Thus, in addition to the main thin-film resistor 1208, the current path 1302 also passes through the selectable thin-film resistors 1210b-1210n and through the selectable thin-film resistors 1212b-1212m. Therefore, the total TCR of the resistance sensor structure 1202 corresponds to the TCR of the main thin-film resistor 1208, as modified by the TCRs of the selectable thin-film resistors 1210b-1210n and 1212b-1212m.

[0132] As mentioned above, providing Figure 13A and Figure 13B For example. Other examples can be found with reference to... Figure 13A and Figure 13B The differences mentioned above.

[0133] Figures 14A-14H This is a diagram of example 1400 of the formation of the resistance sensor structure 1202 described herein. In some embodiments, a combination of and / or execution can be used. Figures 14A-14HOne or more of the semiconductor processing techniques and / or operations described herein are used to form one or more of the other resistive sensor structures described herein. In some embodiments, one or more of semiconductor processing stations (e.g., 102-112) and / or wafer / die transfer stations 114 are used to perform the combination. Figures 14A-14H One or more of the aforementioned semiconductor processing operations. In some embodiments, combined with Figures 14A-14H One or more of the semiconductor processing operations are performed using another semiconductor processing machine.

[0134] like Figure 14A As shown, a dielectric layer 1266 can be formed on top of a substrate 1264. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1 The dielectric layer 1266 is deposited using another type of deposition technique and / or another suitable deposition technique. The dielectric layer 1266 may be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 1266, a planarization station 110 may be used to planarize the dielectric layer 1266. In some embodiments, the thickness of the dielectric layer 1266 is included in the range of about 100 angstroms to about 300 angstroms. However, other values ​​in this range are within the range disclosed herein.

[0135] like Figure 14B As shown, a TCR reduction layer 1402 is formed on the dielectric layer 1266. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1 The other type of deposition technique and / or another suitable deposition technique are used to deposit the TCR reduction layer 1402. The TCR reduction layer 1402 may be deposited in one or more deposition operations. In some embodiments, after depositing the TCR reduction layer 1402, a planarization station 110 may be used to planarize the TCR reduction layer 1402. In some embodiments, the thickness of the TCR reduction layer 1402 is included in the range of about 400 angstroms to about 600 angstroms. However, other values ​​in this range are within the range disclosed herein.

[0136] like Figure 14CAs shown, the TCR reduction layer 1402 is etched to remove a portion of the TCR reduction layer 1402. In some embodiments, a pattern in the photoresist layer is used to etch the TCR reduction layer 1402. In these embodiments, a deposition stage 102 can be used to form the photoresist layer on the TCR reduction layer 1402. An exposure stage 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development stage 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching stage 108 can be used to etch the TCR reduction layer 1402 based on the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal stage can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the TCR reduction layer 1402.

[0137] like Figure 14D As shown, a TCR-increasing layer 1404 is formed on the dielectric layer 1266 and the TCR-reducing layer 1402. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1 The other type of deposition technique and / or another suitable deposition technique are used to deposit the TCR augmentation layer 1404. The TCR augmentation layer 1404 may be deposited in one or more deposition operations. In some embodiments, after depositing the TCR augmentation layer 1404, a planarization station 110 may be used to planarize the TCR augmentation layer 1404. In some embodiments, the thickness of the TCR augmentation layer 1404 is included in the range of about 1000 angstroms to about 1200 angstroms. However, other values ​​in this range are within the range disclosed herein.

[0138] like Figure 14EAs shown, the TCR increase layer 1404 is etched to remove a portion of the TCR increase layer 1404 on the TCR decrease layer 1402. In some embodiments, a pattern in the photoresist layer is used to etch the TCR increase layer 1404. In these embodiments, a deposition stage 102 can be used to form a photoresist layer on the TCR increase layer 1404. An exposure stage 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development stage 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching stage 108 can be used to etch the TCR increase layer 1404 based on the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal stage can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the TCR augmentation layer 1404.

[0139] like Figure 14E As shown, a portion of the TCR increase layer 1404 can be removed to define segments 1272 and 1274 of the main thin-film resistor 1208 of the resistance sensor structure 1202 (e.g., from the TCR decrease layer 1402 and the TCR increase layer 1404, respectively), define one or more optional thin-film resistors 1210 of the resistance sensor structure 1202 (e.g., from the TCR increase layer 1404), and / or define one or more optional thin-film resistors 1212 of the resistance sensor structure 1202 (e.g., from the TCR decrease layer 1402).

[0140] like Figure 14F As shown, a dielectric layer 1268 can be formed above the resistance sensor structure 1202. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1 The dielectric layer 1268 is deposited using another type of deposition technique and / or another suitable deposition technique. The dielectric layer 1268 may be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 1268, a planarization stage 110 may be used to planarize the dielectric layer 1268.

[0141] like Figure 14G As shown, dielectric layer 1270 can be formed on dielectric layer 1268. Deposition stage 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, and bonding technology. Figure 1The dielectric layer 1270 is deposited using another type of deposition technique and / or another suitable deposition technique. The dielectric layer 1270 may be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 1270, a planarization stage 110 may be used to planarize the dielectric layer 1270.

[0142] like Figure 14H As shown, contacts 1224, 1226, 1234, and / or 1236 can be formed. Deposition equipment 102 and / or plating equipment 112 can be used to bond the surfaces. Figure 1 The CVD, PVD, ALD, electroplating, other deposition techniques and / or other suitable deposition techniques are used to deposit contacts 1224, 1226, 1234 and / or 1236.

[0143] As mentioned above, providing Figures 14A-14H For example. Other examples can be found with reference to... Figures 14A-14H The differences mentioned above.

[0144] Figure 15A and Figure 15B This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 15A Example 1500 of an embodiment of a resistance sensor structure 1502 is shown. The resistance sensor structure 1502 is similar to the resistance sensor structure 1202 and includes one or more inputs 1504a, 1504b, one or more sensing terminals 1506a, 1506b, a main thin-film resistor 1508, multiple selectable thin-film resistors 1510a-1510n (e.g., resistors that increase TCR), multiple selectable thin-film resistors 1512a-1512m (e.g., resistors that decrease TCR), and multiple control gates 1514a-1514x. However, the control gates 1514a-1514x of the resistance sensor structure 1502 differ from those of the control gates 1214a-1214x of the resistance sensor structure 1202 in that the control gates 1514a-1514x include a programmable gate structure similar to the control gates 512a-512n of the resistance sensor structure 502. The control gates 1514a-1514x can be combined Figure 5A-5I One or more examples of programmable control gates are shown and described to implement this.

[0145] Figure 15B Example 1516 illustrates a structural embodiment of the control gates 1514a-1514x of the resistance sensor structure 1502. (See example 1516.) Figure 15BAs shown, each of the control gates 1514a-1514x may include a floating gate transistor structure, the floating gate transistor structure including active regions 1538a and 1538b, word line structures 1540a and 1540b, control gate structures 1542a and 1542b, and an erase gate structure 1544. The active regions 1528 of optional thin-film resistors 1510a-1510n are connected in series. The active regions 1528 of optional thin-film resistors 1512a-1512m are connected in series. The active region 1518 of the primary thin-film resistor 1508 is electrically coupled in series with the active regions 1528 of the optional thin-film resistors 1510a-1510n and the optional thin-film resistors 1512a-1512m. Each of the control gates 1514a-1514x in the first subset is electrically coupled in parallel to a corresponding one of the selectable thin-film resistors 1510a-1510n. Each of the control gates 1514a-1514x in the second subset is electrically coupled in parallel to a corresponding one of the selectable thin-film resistors 1512a-1512m. The control gates 1514a-1514x are also electrically coupled in series to the main thin-film resistor 1508.

[0146] As mentioned above, providing Figure 15A and Figure 15B For example. Other examples can be found with reference to... Figure 15A and Figure 15B The differences mentioned above.

[0147] Figures 16A-16C This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 16A Example 1600 illustrates an embodiment of a resistance sensor structure 1602. The resistance sensor structure 1602 is similar to the resistance sensor structure 1202 and includes one or more inputs 1604a, 1604b, one or more sensing terminals 1606a, 1606b, a primary thin-film resistor 1608, multiple selectable thin-film resistors 1610a-1610n (e.g., resistors that increase TCR), multiple selectable thin-film resistors 1612a-1612m (e.g., resistors that decrease TCR), and multiple control gates 1614a-1614x implemented as transfer gates, each of which includes an NMOS transistor 1616 electrically coupled in parallel with a PMOS transistor 1618.

[0148] Figure 16B Example 1620 of a structural implementation of the resistance sensor structure 1602 is shown. For example... Figure 16BAs shown, the structural implementation of the resistance sensor structure 1602 is similar to that of the resistance sensor structure 1202. For example, the main thin-film resistor 1608 includes an active region 1622, contacts 1624 and 1626, and metallization layers 1628 and 1630; each of the optional thin-film resistors 1610a-1610n and 1612a-1612m includes an active region 1632, contacts 1634 and 1636, and metallization layers 1638 and 1640; and each of the control gates 1614a-1614x includes an NMOS transistor 1616 (e.g., including an active region 1642, gate structure 1644, contacts 1646 and 1648) and a PMOS transistor 1618 (e.g., including an active region 1650, gate structure 1652, and contacts 1656 and 1658).

[0149] However, unlike the resistive sensor structure 1202, the active region 1622 of the main thin-film resistor 1608, the active regions 1632 of the selectable thin-film resistors 1610a-1610n, and the active regions 1632 of the selectable thin-film resistors 1612a-1612m are not directly connected, but are physically isolated. Instead, the main thin-film resistor 1608 is electrically coupled in series with the selectable thin-film resistors 1610a-1610n and the selectable thin-film resistors 1612a-1612m through metallization layers 1628, 1630, 1638, and / or 1640. The main thin-film resistor 1608 is also electrically coupled in series with the control gates 1614a-1614x through metallization layers 1628, 1630, 1638, and / or 1640. Each of the control gates 1614a-1614x in the first subset is electrically coupled in parallel to a corresponding one of the selectable thin-film resistors 1610a-1610n. Each of the control gates 1614a-1614x in the second subset is electrically coupled in parallel to a corresponding one of the selectable thin-film resistors 1612a-1612m.

[0150] Figure 16C Example 1660 illustrates a structural embodiment of a semiconductor device 1662 that may include a resistance sensor structure 1602. The semiconductor device 1662 may include a substrate 1664 and multiple dielectric layers 1666, 1668, and 1670. The resistance sensor structure 1602 may include a primary thin-film resistor 1608, which may include one or more resistive segments 1672 and 1674 vertically arranged within the semiconductor device 1662. In some embodiments, segment 1672 is a TCR-reducing segment and segment 1674 is a TCR-increasing segment. The primary thin-film resistor 1608 is electrically coupled to contacts 1624 and 1626.

[0151] The optional thin-film resistor 1610 includes a TCR-enhancing material and is electrically coupled to a set of contacts 1634 and 1636. An optional thin-film resistor 1612 may be located between the optional thin-film resistor 1610 and the primary thin-film resistor 1608, and may include a TCR-reducing material. The optional thin-film resistor 1612 may be electrically coupled to another set of contacts 1634 and 1636. The primary thin-film resistor 1608, the optional thin-film resistor 1610, and the optional thin-film resistor 1612 are physically isolated from each other in the semiconductor device 1662, such as... Figure 16C Example 1660 is shown in the example.

[0152] As mentioned above, providing Figures 16A-16C For example. Other examples can be found with reference to... Figures 16A-16C The differences mentioned above.

[0153] Figure 17A-17I This is a diagram of example 1700 of the formation of the resistance sensor structure 1602 described herein. In some embodiments, a combination can be used and / or performed. Figure 17A-17I One or more of the semiconductor processing techniques and / or operations described herein are used to form one or more of the other resistive sensor structures described herein. In some embodiments, one or more of semiconductor processing stations (e.g., 102-112) and / or wafer / die transfer stations 114 are used to perform the combination. Figure 17A-17I One or more of the aforementioned semiconductor processing operations. In some embodiments, combined with Figure 17A-17I One or more of the semiconductor processing operations are performed using another semiconductor processing machine.

[0154] like Figure 17A As shown, dielectric layer 1666 can be formed above substrate 1264. Deposition stage 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, and bonding technology. Figure 1 The dielectric layer 1666 is deposited using another type of deposition technique and / or another suitable deposition technique. The dielectric layer 1666 may be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 1666, a planarization stage 110 may be used to planarize the dielectric layer 1666. In some embodiments, the thickness of the dielectric layer 1666 is included in the range of about 100 angstroms to about 300 angstroms. However, other values ​​within this range are within the range disclosed herein.

[0155] like Figure 17B As shown, a TCR reduction layer 1702 is formed on the dielectric layer 1666. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1The other type of deposition technique and / or another suitable deposition technique are used to deposit the TCR reduction layer 1702. The TCR reduction layer 1702 may be deposited in one or more deposition operations. In some embodiments, after depositing the TCR reduction layer 1702, a planarization station 110 may be used to planarize the TCR reduction layer 1702. In some embodiments, the thickness of the TCR reduction layer 1702 is included in the range of about 400 angstroms to about 600 angstroms. However, other values ​​in this range are within the range disclosed herein.

[0156] like Figure 17C As shown, the TCR reduction layer 1702 is etched to remove a portion of the TCR reduction layer 1702. In some embodiments, a pattern in the photoresist layer is used to etch the TCR reduction layer 1702. In these embodiments, a deposition stage 102 can be used to form a photoresist layer on the TCR reduction layer 1702. An exposure stage 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development stage 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching stage 108 can be used to etch the TCR reduction layer 1702 based on the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal stage can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the TCR reduction layer 1702.

[0157] like Figure 17D As shown, a TCR-increasing layer 1704 is formed on the dielectric layer 1666 and the TCR-reducing layer 1702. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1 The other type of deposition technique and / or another suitable deposition technique are used to deposit the TCR augmentation layer 1704. The TCR augmentation layer 1704 may be deposited in one or more deposition operations. In some embodiments, after depositing the TCR augmentation layer 1704, a planarization station 110 may be used to planarize the TCR augmentation layer 1704. In some embodiments, the thickness of the TCR augmentation layer 1704 is included in the range of about 1000 angstroms to about 1200 angstroms. However, other values ​​in this range are within the range disclosed herein.

[0158] like Figure 17EAs shown, the TCR augmentation layer 1704 is etched to remove a portion of the TCR augmentation layer 1704 on the TCR depletion layer 1702. In some embodiments, a pattern in the photoresist layer is used to etch the TCR augmentation layer 1704. In these embodiments, a deposition stage 102 can be used to form a photoresist layer on the TCR augmentation layer 1704. An exposure stage 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development stage 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching stage 108 can be used to etch the TCR augmentation layer 1704 based on the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal stage can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the TCR augmentation layer 1704.

[0159] like Figure 17F As shown, subsequent etching is performed to remove multiple additional portions of the TCR reduction layer 1702 and multiple additional portions of the TCR increase layer 1704. This etching can be performed to define segments 1672 and 1674 of the primary thin-film resistor 1608 of the resistance sensor structure 1602 (e.g., from the TCR reduction layer 1702 and the TCR increase layer 1704, respectively), define one or more optional thin-film resistors 1610 of the resistance sensor structure 1602 (e.g., from the TCR increase layer 1704), and define one or more optional thin-film resistors 1612 of the resistance sensor structure 1602 (e.g., from the TCR reduction layer 1702). The primary thin-film resistor 1608, one or more optional thin-film resistors 1610, and one or more optional thin-film resistors 1612 are defined such that the primary thin-film resistor 1608, the optional thin-film resistors 1610, and the optional thin-film resistors 1612 are electrically isolated from each other. This allows the primary thin-film resistor 1608, the optional thin-film resistor 1610, and the optional thin-film resistor 1612 to be electrically connected through metallization layers 1628, 1630, 1638, and 1640.

[0160] like Figure 17G As shown, a dielectric layer 1668 can be formed above the resistance sensor structure 1602. The deposition stage 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1The other type of deposition technique and / or another suitable deposition technique are used to deposit the dielectric layer 1668. The dielectric layer 1668 may be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 1668, a planarization station 110 may be used to planarize the dielectric layer 1668.

[0161] like Figure 17H As shown, dielectric layer 1670 can be formed on dielectric layer 1668. Deposition stage 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, and bonding technology. Figure 1 The other type of deposition technique and / or another suitable deposition technique are used to deposit the dielectric layer 1670. The dielectric layer 1670 may be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 1670, a planarization station 110 may be used to planarize the dielectric layer 1670.

[0162] like Figure 17I As shown, contacts 1624, 1626, 1634, and / or 1636 can be formed. Deposition equipment 102 and / or plating equipment 112 can be used with the bonding surface... Figure 1 The CVD, PVD, ALD, electroplating, and other deposition techniques are used to deposit contacts 1624, 1626, 1634, and / or 1636.

[0163] As mentioned above, providing Figure 17A-17I For example. Other examples can be found with reference to... Figure 17A-17I The differences mentioned above.

[0164] Figure 18A and Figure 18B This is a diagram of an example implementation of the tunable resistive sensor structure described herein. Figure 18A Example 1800 of an embodiment of a resistance sensor structure 1802 is shown. The resistance sensor structure 1802 is similar to the resistance sensor structure 1602 and includes one or more inputs 1804a, 1804b, one or more sensing terminals 1806a, 1806b, a main thin-film resistor 1808, multiple selectable thin-film resistors 1810a-1810n (e.g., resistors with increased TCR), multiple selectable thin-film resistors 1812a-1812m (e.g., resistors with decreased TCR), and multiple control gates 1814a-1814x. However, the control gates 1814a-1814x of the resistance sensor structure 1802 differ from those of the control gates 1614a-1614x of the resistance sensor structure 1602 in that the control gates 1814a-1814x include a programmable gate structure similar to the control gates 512a-512n of the resistance sensor structure 502. The control gates 1814a-1814x can be combined Figure 5A-5IOne or more examples of programmable control gates are shown and described to implement this.

[0165] Figure 18B Example 1816 illustrates a structural implementation of the resistance sensor structure 1802. For example... Figure 18B As shown, the structural implementation of the resistance sensor structure 1802 is similar to that of the resistance sensor structure 1602. For example, the main thin-film resistor 1808 includes an active region 1818, contacts 1820 and 1822, and metallization layers 1824 and 1826. Each of the optional thin-film resistors 1810a-1810n and 1812a-1812m includes an active region 1828, contacts 1830 and 1832, and metallization layers 1834 and 1836. The active region 1818 of the main thin-film resistor 1808, the active region 1828 of the optional thin-film resistors 1810a-1810n, and the active region 1828 of the optional thin-film resistors 1812a-1812m are not directly connected but are physically isolated. The main thin-film resistor 1808 is electrically coupled in series with optional thin-film resistors 1810a-1810n and optional thin-film resistors 1812a-1812m via metallization layers 1824, 1826, 1834 and / or 1836. The main thin-film resistor 1808 is also electrically coupled in series with control gates 1814a-1814x via metallization layers 1824, 1826, 1834 and / or 1836. Each of the control gates 1814a-1814x in a first subset is electrically coupled in parallel with a corresponding optional thin-film resistor 1810a-1810n. Each of the control gates 1814a-1814x in a second subset is electrically coupled in parallel with a corresponding optional thin-film resistor 1814a-1814m.

[0166] However, unlike the transmission gates of control gates 1614a-1614x, each of the control gates 1814a-1814x may include a floating gate transistor structure, which includes active regions 1838a and 1838b, word line structures 1840a and 1840b, control gate structures 1842a and 1842b, and erase gate structure 1844.

[0167] As mentioned above, providing Figure 18A and Figure 18B For example. Other examples can be found with reference to... Figure 18A and Figure 18B The differences mentioned above.

[0168] Figure 19This is a diagram of an example component of the apparatus 1900 described herein. In some embodiments, one or more of a semiconductor processing stage (e.g., 102-112) and / or a wafer / die transfer stage 114 may include one or more apparatuses 1900 and / or components of one or more apparatuses 1900. Figure 19 As shown, device 1900 may include bus 1910, processor 1920, memory 1930, input component 1940, output component 1950 and / or communication component 1960.

[0169] Bus 1910 may include one or more components capable of wired and / or wireless communication between components of device 1900. Bus 1910 can... Figure 19 Two or more components are coupled together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 1910 may include electrical connections (e.g., wires, traces, and / or leads) and / or a wireless bus. Processor 1920 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or other types of processing components. Processor 1920 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1920 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0170] Memory 1930 may include volatile and / or non-volatile memory. For example, memory 1930 may include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1930 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1930 may be a non-transitory computer-readable medium. Memory 1930 may store information related to the operation of device 1900, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1930 may include one or more memories coupled (e.g., communication coupling) to one or more processors (e.g., processor 1920), for example, via bus 1910. The communication coupling between processor 1920 and memory 1930 enables processor 1920 to read and / or process information stored in memory 1930 and / or information stored in memory 1930.

[0171] Input component 1940 enables device 1900 to receive input, such as user input and / or sensed input. For example, input component 1940 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator. Output component 1950 enables device 1900 to provide output, such as via a display, speaker, and / or LED. Communication component 1960 enables device 1900 to communicate with other devices via wired and / or wireless connections. For example, communication component 1960 may include a receiver, transmitter, transceiver, modem, network interface card (NIC), and / or antenna.

[0172] Device 1900 may perform one or more of the operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1930) may store a set of instructions (e.g., one or more instructions or code) for execution by processor 1920. Processor 1920 may execute the set of instructions to perform one or more of the operations or processes described herein. In some embodiments, execution of the set of instructions by one or more processors 1920 causes one or more processors 1920 and / or device 1900 to perform one or more of the operations or processes described herein. In some embodiments, hard circuitry may be used in place of or in combination with instructions to perform one or more of the operations or processes described herein. Alternatively or additionally, processor 1920 may be configured to perform one or more of the operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0173] Figure 19 The number and arrangement of the components shown are provided as an example. Device 1900 may include more than Figure 19 The additional components, fewer components, different components, or components arranged differently shown. Alternatively, a group of components in device 1900 (e.g., one or more components) may perform one or more functions described as being performed by another group of components in device 1900.

[0174] Figure 20 This is a flowchart of an example process 2000 related to the formation of the resistance sensor structure described herein. In some embodiments, Figure 20 One or more process blocks are executed using one or more semiconductor processing units (e.g., one or more semiconductor processing units such as 102-112). Alternatively or alternatively, Figure 20 One or more process blocks may be executed using one or more components in device 1900 (e.g., processor 1920, memory 1930, input component 1940, output component 1950 and / or communication component 1960).

[0175] like Figure 20 As shown, process 2000 may include a thin-film resistor (block 2010) for forming a resistive sensor structure. For example, one or more thin-film resistors (e.g., primary thin-film resistors 208, 508, 608, 808, 908, 1108, 1208, 1508, 1608, and / or 1808) in a semiconductor processing apparatus (e.g., 102-112) may be used to form resistive sensor structures as described herein (e.g., resistive sensor structures 202, 502, 602, 802, 902, 1102, 1202, 1508, 1608, and / or 1808).

[0176] like Figure 20 As further shown, process 2000 may include a resistance trimming structure (block 2020) that is electrically coupled in series with a thin-film resistor to form a resistance sensor structure. For example, one or more of the semiconductor processing equipment (e.g., 102-112) may be used to form resistor trimming structures electrically coupled in series with thin-film resistors (e.g., selectable thin-film resistors 210a-210n, selectable thin-film resistors 510a-510n, resistor trimming structure 610, resistor trimming structure 810, resistor trimming structure 910, resistor trimming structure 1110, selectable thin-film resistors 1210a-1210n, selectable thin-film resistors 1212a-1212m, selectable thin-film resistors 1510a-1510n, selectable thin-film resistors 1512a-1512m, selectable thin-film resistors 1610a-1610n, selectable thin-film resistors 1612a-1612m, selectable thin-film resistors 1810a-1810n, selectable thin-film resistors 1812a-1812m).

[0177] Process 2000 may include additional implementations, such as any single implementation or any combination of implementations in combination with one or more other processes described elsewhere herein.

[0178] In the first embodiment, the thin-film resistor is the first thin-film resistor in the resistance sensor structure, and the resistance fine-tuning structure includes a plurality of second thin-film resistors (e.g., selectable thin-film resistors 210a-210n, selectable thin-film resistors 510a-510n, selectable thin-film resistors 1210a-1210n, selectable thin-film resistors 1212a-1212m, selectable thin-film resistors 1510a-1510n, selectable thin-film resistors 1512a-1512m, selectable thin-film resistors) electrically coupled in series with the first thin-film resistor. Resistors 1610a-1610n, optional thin-film resistors 1612a-1612m, optional thin-film resistors 1810a-1810n, optional thin-film resistors 1812a-1812m, and multiple control gates (e.g., control gates 212a-212n, control gates 512a-512n, control gates 1214a-1214x, control gates 1514a-1514x, control gates 1614a-1614x, control gates 1814a-1814x) electrically coupled in series with the first thin-film resistor.

[0179] In the second embodiment, either alone or in combination with the first embodiment, the plurality of second thin-film resistors are electrically connected in series, and the plurality of control gates are electrically connected in series.

[0180] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, a corresponding one of the plurality of control gates is electrically coupled in parallel to a corresponding one of the plurality of second thin-film resistors.

[0181] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the resistor trimming structure includes a plurality of electrically conductive sensing lines (e.g., sensing line 614, sensing line 814, sensing line 914, sensing line 1114) electrically coupled to the thin-film resistor, a plurality of resistor trimming pads (e.g., resistor trimming pad 612, resistor trimming pad 812, resistor trimming pad 912, resistor trimming pad 1112) electrically coupled to the plurality of conductive sensing lines, and a plurality of control gates (e.g., control gate 620, control gate 818, control gate 918, control gate 1116) electrically coupled to the plurality of resistor trimming pads.

[0182] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, a corresponding one of the resistor trimming pads is electrically coupled to a corresponding one of the plurality of control gates and a corresponding one of the electrically conductive sensing lines.

[0183] In the sixth embodiment, the plurality of resistance trimming pads are electrically connected in series, either alone or in combination with one or more of the first to fifth embodiments.

[0184] although Figure 20 An example block from process 2000 is shown, but in some implementations, it differs from... Figure 20 Compared to those shown, process 2000 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more blocks in process 2000 can be executed in parallel.

[0185] In this manner, some resistance sensor structures described herein include a primary thin-film resistor section and one or more optional thin-film resistor sections connected in series (e.g., connected together and connected to the primary thin-film resistor). The one or more optional thin-film resistor sections of the resistance sensor structures described herein can be selectively activated and / or deactivated based on the required resistance and / or TCR of the resistance sensor structure. Various structural embodiments of the control gate for selectively activating and / or deactivating one or more optional thin-film resistors are disclosed herein.

[0186] As described in more detail above, some embodiments described herein provide a method. The method includes forming a thin-film resistor into a resistive sensor structure. The method also includes forming a resistance trimming structure electrically coupled in series with the thin-film resistor into the resistive sensor structure.

[0187] In some embodiments, the thin-film resistor is a first thin-film resistor of the resistance sensor structure, and the resistance trimming structure includes a plurality of second thin-film resistors electrically coupled in series with the first thin-film resistor and a plurality of control gates electrically coupled in series with the first thin-film resistor. In some embodiments, the plurality of second thin-film resistors are electrically coupled in series, and the plurality of control gates are electrically connected in series. In some embodiments, a corresponding one of the plurality of control gates is electrically coupled in parallel with a corresponding one of the plurality of second thin-film resistors. In some embodiments, the resistance trimming structure includes a plurality of electrically conductive sensing lines electrically coupled to the thin-film resistor, a plurality of resistance trimming pads electrically coupled to the plurality of conductive sensing lines, and a plurality of control gates electrically coupled to the plurality of resistance trimming pads. In some embodiments, the resistance trimming structure includes a plurality of resistance trimming pads, and a corresponding one of the resistance trimming pads is electrically coupled to a corresponding one of the plurality of control gates and a corresponding one of the electrically conductive sensing lines. In some embodiments, the plurality of resistance trimming pads are electrically coupled in parallel with the thin-film resistor.

[0188] As described in more detail above, some embodiments described herein provide a resistance sensor structure. The resistance sensor structure includes a first thin-film resistor. The resistance sensor structure includes a plurality of second thin-film resistors electrically coupled in series with the first thin-film resistor, wherein the plurality of second thin-film resistors are electrically coupled in series. The resistance sensor structure includes a plurality of control gates electrically coupled in series with the first thin-film resistor, wherein the plurality of control gates are electrically coupled in series, and wherein a respective one of the plurality of control gates is electrically coupled in parallel with a respective one of the plurality of second thin-film resistors.

[0189] In some embodiments, the plurality of control gates includes a plurality of transmission gates, and each of the plurality of transmission gates includes a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor electrically coupled in parallel with the PMOS transistor. In some embodiments, the plurality of control gates includes a plurality of electrically programmable control gates. In some embodiments, the plurality of electrically programmable control gates includes at least one of the following: a plurality of p-type metal-oxide-semiconductor transistors, a plurality of n-type metal-oxide-semiconductor transistors, a plurality of negative-positive-negative bipolar junction transistors, a plurality of positive-negative-positive bipolar junction transistors, a plurality of floating gate transistors, or a plurality of resistive random access memory structures. In some embodiments, the first thin-film resistor is electrically coupled in series with the plurality of second thin-film resistors through a first active region of the first thin-film resistor and through a plurality of second active regions of the plurality of second thin-film resistors, wherein the second thin-film resistors are electrically coupled in series through the plurality of second active regions of the plurality of second thin-film resistors. In some embodiments, the first thin-film resistor is electrically coupled in series with the plurality of second thin-film resistors through a plurality of metallization layers, wherein the second thin-film resistors are electrically connected in series through the plurality of metallization layers. In some embodiments, the plurality of second thin-film resistors include one or more thin-film resistors with increased resistivity and thermal coefficient and one or more thin-film resistors with decreased resistivity and thermal coefficient.

[0190] As described in more detail above, some embodiments described herein provide a resistance sensor structure. The resistance sensor structure includes a thin-film resistor. The resistance sensor structure includes a resistance trimming structure electrically coupled to the thin-film resistor via a plurality of electrically conductive sensing lines. The resistance sensor structure includes a plurality of control gates electrically coupled to the resistance trimming structure.

[0191] In some embodiments, the resistor trimming structure includes a plurality of series-coupled resistor trimming pads, wherein a corresponding one of the resistor trimming pads is electrically coupled to a corresponding one of the plurality of control gates and a corresponding one of the electrically conductive sensing lines. In some embodiments, each of the plurality of resistor trimming pads includes a burn-out region. In some embodiments, the plurality of control gates includes a plurality of transmission gates. In some embodiments, the plurality of control gates includes a plurality of programmable control gates. In some embodiments, the resistor trimming structure includes a plurality of resistor trimming pads, wherein a corresponding one of the resistor trimming pads is electrically coupled to a corresponding one of the plurality of control gates and a corresponding one of the electrically conductive sensing lines.

[0192] As used in this article, “meeting the threshold” can refer to a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, or equal to the threshold, depending on the context.

[0193] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A resistive sensor structure, characterized by include: First thin-film resistor; A plurality of second thin-film resistors are electrically coupled in series with the first thin-film resistor, wherein the plurality of second thin-film resistors are electrically connected in series; as well as A plurality of control gates are electrically coupled in series with the first thin-film resistor, wherein the plurality of control gates are electrically coupled in series, and a corresponding one of the plurality of control gates is electrically coupled in parallel with a corresponding one of the plurality of second thin-film resistors.

2. The electrical resistance sensor structure according to claim 1, characterized in that The plurality of control gates includes a plurality of transmission gates, and each of the plurality of transmission gates includes: p-type metal-oxide-semiconductor transistor; and The n-type metal-oxide-semiconductor transistor is electrically coupled in parallel with the p-type metal-oxide-semiconductor transistor.

3. The electrical resistance sensor structure of claim 1, wherein, The plurality of control gates includes a plurality of electrically programmable control gates.

4. The electrical resistance sensor structure of claim 1, wherein, The first thin-film resistor is electrically coupled in series with the plurality of second thin-film resistors through a first active region of the first thin-film resistor and through a plurality of second active regions of the plurality of second thin-film resistors, and the second thin-film resistors are electrically coupled in series with the plurality of second active regions of the plurality of second thin-film resistors.

5. The electrical resistance sensor structure of claim 1, wherein, The first thin-film resistor is electrically coupled in series with the plurality of second thin-film resistors through a plurality of metallization layers, and the second thin-film resistors are electrically connected in series through the plurality of metallization layers.

6. The electrical resistance sensor structure of claim 1, wherein, The plurality of second thin-film resistors include: One or more thin-film resistors with an increased temperature coefficient of resistance; and One or more thin-film resistors with a reduced temperature coefficient of resistance.

7. A resistive sensor structure, characterized by include: Thin film resistors; The resistor trimming structure is electrically coupled to the thin-film resistor through multiple electrically conductive sensing lines; as well as Multiple control gates are electrically coupled to the resistor trimming structure.

8. The electrical resistance sensor structure according to claim 7, characterized in that The resistor trimming structure includes a plurality of resistor trimming pads that are electrically coupled in series, wherein a corresponding one of the resistor trimming pads is electrically coupled to a corresponding one of the plurality of control gates and a corresponding one of the electrically conductive sensing lines.

9. The resistive sensor structure according to claim 8, characterized in that Each of the plurality of resistance trimming pads includes a burn-out area.

10. The resistive sensor structure of claim 7, wherein, The resistor trimming structure includes a plurality of resistor trimming pads, wherein a corresponding one of the resistor trimming pads is electrically coupled to a corresponding one of the plurality of control gates and a corresponding one of the electrically conductive sensing lines.

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