Frequency modulation matching circuit and electronic equipment

Abstract

The utility model discloses a frequency modulation matching circuit and electronic equipment, and relates to the technical field of radio frequency power supplies. Wherein the output end of the system-on-chip circuit is connected with the input end of the digital frequency synthesis circuit; the output end of the digital frequency synthesis circuit is connected with the input end of the signal processing circuit; the output end of the signal processing circuit is connected with the input end of the impedance matching circuit; the first output end of the impedance matching circuit is connected with a load; the input end of the sampling circuit is connected with the second output end of the impedance matching circuit, and the output end of the sampling circuit is connected with the input end of the system-on-chip circuit. Therefore, the load is monitored in real time, the parameters of the impedance matching circuit are dynamically adjusted, the energy transmission efficiency is improved, the digital frequency synthesis technology is adopted, microsecond-level frequency switching can be achieved, the high-frequency frequency modulation requirement is met, high-frequency resolution is provided, and the precision and stability of radio-frequency signals are ensured.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency power supply technology, and in particular to a frequency modulation matching circuit and electronic device. Background Technology

[0002] In ion processing within a System on Chip (SOC), the load changes as the SOC operates, causing fluctuations in plasma impedance. However, the fixed-frequency RF power supply in the SOC transmits a signal at a fixed frequency, making it difficult to adapt to load changes and maintain plasma stability. This can lead to plasma extinguishing and interference. Furthermore, the fixed signal frequency results in a relatively uniform electric field distribution within the processing area, leading to inhomogeneity.

[0003] In view of the above-mentioned technology, finding a frequency modulation matching circuit is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide a frequency modulation matching circuit and electronic device that can solve the problem that fixed-frequency radio frequency signals in the prior art are difficult to adapt to changes in load, resulting in a relatively uniform electric field distribution in the signal generation area and unevenness in the processing area.

[0005] To solve the above-mentioned technical problems, on the one hand, this utility model provides a frequency modulation matching circuit, including: an on-chip system circuit, a digital frequency synthesis circuit, a signal processing circuit, an impedance matching circuit, and a sampling circuit;

[0006] The output of the on-chip system circuit is connected to the input of the digital frequency synthesis circuit, and is used to send a generated signal representing a preset frequency to the digital frequency synthesis circuit.

[0007] The output of the digital frequency synthesis circuit is connected to the input of the signal processing circuit, and is used to generate a radio frequency signal with a preset frequency based on the generated signal.

[0008] The output of the signal processing circuit is connected to the input of the impedance matching circuit to amplify and filter the radio frequency signal.

[0009] The first output of the impedance matching circuit is connected to the load and is used to determine the circuit parameters that match the load based on the processed RF signal.

[0010] The input terminal of the sampling circuit is connected to the second output terminal of the impedance matching circuit, and the output terminal of the sampling circuit is connected to the input terminal of the on-chip system circuit. It is used to send the parameters corresponding to the current impedance matching circuit to the on-chip system circuit so that the on-chip system circuit can generate generated signals representing different frequencies according to the parameters.

[0011] Preferably, the on-chip system circuit includes: a drive control circuit and an algorithm processing circuit;

[0012] The first terminal of the drive control circuit is connected to the input terminal of the digital frequency synthesis circuit as the output terminal of the on-chip system circuit; the second terminal of the drive control circuit is connected to the output terminal of the sampling circuit as the input terminal of the on-chip system circuit.

[0013] The third and fourth terminals of the drive control circuit are connected to the first and second terminals of the algorithm processing circuit via the AXI bus protocol.

[0014] The third terminal of the algorithm processing circuit is connected to the memory module; the fourth terminal of the algorithm processing circuit is connected to the host computer.

[0015] Preferably, the digital frequency synthesis circuit includes: a reference clock, a phase-locked loop, an accumulator controller, a memory, and a conversion filter circuit;

[0016] The output of the reference clock is connected to the input of the phase-locked loop.

[0017] The output of the phase-locked loop is connected to the first input of the accumulator controller and the first input of the memory.

[0018] The second input terminal of the accumulator controller is connected to the output terminal of the on-chip system circuit as the input terminal of the digital frequency synthesis circuit.

[0019] The output of the accumulator controller is connected to the second input of the memory;

[0020] The output of the memory is connected to the input of the conversion filter circuit;

[0021] The output of the conversion filter circuit is connected to the input of the signal processing circuit as the output of the digital frequency synthesis circuit.

[0022] Preferably, the conversion filtering circuit includes: a digital-to-analog converter and a first low-pass filter;

[0023] The input terminal of the digital-to-analog converter is connected to the output terminal of the memory as the input terminal of the conversion filter circuit.

[0024] The output of the digital-to-analog converter is connected to the input of the first low-pass filter;

[0025] The output of the first low-pass filter is connected to the input of the signal processing circuit as the output of the conversion filter circuit.

[0026] Preferably, the signal processing circuit includes: a variable gain amplifier, a power amplifier, and a second low-pass filter;

[0027] The input terminal of the variable gain amplifier is connected to the output terminal of the digital frequency synthesis circuit as the input terminal of the signal processing circuit.

[0028] The output of the variable gain amplifier is connected to the input of the power amplifier;

[0029] The output of the power amplifier is connected to the input of the second low-pass filter;

[0030] The output of the second low-pass filter is connected to the input of the impedance matching circuit as the output of the signal processing circuit.

[0031] The connection terminal of the variable gain amplifier is connected to the first connection terminal of the on-chip system circuit.

[0032] The connection terminal of the power amplifier is connected to the second connection terminal of the on-chip system circuit.

[0033] Preferably, the impedance matching circuit includes: a first capacitor, a second capacitor, and a first inductor;

[0034] The first terminal of the first capacitor is connected to the first terminal of the second capacitor, and together they serve as the input terminal of the impedance matching circuit and are connected to the output terminal of the signal processing circuit.

[0035] The second terminal of the first capacitor and the second terminal of the second capacitor together serve as the second output terminal of the impedance matching circuit, which is connected to the input terminal of the sampling circuit.

[0036] The third terminal of the first capacitor is connected to the first terminal of the first inductor;

[0037] The second end of the first inductor is connected to the load as the first output terminal of the impedance matching circuit.

[0038] The third terminal of the second capacitor is grounded.

[0039] Preferably, the first capacitor and the second capacitor are variable capacitors.

[0040] Preferably, it further includes: equivalent resistance;

[0041] The first end of the equivalent resistor is connected to the output of the digital frequency synthesis circuit.

[0042] The second end of the equivalent resistor is connected to the input terminal of the signal processing circuit.

[0043] Preferably, the sampling circuit is an RF agile transceiver.

[0044] On the other hand, this application also provides an electronic device including the above-described frequency modulation matching circuit.

[0045] This utility model provides a frequency modulation matching circuit, comprising: a system-on-a-chip (SoC) circuit, a digital frequency synthesis circuit, a signal processing circuit, an impedance matching circuit, and a sampling circuit; wherein, the output terminal of the SoC circuit is connected to the input terminal of the digital frequency synthesis circuit, and is used to send a generated signal representing a preset frequency to the digital frequency synthesis circuit; the output terminal of the digital frequency synthesis circuit is connected to the input terminal of the signal processing circuit, and is used to generate an radio frequency (RF) signal with a preset frequency based on the generated signal; the output terminal of the signal processing circuit is connected to the input terminal of the impedance matching circuit, and is used to amplify and filter the RF signal; the first output terminal of the impedance matching circuit is connected to a load, and is used to determine the circuit parameters matching the load based on the processed RF signal; the input terminal of the sampling circuit is connected to the second output terminal of the impedance matching circuit, and the output terminal of the sampling circuit is connected to the input terminal of the SoC circuit, and is used to send the parameters corresponding to the current impedance matching circuit to the SoC circuit, so that the SoC circuit can generate generated signals representing different frequencies based on the parameters. Therefore, this application monitors the load in real time and dynamically adjusts the parameters of the impedance matching circuit to improve energy transmission efficiency. Furthermore, this application uses digital frequency synthesis technology, which can achieve microsecond-level frequency switching to meet the requirements of high-frequency modulation, and provides high frequency resolution to ensure the accuracy and stability of radio frequency signals. Attached Figure Description

[0046] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A block diagram of a frequency modulation matching circuit provided in this application;

[0048] Figure 2 A general block diagram of a frequency modulation matching circuit provided in this application;

[0049] Figure 3 A circuit diagram of a digital frequency synthesis circuit provided in an embodiment of this application;

[0050] Figure 4 A circuit diagram of the signal processing circuit provided in the embodiments of this application;

[0051] Figure 5 A flowchart of the method corresponding to the frequency modulation matching circuit provided in the embodiments of this application. Detailed Implementation

[0052] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0053] The core of this invention is to provide a frequency modulation matching circuit and an electronic device.

[0054] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Figure 1 A block diagram of a frequency modulation matching circuit provided in this application is shown below. Figure 1 As shown, the circuit includes: a system-on-chip (SoC) circuit 1, a digital frequency synthesis circuit 2, a signal processing circuit 3, an impedance matching circuit 4, and a sampling circuit 5. It also includes a load ZL. The circuit connections are as follows: the output of the SoC circuit 1 is connected to the input of the digital frequency synthesis circuit 2; the output of the digital frequency synthesis circuit 2 is connected to the input of the signal processing circuit 3; the output of the signal processing circuit 3 is connected to the input of the impedance matching circuit 4; the first output of the impedance matching circuit 4 is connected to the load ZL; the input of the sampling circuit 5 is connected to the second output of the impedance matching circuit 4, and the output of the sampling circuit 5 is connected to the input of the SoC circuit 1.

[0056] In a specific embodiment, based on the connection relationship of the above circuits, it can be seen that they form a loop. The on-chip system circuit 1 first sends a generated signal representing a preset frequency to the digital frequency synthesis circuit 2. The digital frequency synthesis circuit 2 generates an RF signal with a preset frequency based on the generated signal. After the RF signal enters the signal processing circuit 3, the signal processing circuit 3 amplifies and filters the RF signal. The impedance matching circuit 4 adjusts the parameters of its own resistors, capacitors, inductors, etc., based on the processed RF signal to achieve the purpose of matching with the load (obtaining the impedance of the load for matching). After matching, the sampling circuit will again collect the parameters corresponding to the current impedance matching circuit 4, which may be the matched circuit parameters or ordinary parameters, and then send them to the on-chip system circuit 1. The on-chip system circuit 1 generates a generated signal representing a different frequency based on the parameters and repeats the above process again to achieve the purpose of continuous adjustment, so as to ensure that the impedance matching circuit 4 can achieve the purpose of matching for any load value.

[0057] In this design, based on the on-chip system circuit 1, digital frequency synthesis circuit 2, signal processing circuit 3, impedance matching circuit 4, and sampling circuit 5, the working process of a frequency modulation matching circuit can be determined as follows:

[0058] 1. Design the system-on-a-chip circuit: 1. Digital frequency synthesis circuit; 2. Signal processing circuit; 3. Impedance matching circuit; 4. Sampling circuit; 5.

[0059] 2. Initialize the on-chip system circuit 1, setting the initial frequency and matching parameters.

[0060] 3. The digital frequency synthesis circuit 2 generates radio frequency signals, and the signal processing circuit 3 amplifies the signals and transmits them to the load ZL.

[0061] 4. Monitor the impedance of the load ZL in real time and feed the data back to the on-chip system circuit 1.

[0062] 5. On-chip system circuit 1 calculates the optimal frequency and matching parameters, and adjusts the output of digital frequency synthesis circuit 2 and the parameters of impedance matching circuit 4.

[0063] 6. Repeat steps 4-5 until the system reaches a stable state.

[0064] This utility model provides a frequency modulation matching circuit, comprising: a system-on-a-chip (SoC) circuit, a digital frequency synthesis circuit, a signal processing circuit, an impedance matching circuit, and a sampling circuit; wherein, the output terminal of the SoC circuit is connected to the input terminal of the digital frequency synthesis circuit, and is used to send a generated signal representing a preset frequency to the digital frequency synthesis circuit; the output terminal of the digital frequency synthesis circuit is connected to the input terminal of the signal processing circuit, and is used to generate an radio frequency (RF) signal with a preset frequency based on the generated signal; the output terminal of the signal processing circuit is connected to the input terminal of the impedance matching circuit, and is used to amplify and filter the RF signal; the first output terminal of the impedance matching circuit is connected to a load, and is used to determine the circuit parameters matching the load based on the processed RF signal; the input terminal of the sampling circuit is connected to the second output terminal of the impedance matching circuit, and the output terminal of the sampling circuit is connected to the input terminal of the SoC circuit, and is used to send the parameters corresponding to the current impedance matching circuit to the SoC circuit, so that the SoC circuit can generate generated signals representing different frequencies based on the parameters. Therefore, this application monitors the load in real time and dynamically adjusts the parameters of the impedance matching circuit to improve energy transmission efficiency. Furthermore, this application uses digital frequency synthesis technology, which can achieve microsecond-level frequency switching to meet the requirements of high-frequency modulation, and provides high frequency resolution to ensure the accuracy and stability of radio frequency signals.

[0065] In specific embodiments, such as Figure 2As shown, its on-chip system circuit 1 includes: a drive control circuit 11 and an algorithm processing circuit 12. Their connections are as follows: the first terminal of the drive control circuit 11 serves as the output terminal of the on-chip system circuit 1 and is connected to the input terminal of the digital frequency synthesis circuit 2; the second terminal of the drive control circuit 11 serves as the input terminal of the on-chip system circuit 1 and is connected to the output terminal of the sampling circuit 5; the third and fourth terminals (PL terminals) of the drive control circuit 11 are connected to the first and second terminals of the algorithm processing circuit 12 via the AXI bus protocol; the third terminal of the algorithm processing circuit 12 is connected to the DDR4 (Double Data Rate) memory module; and the fourth terminal (PS terminal) of the algorithm processing circuit 12 is connected to the host computer (PC).

[0066] and Figure 2 In the circuit shown, the impedance matching circuit 4 includes a first capacitor C1, a second capacitor C2, and a first inductor L1. The connections are as follows: the first terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and together they serve as the input terminal of the impedance matching circuit 4, connected to the output terminal of the signal processing circuit 3; the second terminals of the first capacitor C1 and the second capacitor C2 together serve as the second output terminal of the impedance matching circuit 4, connected to the input terminal of the sampling circuit 5; the third terminal of the first capacitor C1 is connected to the first terminal of the first inductor L1; the second terminal of the first inductor L2 serves as the first output terminal of the impedance matching circuit 4, connected to the load ZL; and the third terminal of the second capacitor C2 is grounded. In addition, the load ZL is also grounded.

[0067] as well as Figure 2 The circuit shown includes an equivalent resistor ZS between the digital frequency synthesis circuit and the signal processing circuit.

[0068] In a specific embodiment, for the system-on-chip circuit 1, the drive control circuit 11 uses the fourth logic processing terminal (PL terminal) of the FPGA (Field-Programmable Gate Array) to drive the digital frequency synthesis circuit to generate radio frequency signals. The signal processing circuit 3 then performs amplification, filtering, and noise reduction operations, outputting the processed radio frequency signal (RF signal), and drives the sampling circuit 5 to acquire parameters in the impedance matching circuit 4 in real time. The fourth terminal (PS terminal, Processing System) of the algorithm processing circuit 12, as an important component of the algorithm processing circuit 12, undertakes key functions such as system management, algorithm processing, and communication control. The collaborative workflow between the PS terminal and the PL terminal includes, but is not limited to:

[0069] 1. Initialize the system at the PS end and configure the digital frequency synthesis circuit 2 and impedance matching circuit 4 at the PL end.

[0070] 2. The PL terminal generates an RF signal and acquires the impedance data corresponding to the load, and transmits the data to the PS terminal via the AXI bus.

[0071] 3. The PS terminal runs the matching algorithm, calculates the optimal frequency and matching parameters, and sends the results to the PL terminal for execution.

[0072] 4. The PS terminal monitors the system status in real time, processes external commands, and stores operational data.

[0073] 5. When the load impedance changes, the PS terminal dynamically adjusts the algorithm parameters to ensure that the system is always in the optimal working state.

[0074] 6. The PS terminal supports human-computer interaction interfaces (such as touch screens, keyboards, and monitors), allowing users to set parameters such as the frequency and power of radio frequency signals through the interface; it also provides configuration file management functions, allowing users to save and load different working mode configurations for easy switching of application scenarios.

[0075] For impedance matching circuit 4, the impedance of load ZL needs to be determined first in order to achieve impedance matching between impedance matching circuit 4 and load ZL.

[0076] The steps to determine the impedance of the load ZL are as follows:

[0077] 1. Signal Injection: Inject a radio frequency signal with a known frequency and amplitude into the load ZL. The radio frequency signal can be generated by the digital frequency synthesis circuit 2, and then amplified and filtered by the signal processing circuit 3 before being transmitted to the load ZL.

[0078] 2. Signal Acquisition: Voltage and current sensors are used to acquire voltage and current signals on the load ZL. The voltage sensor measures the voltage across the load, and the current sensor measures the current through the load.

[0079] 3. Signal processing: The acquired analog signal is converted into a digital signal through an ADC (analog-to-digital converter), and the digital signal is filtered and calibrated to eliminate noise and errors.

[0080] 4. Calculation Method: The impedance of the load ZL is calculated based on Ohm's law and the complex impedance formula:

[0081] Ohm's Law:

[0082] The formula for calculating the impedance Z of the load ZL is:

[0083] ;

[0084] Where V is the voltage across the load ZL, and I is the current through the load ZL.

[0085] Complex impedance:

[0086] Impedance Z can be expressed in complex form:

[0087] ;

[0088] Where R is resistance (real part) and X is reactance (imaginary part).

[0089] The reactance X can be calculated by measuring the phase difference between voltage and current.

[0090] ;

[0091] Where θ is the phase difference between voltage and current.

[0092] The impedance matching circuit 4 is matched with the load ZL in the following way:

[0093] 1. The calculation of optimal frequency and matching parameters is usually based on impedance matching theory. Commonly used methods include:

[0094] The first method: Conjugate matching method:

[0095] The goal is to make the impedance Z of the load ZL equal to the impedance of the equivalent resistance ZS. Conjugate matching, i.e.:

[0096] ;

[0097] in, It is the conjugate complex number of the load impedance.

[0098] By adjusting the frequency and component values ​​of the matching network, the impedance of the equivalent resistance ZS is reduced. The impedance Z of the load ZL is conjugate matched.

[0099] The second method: Smith chart method: Using the Smith chart tool, the component values ​​of the matching network are calculated graphically. Based on the location of the load impedance, the matching path is found on the Smith chart, and the values ​​of inductor L1, first capacitor C1 and second capacitor C2 are determined.

[0100] 2. Optimization Algorithm: Numerical optimization algorithms (such as gradient descent and genetic algorithms) are used to calculate the optimal frequency and matching parameters, with the goal of minimizing the reflection coefficient or maximizing the transmission efficiency.

[0101] 3. Parameter adjustment: Frequency adjustment: The calculated optimal frequency parameters are sent to the on-chip system circuit 1 to adjust the frequency of the RF signal; Matching network adjustment: The component values ​​of the impedance matching network (such as the first inductor L1, the first capacitor C1, and the second capacitor C2) are adjusted through the digital control interface SPI.

[0102] It should be noted that the embodiments provided in this application are only one possible implementation method, but are not limited to this only implementation method. Users can set their own implementation methods according to their needs.

[0103] It should also be noted that, in order to reduce the operation of replacing components, the first capacitor C1 and the second capacitor C2 in this application are variable capacitors; and the sampling circuit 5 is an RF agile transceiver.

[0104] This application defines the specific structure of the system-on-chip circuit and the impedance matching circuit. Under this structure, the system-on-chip circuit integrates multiple functional modules, simplifying system design; the impedance matching circuit can achieve load matching and improve energy transfer efficiency.

[0105] Based on the above embodiments, such as Figure 3 As shown, its digital frequency synthesis circuit 2 includes: a reference clock 21, a phase-locked loop 22, an accumulator controller 23, a memory 24, a digital-to-analog converter 25, and a first low-pass filter 26. The circuit connections are as follows: the output of the reference clock 21 is connected to the input of the phase-locked loop 22; the output of the phase-locked loop 22 is connected to the first input of the accumulator controller 23 and the first input of the memory 24; the second input of the accumulator controller 23 serves as the input of the digital frequency synthesis circuit 2 and is connected to the output of the system-on-chip circuit 1; the output of the accumulator controller 23 is connected to the second input of the memory 24; the output of the memory 24 is connected to the input of the digital-to-analog converter 25; the output of the digital-to-analog converter 25 is connected to the input of the first low-pass filter 26; and the output of the first low-pass filter 26 serves as the output of the digital frequency synthesis circuit 2 and is connected to the input of the signal processing circuit 3.

[0106] like Figure 4 As shown, its signal processing circuit 3 includes: a variable gain amplifier 31, a power amplifier 32, and a second low-pass filter 33. The connections are as follows: the input terminal of the variable gain amplifier 31 is connected to the output terminal of the digital frequency synthesis circuit 2, serving as the input terminal of the signal processing circuit 3; the output terminal of the variable gain amplifier 31 is connected to the input terminal of the power amplifier 32; the output terminal of the power amplifier 32 is connected to the input terminal of the second low-pass filter 33; the output terminal of the second low-pass filter 33 is connected to the input terminal of the impedance matching circuit 4, serving as the output terminal of the signal processing circuit 3; the connection terminal of the variable gain amplifier 31 is connected to the first connection terminal of the on-chip system circuit 1; and the connection terminal of the power amplifier 32 is connected to the second connection terminal of the on-chip system circuit 1.

[0107] It should be noted that the main function of the digital frequency synthesis circuit 2 is to generate the corresponding radio frequency signal based on the generated signal, while the signal processing circuit 3 performs amplification, filtering and other processing on the radio frequency signal. Therefore, the structure provided in this application is only one possible implementation method, but it is not limited to this implementation method. Users can set it themselves according to their needs.

[0108] In summary, the process of this application is as follows: Figure 5 As shown, the process includes the following:

[0109] S10: Begin.

[0110] S11: Circuit initialization.

[0111] S12: Determine whether the on-chip system circuit and the PC are configured successfully.

[0112] S13: Generates radio frequency signals through a digital frequency synthesis circuit.

[0113] S14: Determine whether to generate an radio frequency signal.

[0114] S15: If so, perform an impedance test on the load.

[0115] S16: If not, adjust the frequency of the radio frequency signal and re-match, and proceed to step S11.

[0116] S17: On-chip system circuitry performs algorithm processing.

[0117] S18: Determine whether the parameters corresponding to the impedance matching circuit are optimal values.

[0118] S19: If yes, determine that the system is stable and proceed to step S14; if no, proceed to step S16.

[0119] S20: To monitor and protect.

[0120] S21: Determine if an anomaly has occurred.

[0121] S22: If yes, then end; otherwise, return to step S19.

[0122] Since steps S10-S22 are a summary of the above embodiments, they will not be described in detail here.

[0123] Therefore, the frequency modulation matching circuit provided in this application has the following advantages:

[0124] 1. Fast frequency modulation: Based on the technology of on-chip system circuit and digital frequency synthesis circuit, microsecond-level frequency switching is achieved to meet the high-frequency modulation requirements.

[0125] 2. High-efficiency matching: Real-time monitoring of load impedance and dynamic adjustment of matching parameters to improve energy transmission efficiency.

[0126] 3. Integrated design: The on-chip system circuit integrates multiple functional modules, simplifying system design.

[0127] 4. High precision: The technology of digital frequency synthesis circuit provides high frequency resolution, ensuring the accuracy and stability of radio frequency signals.

[0128] On the other hand, this application also provides an electronic device that includes the above-described frequency modulation matching circuit and has the same beneficial effects.

[0129] Since the embodiments of the electronic devices provided in this application are the same as the embodiments of the frequency modulation matching circuit described above, this application will not repeat them here.

[0130] The frequency modulation matching circuit and electronic device provided by this utility model have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this utility model without departing from the principle of this utility model, and these improvements and modifications also fall within the protection scope of the claims of this utility model.

[0131] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A frequency matching circuit, characterized by, include: On-chip system circuitry, digital frequency synthesis circuitry, signal processing circuitry, impedance matching circuitry, and sampling circuitry; The output terminal of the system-on-chip circuit is connected to the input terminal of the digital frequency synthesis circuit, and is used to send a generated signal representing a preset frequency to the digital frequency synthesis circuit. The output terminal of the digital frequency synthesis circuit is connected to the input terminal of the signal processing circuit, and is used to generate a radio frequency signal with the preset frequency according to the generated signal. The output terminal of the signal processing circuit is connected to the input terminal of the impedance matching circuit, and is used to amplify and filter the radio frequency signal. The first output terminal of the impedance matching circuit is connected to the load and is used to determine the circuit parameters that match the load based on the processed radio frequency signal. The input terminal of the sampling circuit is connected to the second output terminal of the impedance matching circuit, and the output terminal of the sampling circuit is connected to the input terminal of the system-on-chip circuit. The sampling circuit is used to send the parameters corresponding to the current impedance matching circuit to the system-on-chip circuit so that the system-on-chip circuit can generate the generated signal representing different frequencies according to the parameters.

2. The frequency matching circuit of claim 1, wherein, The on-chip system circuit includes: a drive control circuit and an algorithm processing circuit; Wherein, the first terminal of the drive control circuit is connected to the input terminal of the digital frequency synthesis circuit as the output terminal of the system-on-chip circuit; the second terminal of the drive control circuit is connected to the output terminal of the sampling circuit as the input terminal of the system-on-chip circuit. The third and fourth terminals of the drive control circuit are connected to the first and second terminals of the algorithm processing circuit via the AXI bus protocol. The third terminal of the algorithm processing circuit is connected to the memory module; the fourth terminal of the algorithm processing circuit is connected to the host computer.

3. The frequency matching circuit of claim 1, wherein, The digital frequency synthesis circuit includes: a reference clock, a phase-locked loop, an accumulator controller, a memory, and a conversion filter circuit; The output of the reference clock is connected to the input of the phase-locked loop. The output terminal of the phase-locked loop is connected to the first input terminal of the accumulator controller and the first input terminal of the memory; The second input terminal of the accumulator controller is connected to the output terminal of the system-on-chip circuit as the input terminal of the digital frequency synthesis circuit. The output terminal of the accumulator controller is connected to the second input terminal of the memory; The output terminal of the memory is connected to the input terminal of the conversion and filtering circuit; The output of the conversion filter circuit is connected to the input of the signal processing circuit as the output of the digital frequency synthesis circuit.

4. The frequency matching circuit of claim 3, wherein, The conversion filtering circuit includes: a digital-to-analog converter and a first low-pass filter; The input terminal of the digital-to-analog converter is connected to the output terminal of the memory as the input terminal of the conversion filter circuit. The output terminal of the digital-to-analog converter is connected to the input terminal of the first low-pass filter; The output terminal of the first low-pass filter is connected to the input terminal of the signal processing circuit as the output terminal of the conversion filter circuit.

5. The frequency-matching circuit of claim 1, wherein, The signal processing circuit includes: a variable gain amplifier, a power amplifier, and a second low-pass filter; The input terminal of the variable gain amplifier is connected to the output terminal of the digital frequency synthesis circuit, serving as the input terminal of the signal processing circuit. The output terminal of the variable gain amplifier is connected to the input terminal of the power amplifier; The output terminal of the power amplifier is connected to the input terminal of the second low-pass filter; The output terminal of the second low-pass filter is connected to the input terminal of the impedance matching circuit as the output terminal of the signal processing circuit. The connection terminal of the variable gain amplifier is connected to the first connection terminal of the system-on-chip circuit. The connection terminal of the power amplifier is connected to the second connection terminal of the system-on-chip circuit.

6. The frequency-matching circuit of claim 1, wherein, The impedance matching circuit includes: a first capacitor, a second capacitor, and a first inductor; Wherein, the first terminal of the first capacitor is connected to the first terminal of the second capacitor, and together they serve as the input terminal of the impedance matching circuit and are connected to the output terminal of the signal processing circuit; The second terminal of the first capacitor and the second terminal of the second capacitor together serve as the second output terminal of the impedance matching circuit and are connected to the input terminal of the sampling circuit. The third terminal of the first capacitor is connected to the first terminal of the first inductor; The second end of the first inductor is connected to the load as the first output terminal of the impedance matching circuit. The third terminal of the second capacitor is grounded.

7. The frequency matching circuit of claim 6, wherein, The first capacitor and the second capacitor are variable capacitors.

8. The frequency-modulated matching circuit of claim 1, wherein, Also includes: Equivalent resistance; Wherein, the first end of the equivalent resistor is connected to the output end of the digital frequency synthesis circuit; The second end of the equivalent resistor is connected to the input terminal of the signal processing circuit.

9. The frequency matching circuit according to any one of claims 1 to 8, characterized in that, The sampling circuit is an RF agile transceiver.

10. An electronic device, comprising: Includes the frequency modulation matching circuit as described in any one of claims 1-9.

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