Bandgap thermal sensor circuit and dynamic element matching circuit

Abstract

The utility model provides a band gap thermal sensor circuit and a dynamic element matching circuit. The band gap thermal sensor circuit includes an operating voltage node, a current mirror circuit, and a dynamic element matching (DEM) circuit. The current mirror circuit is coupled to an operating voltage node and includes a plurality of resistive devices. A current mirror circuit is configured to generate a bias current over the plurality of resistive devices. The DEM circuit includes a plurality of DEM transistors coupled to the current mirror circuit. The DEM circuit is configured to switch the bias current via one or more DEM transistors of the plurality of DEM transistors. The DEM circuit includes a leakage reduction circuit configured to reduce a gate current of the one or more DEM transistors of the plurality of DEM transistors and configured to generate a DEM output current based on the bias current and the gate current.

Description

Technical Field

[0001] This utility model relates to a bandgap thermal sensor circuit and a dynamic element matching circuit. Background Technology

[0002] A bandgap thermal sensor is a temperature sensor used in electronic equipment. Some bandgap thermal sensors use a chopper switch to improve signal quality. Some chopper switches utilize dynamic element matching (DEM) technology and are used in bandgap thermal sensors. This type of device may be susceptible to unwanted leakage current. Utility Model Content

[0003] This invention provides a bandgap thermal sensor circuit. The bandgap thermal sensor circuit includes: an operating voltage node; a current mirror circuit coupled to the operating voltage node, the current mirror circuit including a plurality of resistive devices configured to generate a bias current across the plurality of resistive devices; and a dynamic element matching circuit including a plurality of dynamic element matching transistors coupled to the current mirror circuit, the dynamic element matching circuit being configured to switch the bias current via one or more of the plurality of dynamic element matching transistors, the dynamic element matching circuit including a leakage reduction circuit configured to reduce the gate current of the one or more of the plurality of dynamic element matching transistors, and the dynamic element matching circuit being configured to generate a dynamic element matching output current based on the bias current and the gate current.

[0004] This invention provides a dynamic element matching circuit. The dynamic element matching circuit includes: a plurality of dynamic element matching transistors, the dynamic element matching circuit being configured to receive a bias current and selectively distribute the bias current using one or more of the plurality of dynamic element matching transistors based on a digital control signal; and a leakage reduction circuit coupled to the plurality of dynamic element matching transistors, the leakage reduction circuit being configured to reduce the gate-source voltage of one or more of the plurality of dynamic element matching transistors.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 A block diagram of a bandgap thermal sensor according to some embodiments is shown.

[0007] Figure 2 Detailed diagrams of a current mirror circuit, a DEM circuit, and a stacking stage according to some embodiments are shown.

[0008] Figure 3 A leakage reduction circuit for one of a plurality of resistive paths is illustrated according to an embodiment.

[0009] Figure 4 Detailed diagrams of current mirror circuits, DEM circuits, and overlay stages according to some embodiments are provided.

[0010] Figure 5 A block diagram of a bandgap thermal sensor with a leakage-reducing cutoff switch is shown according to some embodiments.

[0011] Figure 6 A leakage reduction cutoff switch is illustrated according to some embodiments.

[0012] Figure 7 A leakage reduction switching element is illustrated according to some embodiments.

[0013] Figure 8 A method for reducing gate leakage current according to some embodiments is illustrated.

[0014] Figure 9 An alternative implementation of a leakage reduction circuit for the gate of a transistor on a resistive path applied to a DEM is illustrated.

[0015] Figure 10 A second alternative implementation of a leakage reduction circuit for the drain / source of a transistor applied to a resistive path in a DEM is illustrated.

[0016] Figure 11 The diagram illustrates an implementation scheme that does not utilize overlay levels. Figure 10 Another example of a leakage reduction circuit is shown.

[0017] Figure 12 This provides another alternative for controlling the gate of the first transistor between the current mirror transistor and the stacked transistor.

[0018] Figure 13 An additional alternative is provided for controlling the gate of the first transistor between the current mirror transistor and the stacked transistor. Detailed Implementation

[0019] The following detailed description is provided to assist the reader in fully understanding the methods, apparatus, and / or systems described herein. Therefore, those skilled in the art may suggest various changes, modifications, and equivalent substitutions to the systems, apparatus, and / or methods described herein. Furthermore, for clarity and conciseness, descriptions of well-known functions and structures may be omitted.

[0020] It should be understood that the wording and terminology used herein are for illustrative purposes and should not be construed as limiting. For example, the use of singular terms (e.g., "a(a)") is not intended to limit the number of items. Furthermore, the use of related terms in the description (e.g., but not limited to "top," "bottom," "left," "right," "upper," "lower," "down," "up," "side") is for clarity and is not intended to limit the scope of the invention or the appended claims. Moreover, it should be understood that any of these features may be used alone or in combination with other features. Other systems, methods, features, and advantages of this invention will become apparent or will become apparent to those skilled in the art upon review of the detailed description. All such additional systems, methods, features, and advantages are intended to be included in this description, within the scope of this invention, and protected by the appended claims.

[0021] As mentioned above, certain devices (e.g., bipolar junction transistor (BJT) bandgap / thermal sensor circuits) can be susceptible to unwanted leakage currents, leading to low power efficiency. In some cases, unwanted gate leakage has been demonstrated in the core metal-oxide-semiconductor (MOS) DEM cutoff switch of BJT bandgap / thermal sensor (BG / TS) devices (e.g., devices with 1.2V VDD). Where the BJT BG / TS operates well at VDD > 1V, this leakage may be difficult to control, possibly due to limitations in the P / N junction turn-on voltage and headroom of the VDD-minus-10% corner. Furthermore, for reliability reasons, certain technologies (e.g., core MOS) may exhibit undesirable gate leakage at VDD-minus-10% corner. gd / V gs / V dsOperation is optimal at voltages below 1 volt. DEM / clipper switches can be used in BJT BG / TS systems to reduce mismatch. However, reliability issues may still exist in certain cases (e.g., core MOS technology only).

[0022] In embodiments, the systems and methods described herein provide designs that can operate in core-MOS-only technology, allowing node scaling to be maintained. In embodiments, temperature sensing devices (BJTs) and main circuit architectures can be implemented away from the BG / TS architecture, reducing node-to-node design migration operations. In embodiments, systems and methods for limiting the effects of gate leakage are proposed, applicable to certain technologies, such as pure core-MOS DEM / cutter circuits in high-voltage (HV) designs and other technologies.

[0023] Figure 1 A block diagram of a bandgap thermal sensor according to some embodiments is shown. The bandgap thermal sensor 100 responds to an operating voltage node (not shown) and generates a signal for indicating temperature. Figure 1 In the example shown, the bandgap thermal sensor 100 includes a current mirror circuit 101, a dynamic element matching (DEM) circuit 102, and a cascode stage 104, which provide an output to a cascode circuit 107, from which the temperature measurement can be confirmed.

[0024] A current mirror circuit 101 is coupled to an operating voltage node (not shown). The current mirror circuit 101 includes a plurality of current matching devices (e.g., transistors) 232, 234, 236, 238. The current mirror circuit 101 generates one or more bias currents 105, 244, 246, 248, with one bias current spanning each of the plurality of current matching devices 232, 234, 236, 238.

[0025] DEM circuit 102 is configured to selectively deliver each bias current 105 via one or more resistive devices (e.g., transistors) based on, for example, the characteristics of resistive devices or the magnitude of bias current 105. DEM circuit 102 includes leakage reduction circuit 103. Leakage reduction circuit 103 is coupled to the plurality of resistive devices and configured to reduce the amount of leakage current flowing from the resistive devices to an external node (e.g., ground). DEM circuit 102 generates DEM output current 106.

[0026] Stack stage 104 receives DEM output current 106 at multiple resistive devices connected in parallel. Stack stage 104 generates stack stage output current 108. Stack stage output current 108 is received by filter circuit 107. Filter circuit 107 is used to control the amount of current passing through resistive elements (e.g., resistors). Temperature can be determined based on the current passing through the resistive elements within filter circuit 107.

[0027] Figure 2 Schematic diagrams of current mirror circuits, DEM circuits, and stacked stages according to some embodiments are shown. Figure 2 In the example shown, each of the plurality of current mirror current matching devices 232, 234, 236, 238 provides bias currents 105, 244, 246, 248, respectively. In the embodiment, the bias currents 105, 244, 246, 248 are proportional to each other (e.g., the second bias current 244 is approximately K times the magnitude of the first bias current 105). The bias currents 105, 244, 246, 248 are received by the DEM circuit 102. The DEM circuit 102 is configured to switch each bias current 105, 244, 246, 248 via one or more of a plurality of resistive paths. For example, for the bias current 105, the DEM circuit 102 includes a resistive path containing a first transistor 201, a resistive path containing a second transistor 202, a resistive path containing a third transistor 203, and a resistive path containing a fourth transistor 204. In operation, one or more of the transistors 201, 202, 203, and 204 may selectively operate at a time. In an embodiment, the resistive path selected by the DEM circuit 102 can be selected based on digital control signals applied to the gates of the transistors 201, 202, 203, and 204. Figure 2 In the example, resistive path transistors 201, 202, 203, and 204 are active low transistors, where a ground signal applied at one of nodes p1, p2, p3, and p4 will activate the corresponding transistor 201, 202, 203, or 204. In the embodiment, the resistive path ( Figure 2 Each of the 16 resistive paths (in the example) is independently controlled. In other instances, fewer signals are used. Figure 2 In this example, four control signals are used (at nodes p1, p2, p3, and p4), and each control signal provides control to four resistive path transistors.

[0028] Stack stage 104 includes a plurality of stacked transistors 215, 216, 217, 218 connected in parallel for each of the plurality of current branches. The inputs of these stacked transistors 215, 216, 217, 218 depend on which of the resistive path transistors (e.g., transistors 201, 202, 203, 204 in the first set of resistive paths) is active upon command of its corresponding control signal. Figure 2 In the example, the first stacked transistor 215 receives current from the first resistive path of each of the four groups, the second stacked transistor 216 receives current from the second resistive path of the four groups, the third stacked transistor 217 receives current from the third resistive path of the four groups, and the fourth stacked transistor 218 receives current from the fourth resistive path of the four groups.

[0029] Each of the multiple sets of resistive paths responds to leakage reduction circuit 103 at the gate of its control transistor (e.g., at the gate of transistors 208, 210, 212, 214 in the first set of resistive paths), which facilitates control of signals at nodes p1, p2, p3, p4. Figure 3 A leakage reduction circuit 103 for one of the multiple sets of resistive paths is illustrated according to an embodiment. Figure 3 In this example, leakage reduction circuit 103 provides two transistors responsive to control nodes p1, p2, p3, and p4. Specifically, leakage reduction circuit 103 includes a first operating transistor 207 coupled to a first transistor 201 at node p1 and a first ground transistor 208 coupled to the first transistor 201 at node p1. Specifically, the first operating transistor 207 is a PMOS transistor, which includes a gate terminal coupled to an operating voltage node 205 when a bias current 105 passes through the first transistor 201. The operating voltage node 205 may have a voltage of, for example, 1.2 volts. The first operating transistor 207 further includes a source terminal coupled to the gate terminal of the first transistor. The first ground transistor 208 includes a gate terminal coupled to a ground voltage node 206 when a bias current 105 passes through the first transistor 201. The first ground transistor 208 further includes a drain terminal coupled to the gate terminal of the first transistor 201.

[0030] The leakage reduction circuit 103 further includes a second operating transistor 209, a third operating transistor 211, and a fourth operating transistor 213, respectively responsive to control nodes p2, p3, and p4. Each of the second operating transistor 209, the third operating transistor 211, and the fourth operating transistor 213 includes a source terminal coupled to the gate terminal of the second transistor 202, the third transistor 203, and the fourth transistor 204, respectively. The leakage reduction circuit 103 further includes a second ground transistor 210, a third ground transistor 212, and a fourth ground transistor 214, each of which is responsive to control nodes p2, p3, and p4, respectively. Each of the second ground transistor 210, the third ground transistor 212, and the fourth ground transistor 214 includes a drain terminal coupled to the gate terminal of the second transistor 202, the third transistor 203, and the fourth transistor 204, respectively.

[0031] exist Figure 3 In this example, the signal at node p1 is enabled, as indicated by the ground signal at transistor 208, while the signals at nodes p2, p3, and p4 are disabled, as indicated by the high signals at the gates of transistors 210, 212, and 214. This causes a bias current 105 to traversing the first transistor 201. As the bias current 105 passes over the first transistor 201, the leakage reduction circuit 103 thus forms a stacked gate structure comprising the first transistor 201, the first ground transistor 208, and a stacked transistor 215 connected to the first transistor 201. The leakage reduction circuit therefore reduces the gate-to-source voltage of the first transistor 201 when the bias current passes over it. Therefore, the gate current of the first transistor 201 is negligible, and virtually all of the bias current 105 delivered to the DEM circuit 102 is received by the stacked stage 104. In a similar manner, the leakage reduction circuit 103 can reduce the gate-source voltage of the second transistor 202, the third transistor 203, or the fourth transistor 204 based on which of the bias currents 105 flow through transistors 201, 202, 203, and 204 (e.g., controlled by signals applied to nodes p1, p2, p3, and p4 via transistors 208, 210, 212, and 214).

[0032] When the first transistor 201 is selected via the activation signal at node p1, and the other transistors 202, 203, and 204 are not selected, the bias current 105 does not pass through these other transistors 202, 203, and 204. When the bias current 105 does not pass through the second transistor 202, the gate terminal of the second operating transistor 209 is coupled to the ground voltage node 206, and the gate terminal of the second ground transistor 210 is coupled to the operating voltage node 205. Similarly, when the bias current 105 does not pass through the third transistor 203 or the fourth transistor 204, the gate terminals of the third operating transistor 211 and the fourth operating transistor 213 are coupled to the ground voltage node 206, and when the bias current 105 does not pass through the third transistor 203 or the fourth transistor 204, the gate terminals of the third ground transistor 212 and the fourth ground transistor 214 are coupled to the operating voltage node 205.

[0033] Figure 4 Detailed diagrams of current mirror circuits, DEM circuits, and overlay stages according to some embodiments are provided. Figure 4 In the example, details of the leakage reduction circuit 103 associated with the first set of resistive paths and the first bias current 105 are shown in detail via transistors 207, 208, 209, 210, 211, 212, 213, and 214, their connections to corresponding transistors in transistors 201, 202, 203, and 204, and their connections to the gates of stacked transistors 215, 216, 217, and 218. Details of the leakage reduction circuit 103 associated with the second, third, and fourth sets of resistive paths are presented in a simplified manner.

[0034] Figure 5 A block diagram of a bandgap thermal sensor with a leakage-reducing chopper switch according to some embodiments is shown. The bandgap thermal sensor 300 includes a current generator 302, which includes a current source 304 and a plurality of current generator transistors 305. A constant number K of current generator transistors 305 may exist. The current source 304 generates a bias current 105 received by a current mirror circuit 101. The current mirror circuit 101 generates a DEM current 307 equal to a constant K multiplied by the bias current 105. The current mirror circuit 101 generates the bias current 105 across the remainder of the plurality of current mirror transistors. As described above, the DEM circuit 102 selectively switches the bias current 105 via one or more of the plurality of DEM transistors. A stack stage 104 includes a plurality of stack transistors connected in parallel. The stack transistors include a first stack transistor 308 for receiving the DEM current 307 and a second stack transistor 309 for receiving the bias current 105.

[0035] A first stacked transistor 308 is coupled to a first terminal of a first chopper switch 311, and a second stacked transistor 309 is coupled to a second terminal of the first chopper switch 311. The output of the first chopper switch 311 is coupled to a second chopper switch 303. The first stacked transistor is further coupled to a first temperature sensing transistor 312. The second stacked transistor 309 is further coupled to a first terminal of a resistor 310. The second terminal of the resistor 310 is coupled to a second temperature sensing transistor 313. The first temperature sensing transistor 312 and the second temperature sensing transistor 313 are coupled to a ground voltage node 314. The temperature of the bandgap thermal sensor 300 can be calculated by comparing the voltage appearing across the first temperature sensing transistor 312 with the voltage appearing across the second temperature sensing transistor 313. Figure 6 The description further elaborates on the operation of the first cutoff switch 311 and the second cutoff switch 303.

[0036] Figure 6 A leakage reduction cutoff switch is illustrated according to some embodiments. The leakage reduction cutoff switch 400 may be, for example... Figure 5 The first cutoff switch 311 or the second cutoff switch 303 shown is illustrated. The leakage reduction cutoff switch 400 includes a positive input voltage node 401, a negative input voltage node 402, a positive output voltage node 403, and a negative output voltage node 404. The leakage reduction cutoff switch 400 further includes a first switching element 407, a second switching element 408, a third switching element 409, and a fourth switching element 410. The first switching element 407 is used to connect and disconnect the positive input voltage node 401 and the positive output voltage node 403. The second switching element 408 is used to connect and disconnect the positive input voltage node 401 and the negative output voltage node 404. The third switching element 409 is used to connect and disconnect the negative input voltage node 402 and the positive output voltage node 403. The fourth switching element 410 is used to connect and disconnect the negative input voltage node 402 and the negative output voltage node 404. Each of the switching elements 407, 408, 409, and 410 is controlled by the digital operating voltage DVDD 405 and the source voltage VS 406. Figure 7 The description further elaborates on the operation of each of the switching elements 407, 408, 409, and 410.

[0037] Figure 7 A leakage reduction switching element is shown according to some embodiments. The leakage reduction switching element 500 can be used as... Figure 6 The leakage reduction shown refers to any of the switching elements 407, 408, 409, and 410 in the chopper switch 400. Figure 7In the example shown, the leakage reduction switching element 500 includes a buffer 501. The buffer 501 receives a switching element input signal 506. The switching element input signal 506 may be a digital operating voltage DVDD 405 or a source voltage VS 406. After passing through the buffer 501, the switching element input signal 506 is received at the gate terminals of the PMOS transistor 502 and the NMOS transistor 503.

[0038] If the switching element input signal 506 is sufficiently high (e.g., digital operating voltage DVDD 405), then the NMOS transistor 503 is enabled, and the ground voltage (e.g., 0 volts) is coupled to the switching element output node 504, which corresponds to, for example, the switching element being closed. The leakage-reducing switching element 500 includes a voltage source 505 that generates a source voltage VS 406 between the ground voltage node 314 and the NMOS transistor 503. If the switching element input signal 506 is sufficiently low (e.g., source voltage VS406), then the PMOS transistor 502 is enabled, and the digital operating voltage DVDD 405 is coupled to the switching element output node 504, which corresponds to, for example, the switching element being open. As shown, these signals are then applied to one of the switching elements (e.g., ...). Figure 6 The switch element 410 shown is used to control the switch with minimized gate leakage.

[0039] Figure 8 Methods for reducing gate leakage current according to some embodiments are illustrated. Figure 8 In the example shown, method 600 includes a first step 601 of receiving a digital control signal. Method 600 further includes a second step 602 of distributing a bias current via one or more transistors based on the digital control signal. Method 600 further includes a third step 603 of coupling the one or more transistors to an operating transistor or a ground transistor based on the digital control signal. This coupling reduces the gate-source voltage of the one or more transistors.

[0040] As described in this article, leakage reduction circuits can take many forms. Figure 9 An alternative implementation of a leakage reduction circuit for the gate of a transistor applied to a resistive path in a DEM is illustrated. A bias current 105 is received at the first transistor 201 from the first current matching device 232 of the current mirror circuit 101. The output of this transistor is provided to the first transistor 215 of the stack stage 104. The gate of the first transistor 201 is controlled by a leakage reduction circuit transistor 702. When the first transistor 201 is selected to start, the leakage reduction circuit transistor 702 pulls node p1 low (e.g., ...). Figure 9As shown in the diagram, this allows the bias current to flow from the current mirror transistor 232 to the stacked transistor 215. In this ON state, the bias current flows to the inverting gate leakage (I) of the leakage reduction circuit transistor 702 to the ground node. GI ) is affected by the small V associated with the first transistor 201 GS The limitation is that when the first transistor 201 is not selected, a high signal is applied to node p1, thereby turning off the first transistor 201 and preventing current from flowing from the current mirror transistor 232 to the stacked transistor 215. In this case, leakage of the high signal from node p1 through the gate of the first transistor 201 is limited (e.g., substantially less than I). GI ).

[0041] Figure 10 A second alternative embodiment of the leakage reduction circuit for the drain / source of transistor 201 applied to the resistive path of a DEM is illustrated. In this case, the bias current 105 from the first current matching device 232 is received directly by the first transistor 215 of the stack stage 104. The gate of the first transistor 215 of the stack stage 104 is controlled by the first transistor 201 and the leakage reduction circuit transistor 802. The leakage reduction circuit transistor 802 receives the inverse of the control signal applied at node p1 (at node p1_b), thereby controlling the signal provided to the gate of the stack transistor 215. When a low signal is applied at node p1, the first transistor 201 is turned on, thereby providing a path from 804 to the gate of the stack transistor 215. This pulls the gate of the stack transistor 204 low, thereby allowing the bias current 105 to pass through this transistor 215. Correspondingly, a high signal is applied at node p1_b, thereby turning off the leakage reduction circuit transistor 802. When a high signal is applied to the first transistor 201 at node p1, a low signal is provided to the gate of the leakage reduction circuit transistor 802, which in turn applies a high signal to the gate of the stacked transistor 215 and turns off the first transistor 201.

[0042] In this example, when the first transistor 201 is turned on, V gs,sw ~ (V DD –V dsat(current_mirror_transistor) ) – V gs,cascode The gate leakage of the switch is not on the bias current path. When the first transistor 201 is turned off, the superimposed gate is connected to V. DD As shown in the figure below, a similar implementation can be directly applied to current mirror transistors.

[0043] Figure 11 The diagram illustrates an implementation scheme that does not utilize overlay levels. Figure 10This is another example of a leakage reduction circuit. Here, the gate of the first current matching device 232 of the current mirror circuit 101 is directly controlled. A low signal at node p1 turns on the first transistor 201, creating a path from 804 to the gate of the current mirror transistor 232. This pulls the gate of the current mirror transistor 232 low, allowing the bias current 105 to pass through this transistor 232. When a high signal is applied to the first transistor 201 at node p1, a high signal is applied from the leakage reduction circuit transistor 802, thereby turning off the current mirror transistor 232.

[0044] Figure 12 Another alternative is provided for controlling the gate of the first transistor 201 between the current mirror transistor 232 and the stacked transistor 215. In this alternative, when the first transistor 201 is turned on, V... gs,sw ~ (V DD –V dsat(current_mirror_transistor) ) – V gs, sw1 When the switch is turned off, the gate of the stacked transistor 215 is connected to V. DD . Figure 13 An additional alternative is provided for controlling the gate of the first transistor between the current mirror transistor 232 and the stacked transistor 215. Wherein, when the switch is turned on, V gs,sw ~ (V DD – V dsat(current_mirror_transistor) ) –V ds, sw1 Similarly, when the switch is turned off, the gate of the stacked transistor 215 is connected to V. DD .

[0045] This document describes systems and methods. In one example, a circuit includes an operating voltage node, a current mirror circuit, and a dynamic element matching (DEM) circuit. The current mirror circuit is coupled to the operating voltage node and includes multiple resistive devices. The current mirror circuit is configured to generate a bias current across the multiple resistive devices. The DEM circuit includes multiple DEM transistors coupled to the current mirror circuit. The DEM circuit is configured to switch the bias current via one or more of the multiple DEM transistors. The DEM circuit includes a leakage reduction circuit configured to reduce the gate current of one or more of the multiple DEM transistors and configured to generate a DEM output current based on the bias current and the gate current.

[0046] In a related embodiment, the bandgap thermal sensor circuit further includes a stacked stage coupled to the dynamic element matching circuit, the stacked stage including a plurality of stacked transistors configured to receive the dynamic element matching output current and generate a stacked stage output current.

[0047] In a related embodiment, the bandgap thermal sensor circuit further includes a chopper circuit coupled to the stack stage, the chopper circuit being configured to receive the output current of the stack stage and operate a chopper switch based on the output current of the stack stage.

[0048] In a related embodiment, the dynamic element matching circuit includes a plurality of current branches, each of which includes the plurality of dynamic element matching transistors.

[0049] In a related embodiment, the leakage reduction circuit includes an operating transistor and a ground transistor coupled to each of the plurality of dynamic element matching transistors.

[0050] In a related embodiment, the leakage reduction circuit reduces the gate current of the one or more dynamic element matched transistors by reducing the gate-source voltage of the one or more dynamic element matched transistors.

[0051] In a related embodiment, the leakage reduction circuit is configured to form a stacked gate structure including the one or more dynamic element matched transistors.

[0052] In related embodiments, the plurality of resistive devices are plurality of current mirror transistors.

[0053] In another example, a dynamic element matching (DEM) circuit includes a plurality of DEM transistors. The DEM circuit is configured to receive a bias current and selectively distribute the bias current using one or more of the plurality of DEM transistors based on a digital control signal. The DEM circuit further includes leakage reduction circuitry coupled to the plurality of DEM transistors. The leakage reduction circuitry is configured to reduce the gate-source voltage of one or more of the plurality of DEM transistors.

[0054] In a related embodiment, the leakage reduction circuit is further configured to form a stacked gate structure including one or more of the dynamic element matching transistors among the plurality of dynamic element matching transistors.

[0055] In a related embodiment, the leakage reduction circuit includes an independent operating transistor coupled to each of the plurality of dynamic element matching transistors.

[0056] In a related embodiment, the leakage reduction circuit includes an independent grounded transistor coupled to each of the plurality of dynamic element matching transistors.

[0057] In related embodiments, the operating transistor and the grounding transistor are P-channel metal-oxide-semiconductor transistors.

[0058] In a related embodiment, the dynamic element matching circuit includes a plurality of current branches, each of which includes the plurality of dynamic element matching transistors.

[0059] In a related embodiment, each of the plurality of current branches is coupled to a current mirror transistor.

[0060] In another example, a method for reducing gate leakage current includes receiving a digital control signal. The method further includes distributing a bias current via one or more transistors based on the digital control signal. The method further includes coupling the one or more transistors to an operating transistor or a ground transistor based on the digital control signal. This coupling reduces the gate-source voltage of the one or more transistors.

[0061] In related embodiments, the method further includes receiving the bias current and generating a dynamic element matching output current based on the bias current and the gate leakage current.

[0062] In a related embodiment, the operating transistor is a P-channel metal-oxide-semiconductor operating transistor having a gate terminal coupled to an operating voltage node.

[0063] In a related embodiment, the grounding transistor is a P-channel metal-oxide-semiconductor grounding transistor having a gate terminal coupled to a ground voltage node.

[0064] In a related embodiment, the plurality of transistors are included in one of a plurality of current branches.

[0065] Those skilled in the art will understand that changes can be made to the above embodiments without departing from the broad inventive concept of this disclosure. Therefore, it should be understood that the utility model disclosed herein is not limited to the specific embodiments disclosed, and is intended to cover modifications within the spirit and scope of this utility model.

Claims

1. A bandgap thermal sensor circuit, characterized by include: Operating voltage node; A current mirror circuit, coupled to the operating voltage node, the current mirror circuit including a plurality of resistive devices, the current mirror circuit being configured to generate a bias current across the plurality of resistive devices; as well as A dynamic element matching circuit includes a plurality of dynamic element matching transistors coupled to the current mirror circuit, the dynamic element matching circuit being configured to switch the bias current via one or more of the plurality of dynamic element matching transistors, the dynamic element matching circuit including a leakage reduction circuit configured to reduce the gate current of the one or more of the plurality of dynamic element matching transistors, and the dynamic element matching circuit being configured to generate a dynamic element matching output current based on the bias current and the gate current.

2. The bandgap thermal sensor circuit of claim 1, wherein, It further includes a stacking stage coupled to the dynamic element matching circuit, the stacking stage including a plurality of stacked transistors configured to receive the dynamic element matching output current and generate a stacking stage output current.

3. The bandgap thermal sensor circuit of claim 2, wherein, It further includes a chopper circuit coupled to the stacking stage, the chopper circuit being configured to receive the output current of the stacking stage and to operate the chopper switch based on the output current of the stacking stage.

4. The band gap thermal sensor circuit of claim 1, wherein, The leakage reduction circuit includes an operating transistor and a ground transistor coupled to each of the plurality of dynamic element matching transistors.

5. The band gap thermal sensor circuit of claim 1, wherein, The plurality of resistive devices are plurality of current mirror transistors.

6. A dynamic element matching circuit, characterized by include: A plurality of dynamic element matching transistors, wherein the dynamic element matching circuit is configured to receive a bias current and selectively distribute the bias current using one or more of the plurality of dynamic element matching transistors based on a digital control signal; as well as A leakage reduction circuit, coupled to the plurality of dynamic element matched transistors, is configured to reduce the gate-source voltage of one or more of the plurality of dynamic element matched transistors.

7. A dynamic element matching circuit according to claim 6, wherein, The leakage reduction circuit is further configured to form a stacked gate structure including one or more of the dynamic element matching transistors among the plurality of dynamic element matching transistors.

8. The dynamic element matching circuit of claim 6, wherein, The leakage reduction circuit includes an independent operating transistor coupled to each of the plurality of dynamic element matched transistors.

9. The dynamic element matching circuit of claim 6, wherein, The dynamic element matching circuit includes multiple current branches, each of which includes the multiple dynamic element matching transistors.

10. A dynamic element matching circuit according to claim 9, wherein, Each of the plurality of current branches is coupled to a current mirror transistor.

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