Integrated circuit with variable threshold circuit

Abstract

This invention provides an integrated circuit with a variable threshold circuit. The integrated circuit includes: an asymmetric upper threshold circuit that outputs an upper branch enable signal; an asymmetric lower threshold circuit that outputs a lower branch enable signal; and a control circuit that changes the output voltage when the logic levels of the upper and lower branch enable signals change continuously. The upper branch enable signal is set to a first upper branch logic level when the input voltage received by the integrated circuit rises above a main upper threshold and is set to a second upper branch logic level when the input voltage falls below an auxiliary upper threshold, wherein the auxiliary upper threshold is higher than the main upper threshold. The lower branch enable signal is set to a first lower branch logic level when the input voltage falls below a main lower threshold and is set to a second lower branch logic level when the input voltage rises above an auxiliary lower threshold, wherein the auxiliary lower threshold is lower than the main lower threshold.

Description

Technical Field

[0001] This utility model relates to an input buffer circuit with a variable threshold circuit, an integrated circuit, and a method thereof. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but deliver more functionality at a faster speed. Miniaturization processes have also made design and manufacturing specifications more stringent and introduced reliability challenges. Various electronic design automation (EDA) tools generate standard cell layout designs for integrated circuits while ensuring compliance with standard cell layout design and manufacturing specifications, and then optimize and verify these standard cell layout designs. Utility Model Content

[0003] This utility model discloses an integrated circuit with a variable threshold circuit, comprising: an asymmetric upper threshold circuit having an upper branch output node configured to output an upper branch enable signal generated based on an input voltage signal, wherein the asymmetric upper threshold circuit is configured to set the upper branch enable signal to a first upper branch logic level in response to the input voltage signal rising above a main upper threshold and is configured to set the upper branch enable signal to a second upper branch logic level in response to the input voltage signal falling below an auxiliary upper threshold, wherein the auxiliary upper threshold is higher than the main upper threshold; and an asymmetric lower threshold circuit having a lower branch output node, wherein the lower branch output node... A point is configured to output a lower branch enable signal generated based on the input voltage signal, wherein the asymmetric lower threshold circuit is configured to set the lower branch enable signal to a first lower branch logic level in response to the input voltage signal falling across a major lower threshold and is configured to set the lower branch enable signal to a second lower branch logic level in response to the input voltage signal rising across an auxiliary lower threshold, wherein the auxiliary lower threshold is lower than the major lower threshold; and a control circuit is configured to change the output voltage signal from a first voltage level to a second voltage level in response to a continuous change in the logic level of the upper branch enable signal and the logic level of the lower branch enable signal.

[0004] This utility model discloses an integrated circuit with a variable threshold circuit, comprising: an asymmetric upper threshold circuit configured to output an upper branch enable signal at an upper branch output node; an asymmetric lower threshold circuit configured to output a lower branch enable signal at a lower branch output node; a first switch configured to be controlled by the upper branch enable signal from the upper branch output node; and a second switch configured to be controlled by the lower branch enable signal from the lower branch output node, wherein each of the asymmetric upper threshold circuit and the asymmetric lower threshold circuit comprises: a first type transistor having a gate terminal and a drain terminal, the gate terminal being configured as an input terminal, the drain terminal being configured as the upper branch output node or the lower branch output node; and a plurality of second type transistors having a channel connected in series between a voltage node and the drain terminal of the first type transistor, the plurality of second type transistors having gate terminals, all of the gate terminals of the plurality of second type transistors being connected to the gate terminal of the first type transistor.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1A This is a schematic diagram of an input buffer circuit having two threshold circuits and a control circuit according to some embodiments.

[0007] Figure 1B According to some embodiments Figure 1A The diagram shows an implementation scheme combining an input buffer circuit with a level shifter.

[0008] Figure 1C This is a schematic diagram of an input buffer circuit with a control circuit implemented using a switch, according to some embodiments.

[0009] Figure 2 Based on some embodiments and Figure 1B The waveform diagram of the signals related to the input buffer circuit is shown.

[0010] Figure 3 Based on some embodiments and Figure 1C The waveform diagram of the signal related to the input buffer circuit.

[0011] Figures 4A to 4B This is a schematic diagram of an input buffer circuit with a variable threshold in a threshold circuit, according to some embodiments.

[0012] Figure 5These are waveforms of signals at various nodes of an improved input buffer circuit according to some embodiments.

[0013] Figure 6 This is a schematic diagram of an input buffer circuit according to some embodiments, the input buffer circuit having a threshold circuit controlled by a threshold selection signal.

[0014] Figure 7 This is a flowchart of a method for generating an output voltage signal based on an input voltage signal according to some embodiments.

[0015] Figure 8A This is a schematic diagram of an asymmetric upper threshold circuit according to some embodiments.

[0016] Figure 8B This is a schematic diagram of an asymmetric lower threshold circuit according to some embodiments.

[0017] Explanation of reference numerals in the attached figures

[0018] 100, 100B, 100C, 400B, 600: Input buffer circuit

[0019] 102: Input Node

[0020] 108: Output Node

[0021] 110, 410, 810: Asymmetric upper threshold circuit

[0022] 112: High-side tracker

[0023] 114: Asymmetric upper threshold detector

[0024] 116: Auxiliary upper threshold detector

[0025] 118, 128: Transmission gate

[0026] 119: Upper branch output node

[0027] 120, 420, 820: Asymmetric lower threshold circuit

[0028] 122: Low-side tracker

[0029] 124: Asymmetric lower threshold detector

[0030] 126: Auxiliary lower threshold detector

[0031] 129: Lower branch output node

[0032] 130: Control Circuit

[0033] 131: First Switch

[0034] 132: Second Switch

[0035] 135: Regenerative Circuit

[0036] 140, 140D, 140U: Level shifters

[0037] 450, 450D, 450U: Threshold selection signal

[0038] 610D, 610U: Delay circuit

[0039] 620: Inverter

[0040] 700: Method

[0041] 705, 710, 714, 720, 724, 730, 734, 740, 744: Operation

[0042] BufOut: Buffer output node

[0043] ENDN: Lower branch enable signal

[0044] ENUPB: Upper Part Support Enable Signal

[0045] MN1, MN2, N1d, N1u, N2d, N2u, N3d, N4d, N4u: NMOS transistors

[0046] MP1, MP2, P1d, P1u, P2d, P2u, P3u, P4u: PMOS transistors

[0047] PAD: Input voltage signal

[0048] PADDN: Downward Tracking Signal

[0049] PADUP: Tracking upward signal

[0050] t1, t1*, t2, t3, t3*, t4, ta, tb, tc, td, t+, t-: time

[0051] TRUE: Logical truth

[0052] VDDH: Voltage / Power Supply Voltage / Upper Power Supply Voltage

[0053] VDDL, VSSH: Voltage / Power Supply Voltage

[0054] Vout: Output voltage signal

[0055] VSS: Voltage / Power Supply Voltage / Lower Power Supply Voltage

[0056] VTH: Upper limit voltage / Main upper threshold / Upper threshold

[0057] VTH+: Auxiliary upper threshold

[0058] VTL: Lower Threshold Voltage / Main Lower Threshold / Lower Threshold

[0059] VTL-: Auxiliary Lower Threshold Detailed Implementation

[0060] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are expected. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0061] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0062] An input buffer circuit couples an input voltage signal from a transmitting circuit in a first power domain to a receiving circuit in a second power domain. The input buffer circuit receives the input voltage signal and generates an output voltage signal. The input buffer circuit has a lower threshold voltage and an upper threshold voltage. In some embodiments, an upper branch enable signal is generated based on a comparison between the input voltage signal and the upper threshold voltage, and a lower branch enable signal is generated based on a comparison between the input voltage signal and the lower threshold voltage. In some embodiments, the output voltage signal changes between a first voltage level and a second voltage level based on the upper and lower branch enable signals. When the input voltage signal rises and successively crosses the lower threshold voltage and then the upper threshold voltage, the output voltage signal changes from the first voltage level to the second voltage level. When the input voltage signal falls and successively crosses the upper threshold voltage and then the lower threshold voltage, the output voltage signal changes from the second voltage level to the first voltage level.

[0063] Figure 1A This is a schematic diagram of an input buffer circuit 100 having two threshold circuits and a control circuit according to some embodiments. The input buffer circuit 100 includes an asymmetric upper threshold circuit 110, an asymmetric lower threshold circuit 120, and a control circuit 130. The asymmetric upper threshold circuit 110 and the asymmetric lower threshold circuit 120 are configured to receive an input voltage signal PAD at an input node 102 of the input buffer circuit 100. The asymmetric upper threshold circuit 110 is configured to generate an upper branch enable signal ENup based on a comparison between the input voltage signal PAD and an upper threshold voltage VTH. In some embodiments, if the input voltage signal PAD is greater than the upper threshold voltage VTH, the upper branch enable signal ENup generated by the asymmetric upper threshold circuit 110 is set to logic true (TRUE). The asymmetric lower threshold circuit 120 is configured to generate a lower branch enable signal ENdn based on a comparison between the input voltage signal PAD and a lower threshold voltage VTL. In some embodiments, if the input voltage signal PAD is less than the lower threshold voltage VTL, the lower branch enable signal ENdn generated by the asymmetric lower threshold circuit 120 is set to logic true. The upper branch enable signal ENup and the lower branch enable signal ENdn are coupled to the control circuit 130. The control circuit 130 is configured to generate an output voltage signal Vout at its output node 108 based on the upper branch enable signal ENup and the lower branch enable signal ENdn.

[0064] In operation, the input voltage signal PAD at input node 102 is provided by electronic circuitry in the first power domain, and the output voltage signal Vout generated by input buffer circuitry 100 at output node 108 is coupled to electronic circuitry in the second power domain. In some embodiments, the electronic circuitry in the first power domain is connected between power supply voltages VDDH and VSS, and the electronic circuitry in the second power domain is connected between power supply voltages VDDL and VSS. In some embodiments, power supply voltage VSS is connected to a shared ground, and power supply voltage VDDH in the first power domain is 2.5 volts (or 3.3 volts), while power supply voltage VDDL in the second power domain is 1.8 volts. In some embodiments, power supply voltage VSS is connected to a shared ground, and power supply voltage VDDH in the first power domain is 1.8 volts (or 2.5 volts), while power supply voltage VDDL in the second power domain is 1.2 volts. In some embodiments, power supply voltage VDDH is higher than 3.3 volts. In some embodiments, power supply voltage VDDL is less than 1.2 volts. Other instances of power supply voltages VDDH and VDDL are within the scope of this disclosure. During operation, the voltage level of the input voltage signal PAD at the input node 102 of the input buffer circuit 100 is generally in the range from VSS to VDDH, and the output voltage signal Vout generated at the output node 108 of the input buffer circuit 100 is in the range from VSS to VDDL.

[0065] The output voltage signal Vout at output node 108 of the input buffer circuit 100 changes in response to the input voltage signal PAD at input node 102. The input voltage signal PAD follows a trapezoidal waveform: the input voltage signal PAD rises from voltage VSS to voltage VDDH and remains at voltage VDDH for a certain time; then, the input voltage signal PAD falls from voltage VDDH back to voltage VSS. While the input voltage signal PAD is rising from voltage VSS and changing towards voltage VDDH, the output voltage signal Vout changes from voltage VSS to voltage VDDL at the time t+ during which the input voltage signal PAD crosses the upper threshold voltage VTH. The output voltage signal Vout remains at voltage VDDL, while the input voltage signal PAD reaches voltage VDDH and remains at voltage VDDH. When the input voltage signal PAD is decreasing from voltage VDDH and changing towards voltage VSS, the output voltage signal Vout changes from voltage VDDL to voltage VSS at the time t- when the input voltage signal PAD crosses the lower threshold voltage VTL. Because the waveform of the output voltage signal Vout changes within the range from VSS to VDDL, it is a more suitable signal for electronic circuits in a second power domain powered by supply voltages VDDL and VSS. In contrast, if the input voltage signal PAD were directly coupled to the electronic circuits in the second power domain, the peak voltage of the input voltage signal PAD (e.g., VDDH) could exceed the maximum withstand voltage of the electronic circuits in the second power domain.

[0066] Figure 1B This is a schematic diagram of an input buffer circuit 100B having a control circuit implemented using a switch, according to some embodiments. Figure 1B In this circuit, the asymmetric upper threshold circuit 110 includes a high-side tracker 112 and an asymmetric upper threshold detector 114. The high-side tracker 112 is configured to generate an upward tracking signal PADUP based on an input voltage signal PAD. The asymmetric upper threshold detector 114 is configured to receive the upward tracking signal PADUP from the high-side tracker 112 and set the logic level of the upper branch enable signal ENUPB based on the upward tracking signal PADUP. Figure 1B In this circuit, the asymmetric lower threshold circuit 120 includes a low-side tracker 122 and an asymmetric lower threshold detector 124. The low-side tracker 122 is configured to generate a downward tracking signal PADDN based on an input voltage signal PAD. The asymmetric lower threshold detector 124 is configured to receive the downward tracking signal PADDN from the low-side tracker 122 and set the logic level of the lower branch enable signal ENDN based on the downward tracking signal PADDN.

[0067] exist Figure 1BIn this circuit, control circuit 130 includes a first switch 131, a second switch 132, and a regenerative circuit 135. The first switch 131 is electrically connected between the upper power supply voltage VDDH and the buffer output node BufOut. The second switch 132 is electrically connected between the buffer output node BufOut and the lower power supply voltage VSS. The buffer output node BufOut is located at the electrical connection between the first switch 131 and the second switch 132. The regenerative circuit 135 is electrically coupled to the buffer output node BufOut. When both the first switch 131 and the second switch 132 are in the open state, the regenerative circuit 135 maintains the voltage at the buffer output node BufOut. The first switch 131 is controlled by the upper branch enable signal ENUPB received from the asymmetric upper threshold detector 114. The second switch 132 is controlled by the lower branch enable signal ENDN received from the asymmetric lower threshold detector 124. The buffer output node BufOut is coupled to the input terminal of the level shifter 140. Level shifter 140 is connected to power supply VDDH in the first power domain and power supply VDDL in the second power domain. The voltage signal at the input terminal of level shifter 140 is within the voltage range of the first power domain, but the voltage signal at the output terminal of level shifter 140 is within the voltage range of the second power domain. The output terminal of level shifter 140 is the output node 108 of input buffer circuit 100B. The output voltage signal Vout of input buffer circuit 100B at output node 108 is within the voltage range of the second power domain. (See reference...) Figure 2 To explain Figure 1B The operation of the input buffer circuit 100B in the middle.

[0068] Figure 2 It is located according to some embodiments Figure 1B Waveform diagrams of signals at the input nodes, output nodes, and various other nodes in the input buffer circuit 100B. Figure 2 Part A is the waveform of the input voltage signal PAD at input node 102. Figure 2 Part B is the waveform of the upward tracking signal PADUP at the output of the high-side tracker 112. Figure 2 Part C is the waveform of the downward tracking signal PADDN at the output of the low-side tracker 122. Figure 2 The D part is the waveform of the upper branch enable signal ENUPB at the output of the asymmetric upper threshold detector 114. Figure 2 The E part is the waveform of the lower branch enable signal ENDN at the output of the asymmetric lower threshold detector 124. Figure 2 The F part is the waveform of the voltage at the output node BufOut of the buffer.

[0069] exist Figure 2In the exemplary waveform shown in Part A, during the time period from ta to tb, the input voltage signal PAD rises from voltage VSS to voltage VDDH. During the time period from tb to tc, the input voltage signal PAD remains at voltage VDDH. During the time period from tb to tc, the input voltage signal PAD remains at voltage VDDH. During the time period from tc to td, the input voltage signal PAD falls from voltage VDDH to voltage VSS. During the time period from ta to tb, where the input voltage signal PAD is rising, the input voltage signal PAD crosses the lower threshold voltage VTL at time t1 and the upper threshold voltage VTH at time t2. During the time period from tc to td, where the input voltage signal PAD is falling, the input voltage signal PAD crosses the upper threshold voltage VTH at time t3 and the lower threshold voltage VTL at time t4.

[0070] exist Figure 2 In the exemplary waveform shown in Part B, if the signal received at the input of the high-side tracker 112 is greater than a predetermined lower limit voltage (e.g., VSSH), the upward tracking signal PADUP at the output of the high-side tracker 112 follows the signal received at the input, and if the signal received at the input is less than or equal to the predetermined lower limit voltage, the upward tracking signal PADUP remains at the predetermined lower limit voltage (e.g., VSSH).

[0071] exist Figure 2 In the exemplary waveform shown in Part C, if the signal received at the input of the low-side tracker 122 is less than a predetermined upper limit voltage (e.g., VDDL), the downward tracking signal PADDN at the output of the low-side tracker 122 follows the signal received at the input, and if the signal received at the input is greater than or equal to the predetermined upper limit voltage, the downward tracking signal PADDN remains at the predetermined upper limit voltage (e.g., VDDL).

[0072] exist Figure 2 In the example waveform shown in section D, the upper branch enable signal ENUPB at the output of the asymmetric upper threshold detector 114 is determined by comparing the upward tracking signal PADUP (received from the high-side tracker 112) with the upper threshold voltage VTH. Before time t2, Figure 2 In Part B, the upward tracking signal PADUP is below the upper threshold voltage VTH, and Figure 2 The upper part of section D enables the signal ENUPB to be in a logic false state. From time t2 to time t3, Figure 2 In Part B, the upward tracking signal PADUP is above the upper threshold voltage VTH, and Figure 2The upper part of section D enables the signal ENUPB to be in logical true. After time t3... Figure 2 In Part B, the upward tracking signal PADUP is again below the upper threshold voltage VTH, and Figure 2 The upper part of section D enables the signal ENUPB to be in a logic false state. Figure 1B In the input buffer circuit 100B shown, the logic of the upper branch enable signal ENUPB is implemented using a lower voltage level, while the logic of the upper branch enable signal ENUPB is implemented using a higher voltage level.

[0073] exist Figure 2 In the exemplary waveform shown in section E, the lower branch enable signal ENDN at the output of the asymmetric lower threshold detector 124 is determined by comparing the downward tracking signal PADDN (received from the low-side tracker 122) with the lower threshold voltage VTL. Before time t1, Figure 2 In section C, the downward tracking signal PADDN is below the lower threshold voltage VTL, and Figure 2 The lower part of section E enables the ENDN signal to be in logical true. From time t1 to time t4, Figure 2 In section C, the downward tracking signal PADDN is above the lower threshold voltage VTL, and Figure 2 The lower part of section E enables the signal ENDN to be in a logical false state. After time t4... Figure 2 In section C, the downward tracking signal PADDN is again below the lower threshold voltage VTL, and Figure 2 The lower part of section E enables the ENDN signal to be in logical true. Figure 1B In the input buffer circuit 100B shown, the logic of the lower branch enable signal ENDN is implemented using a higher voltage level, while the logic of the lower branch enable signal ENDN is implemented using a lower voltage level.

[0074] exist Figure 1B In the input buffer circuit 100B shown, the upper branch enable signal ENUPB from the asymmetric upper threshold detector 114 controls the first switch 131, and the lower branch enable signal ENDN received from the asymmetric lower threshold detector 124 controls the second switch 132. When the upper branch enable signal ENUPB is logically true, the first switch 131 is in a connected state where the buffer output node BufOut is connected to the upper power supply voltage VDDH. When the lower branch enable signal ENDN is logically true, the second switch 132 is in a connected state where the buffer output node BufOut is connected to the lower power supply voltage VSS.

[0075] exist Figure 2In the example waveform shown in part F, Figure 1B The voltage at the output node BufOut of the buffer depends on Figure 2 The upper part of section D supports the enable signal ENUPB and Figure 2 The lower support enable signal ENDN in section E. Before time t1, because the upper support enable signal ENUPB is logically false and the lower support enable signal ENDN is logically true, the buffer output node BufOut is not connected to the upper power supply voltage VDDH through the first switch 131, but the buffer output node BufOut is connected to the lower power supply voltage VSS through the second switch 132. Therefore, the voltage at the buffer output node BufOut is at the lower power supply voltage VSS.

[0076] From time t1 to time t2, since the upper support enable signal ENUPB is at logic false and the lower support enable signal ENDN is at logic false, the buffer output node BufOut is not connected to the upper power supply voltage VDDH through the first switch 131, nor is it connected to the lower power supply voltage VSS through the second switch 132. However, during the period from time t1 to time t2, since the regenerative circuit 135 maintains the voltage of the buffer output node BufOut at time t1 until time t2 when each of the first switch 131 and the second switch 132 is not in the connected state, the voltage at the buffer output node BufOut remains at the lower power supply voltage VSS.

[0077] From time t2 to time t3, since the upper support enable signal ENUPB is true and the lower support enable signal ENDN is false, the buffer output node BufOut is connected to the upper power supply voltage VDDH through the first switch 131, but the buffer output node BufOut is not connected to the lower power supply voltage VSS through the second switch 132. Therefore, the voltage at the buffer output node BufOut is at the upper power supply voltage VDDH.

[0078] From time t3 to time t4, since the upper support enable signal ENUPB is at logic false and the lower support enable signal ENDN is at logic false, the buffer output node BufOut is not connected to the upper power supply voltage VDDH through the first switch 131, nor is it connected to the lower power supply voltage VSS through the second switch 132. However, during the period from time t3 to time t4, since the regeneration circuit 135 maintains the voltage of the buffer output node BufOut at time t3 until time t4 when each of the first switch 131 and the second switch 132 is not in the connected state, the voltage at the buffer output node BufOut remains at the upper power supply voltage VDDH.

[0079] After time t4, since the upper support enable signal ENUPB is in logic false and the lower support enable signal ENDN is in logic true, the buffer output node BufOut is not connected to the upper power supply voltage VDDH through the first switch 131. Instead, the buffer output node BufOut is connected to the lower power supply voltage VSS through the second switch 132. Therefore, the voltage at the buffer output node BufOut is at the lower power supply voltage VSS.

[0080] exist Figure 2 In the example waveform shown in section F, when the input voltage signal PAD crosses the upper threshold voltage VTH while the input voltage signal PAD is rising, the voltage at the buffer output node BufOut changes from the lower supply voltage VSS to the upper supply voltage VDDH at time t+ (the same as time t2). When the input voltage signal PAD crosses the lower threshold voltage VTL while the input voltage signal PAD is falling, the voltage at the buffer output node BufOut changes from the upper supply voltage VDDH to the lower supply voltage VSS at time t- (the same as time t4).

[0081] Figure 1B An exemplary implementation of the input buffer circuit 100B is as follows: Figure 1C The input buffer circuit shown. Figure 1C This is a schematic diagram of an input buffer circuit 100C with a control circuit implemented using switches, according to some embodiments. Figure 1B In the input buffer circuit 100B shown, each of the asymmetric upper threshold detector 114 and the asymmetric lower threshold detector 124 can be implemented based on an asymmetric metal oxide semiconductor field-effect transistor (MOSFET) threshold or based on a symmetric MOSFET threshold. Figure 1C In the input buffer circuit 100C shown, each of the asymmetric upper threshold detector 114 and the asymmetric lower threshold detector 124 is implemented based on an asymmetric MOSFET threshold. Figure 1C In the asymmetric upper threshold detector 114 and asymmetric lower threshold detector 124, each includes a plurality of first type transistors connected in series with second type transistors.

[0082] exist Figure 1CIn the asymmetric upper threshold detector 114, four P-channel MOS (PMOS) transistors P1u to P4u and an N-channel MOS (NMOS) transistor N1u are included. The asymmetric lower threshold detector 124 includes four NMOS transistors N1d to N4d and a PMOS transistor P1d. A first switch 131 controlled by the asymmetric upper threshold detector 114 includes PMOS transistors MP1 and MP2. A second switch 132 controlled by the asymmetric lower threshold detector 124 includes NMOS transistors MN1 and MN2.

[0083] In the asymmetric upper threshold detector 114, the channels of PMOS transistors P1u to P4u are connected in series between a constant voltage node (e.g., upper supply voltage VDDH) and the drain terminal of NMOS transistor N1u. The drain terminal of NMOS transistor N1u is the upper branch output node 119 of the asymmetric upper threshold detector 114. The channel of NMOS transistor N1u is connected between the upper branch output node 119 and the supply voltage VSSH. The gate terminals of PMOS transistors P1u to P4u are all connected together with the gate terminal of NMOS transistor N1u to receive the upward tracking signal PADUP from the high-side tracker 112. The upper branch output node 119 is configured to output an upper branch enable signal ENUPB that swings between two upper branch logic levels: logic high voltage (e.g., voltage VDDH) and logic low voltage (e.g., voltage VSSH).

[0084] In the asymmetric lower threshold detector 124, the channels of NMOS transistors N1d to N4d are connected in series between the drain terminal of PMOS transistor P1d and a constant voltage node (e.g., the lower supply voltage VSS). The drain terminal of PMOS transistor P1u is the lower branch output node 129 of the asymmetric lower threshold detector 124. The channel of PMOS transistor P1d is connected between the supply voltage VDDL and the lower branch output node 129. The gate terminals of NMOS transistors N1d to N4d are all connected together with the gate terminal of PMOS transistor P1d to receive the down-tracking signal PADDN from the low-side tracker 122. The lower branch output node 129 of the asymmetric lower threshold detector 124 is configured to output a lower branch enable signal ENDN that swings between two lower branch logic levels: a logic high voltage (e.g., voltage VDDL) and a logic low voltage (e.g., voltage VSS).

[0085] In the first switch 131, the channels of PMOS transistors MP1 and MP2 are connected in series between the upper power supply voltage VDDH and the buffer output node BufOut. The gate of PMOS transistor MP1 is connected to the upper branch output node 119 of the asymmetric upper threshold detector 114 to receive the upper branch enable signal ENUPB. The gate of PMOS transistor MP1 is connected to the power supply voltage VSSH.

[0086] In the second switch 132, the channels of NMOS transistors MN2 and MN1 are connected in series between the buffer output node BufOut and the lower power supply voltage VSS. The gate of NMOS transistor MN1 is connected to the lower branch output node 129 of the asymmetric lower threshold detector 124 to receive the lower branch enable signal ENDN. The gate of NMOS transistor MN1 is connected to the power supply voltage VDDL.

[0087] In operation, if as follows Figure 2 The input voltage signal PAD shown in section A is coupled to Figure 1C If the input node 102 of the input buffer circuit 100C is such that the voltage at the output node BufOut of the input buffer circuit 100C has the following characteristics: Figure 2 The waveform shown in section F.

[0088] Before time t1, the upward tracking signal PADUP at the output of the high-side tracker 112 induced by the input voltage signal PAD is below the upper threshold voltage VTH of the asymmetric upper threshold detector 114, and the logic high voltage (e.g., voltage VDDH) at the output of the asymmetric upper threshold detector 114 drives the PMOS transistor MP1 to a non-conducting state. As the PMOS transistor MP1 is driven to the non-conducting state, the first switch 131 is driven to the off state. Here, in order to control the first switch 131, the logic high voltage (e.g., voltage VDDH) of the upper branch enable signal ENUPB at the output of the asymmetric upper threshold detector 114 is logic false. Additionally, prior to time t1, the downward tracking signal PADDN at the output of the low-side tracker 122, induced by the input voltage signal PAD, is below the lower threshold voltage VTL of the asymmetric lower threshold detector 124, and the logic high voltage (e.g., voltage VDDL) at the output of the asymmetric lower threshold detector 124 drives the NMOS transistor MN1 to the connected state. Since both NMOS transistors MN1 and MN2 are in the on state, the second switch 132 is driven to the connected state. At this point, to control the second switch 132, the logic high voltage (e.g., voltage VDDL) of the lower branch enable signal ENDN at the output of the asymmetric lower threshold detector 124 is logic true.

[0089] Before time t1, such as Figure 2 As shown in section F, in response to the situation where the first switch 131 is in the off state and the second switch 132 is in the on state, the buffer output node BufOut is at voltage VSS.

[0090] From time t1 to time t2, the upward tracking signal PADUP remains below the upper threshold voltage VTH of the asymmetric upper threshold detector 114, and the output of the asymmetric upper threshold detector 114 remains at a logic high voltage (e.g., voltage VDDH) that drives the PMOS transistor MP1 to a non-conducting state. Therefore, the first switch 131 remains in the off state, and the PMOS transistor MP1 remains in the non-conducting state. On the other hand, when the downward tracking signal PADDN rises above the lower threshold voltage VTL of the asymmetric lower threshold detector 124 at time t1, the output of the asymmetric lower threshold detector 124 begins to change from a logic high voltage (e.g., voltage VDDL) towards a logic low voltage (e.g., voltage VSS). In response to the output of the asymmetric lower threshold detector 124 reaching a logic low voltage (e.g., voltage VSS), the NMOS transistor MN1 is driven to a non-conducting state, and thus the second switch 132 is driven to the off state. Here, in order to control the second switch 132, the logic low voltage (e.g., voltage VSS) of the lower branch enable signal ENDN at the output of the asymmetric lower threshold detector 124 is logic false.

[0091] From time t1 to time t2, such as Figure 2 As shown in section F, even if the first switch 131 is in the open state and the second switch 132 changes from the connected state to the open state after a delay from time t1, the buffer output node BufOut remains at voltage VSS. Even if both the first switch 131 and the second switch 132 are in the open state before time t2, the regeneration circuit 135 maintains the voltage at the buffer output node BufOut.

[0092] At time t2, the upward tracking signal PADUP rises above the upper threshold voltage VTH of the asymmetric upper threshold detector 114, and the output of the asymmetric upper threshold detector 114 begins to change from a logic high voltage (e.g., voltage VDDH) towards a logic low voltage (e.g., voltage VSSH). In response to the output of the asymmetric upper threshold detector 114 reaching a logic low voltage (e.g., voltage VSSH), the PMOS transistor MP1 is driven to the connected state, and thus the first switch 131 is driven to the connected state. Here, to control the first switch 131, the logic low voltage (e.g., voltage VSSH) of the upper branch enable signal ENUPB at the output of the asymmetric upper threshold detector 114 is logic true. Furthermore, at and after time t2, the downward tracking signal PADDN continues to remain above the lower threshold voltage VTL of the asymmetric lower threshold detector 124 at least until time t4. During normal operation, the output of the asymmetric lower threshold detector 124 reaches a logic low voltage (e.g., voltage VSS) before time t2. At and after time t2, the output of the asymmetric lower threshold detector 124 remains at a logic low voltage (e.g., voltage VSS) at least until time t4, and therefore the second switch 132 remains in the off state at least until time t4. Similarly, to control the second switch 132, the logic low voltage (e.g., voltage VSS) of the lower branch enable signal ENDN at the output of the asymmetric lower threshold detector 124 is logic false.

[0093] After a delay from time t2, in response to the output of the asymmetric upper threshold detector 114 reaching a logic low voltage (e.g., voltage VSSH), the first switch 131 is driven to the connected state, and thus the voltage at the buffer output node BufOut is changed to voltage VDDH, while the second switch 132 remains in the disconnected state.

[0094] From time t2 to time t3, such as Figure 2 As shown in section F, in response to the situation where the first switch 131 is in the connected state after a certain delay from time t2 and the second switch 132 is in the open state from time t2, the buffer output node BufOut is at voltage VDDH.

[0095] At time t3, the upward tracking signal PADUP drops below the upper threshold voltage VTH of the asymmetric upper threshold detector 114, and the output of the asymmetric upper threshold detector 114 begins to change from a logic low voltage (e.g., voltage VSSH) towards a logic high voltage (e.g., voltage VDDH). After a delay from time t3, in response to the output of the asymmetric upper threshold detector 114 reaching a logic high voltage (e.g., voltage VDDH), the PMOS transistor MP1 is driven to a non-conducting state, and thus the first switch 131 is driven to the off state. Furthermore, at and after time t3, the downward tracking signal PADDN remains above the lower threshold voltage VTL of the asymmetric lower threshold detector 124 at least until time t4, and the output of the asymmetric lower threshold detector 124 remains at a logic low voltage (e.g., voltage VSS) at least until time t4. Therefore, from time t3 to at least time t4, the second switch 132 remains in the off state.

[0096] From time t3 to time t4, such as Figure 2 As shown in section F, even if the first switch 131 changes from the connected state to the disconnected state after a delay from time t3 and the second switch 132 is in the disconnected state before time t4, the buffer output node BufOut remains at voltage VDDH. Even if both the first switch 131 and the second switch 132 are in the disconnected state before time t4, the regeneration circuit 135 maintains the voltage at the buffer output node BufOut.

[0097] At and after time t4, the upward tracking signal PADUP remains below the upper threshold voltage VTH of the asymmetric upper threshold detector 114. In normal operation, the output of the asymmetric upper threshold detector 114 reaches a logic high voltage (e.g., voltage VDDH) before time t4 and remains thereafter. Therefore, after time t4, the output of the asymmetric upper threshold detector 114 remains, the PMOS transistor MP1 remains in the non-conducting state, and the first switch 131 remains in the open state. Additionally, at time t4, the downward tracking signal PADDN drops below the lower threshold voltage VTL of the asymmetric lower threshold detector 124, and the output of the asymmetric lower threshold detector 124 begins to change from a logic low voltage (e.g., voltage VSS) towards a logic high voltage (e.g., voltage VDDL). In response to the output of the asymmetric lower threshold detector 124 reaching a logic high voltage (e.g., voltage VDDL), the NMOS transistor MN1 is driven to the connected state after a delay from time t4, and thus the second switch 132 is driven to the connected state.

[0098] After time t4, such as Figure 2As shown in section F, in response to the situation where the first switch 131 remains in the off state from time t4 and the second switch 132 changes from the off state to the connected state after a certain delay from time t4, the voltage at the buffer output node BufOut changes to voltage VSS.

[0099] exist Figure 2 In part D, the exemplary waveform of the upper branch enable signal ENUPB is generated by the asymmetric upper threshold detector 114. In the asymmetric upper threshold detector 114, PMOS transistors P1u to P4u and NMOS transistor N1u are connected to... Figure 2 The falling edge of the input voltage signal PAD in Part A is relatively fast. Specifically, the PMOS transistors P1u to P4u and the NMOS transistor N1u are fast enough that after the input voltage signal PAD falls below the upper threshold voltage VTH of the asymmetric upper threshold detector 114 at time t3, when the output of the asymmetric upper threshold detector 114 begins to change from a logic low voltage (e.g., voltage VSSH) to a logic high voltage (e.g., voltage VDDH), the output of the asymmetric upper threshold detector 114 reaches a logic high voltage (e.g., voltage VDDH) before time t4. In some cases, such as Figure 3 As shown in the example waveform in Part D, the output of the asymmetric upper threshold detector 114 cannot reach a logic high voltage (e.g., voltage VDDH) at time t4 because the transistor in the asymmetric upper threshold detector 114 is too slow. This causes an undesirable situation in which both the first switch 131 and the second switch 132 are in a connected state.

[0100] exist Figure 2 In the E section, the instance waveform of the lower branch enable signal ENDN is generated by the asymmetric lower threshold detector 124. In the asymmetric lower threshold detector 124, NMOS transistors N1u to N4u and PMOS transistor P1d are connected to... Figure 2 The rising edge of the input voltage signal PAD in Part A is relatively fast. Specifically, the NMOS transistors N1u to N4u and the PMOS transistor P1d are fast enough that after the down-tracking signal PADDN rises above the lower threshold voltage VTL of the asymmetric lower threshold detector 124 at time t1 when the output of the asymmetric lower threshold detector 124 begins to change from a logic high voltage (e.g., voltage VDDL) to a logic low voltage (e.g., voltage VSS), the output of the asymmetric lower threshold detector 124 reaches a logic low voltage (e.g., voltage VSS) before time t2. In some cases, such as Figure 3As shown in the example waveform in Part E, the output of the asymmetric lower threshold detector 124 cannot reach a logic low voltage (e.g., voltage VSS) at time t2 because the transistor in the asymmetric lower threshold detector 124 is too slow. This causes an undesirable situation in which both the first switch 131 and the second switch 132 are in a connected state.

[0101] Figure 3 It is located according to some embodiments Figure 1C Waveforms of signals at the input nodes, output nodes, and various other nodes in the input buffer circuit 100C. Figure 3 Part A to Figure 3 The corresponding C part is the same as Figure 2 Part A to Figure 2 Part C.

[0102] Figure 3 Part D is Figure 1C The waveform of the upper branch enable signal ENUPB at the output of the asymmetric upper threshold detector 114 in the input buffer circuit 100C is shown. Since the asymmetric upper threshold detector 114 in the input buffer circuit 100C is an asymmetric threshold detector based on an asymmetric MOSFET threshold, the fall time of the upper branch enable signal ENUPB, which begins to change from logic high to logic low at time t2, is less than the rise time of the upper branch enable signal ENUPB, which begins to change from logic low to logic high at time t3. In some cases, such as... Figure 3 As shown in section D, the upper branch enable signal ENUPB reaches a logic high voltage at time t3*, and time t3* is later than time t4 (time t4 is the moment when the input voltage signal PAD drops below the lower threshold voltage VTL). The slower the transistor in the asymmetric upper threshold detector 114, the larger the time difference t3*-t3. The faster the input voltage signal PAD decreases at the falling edge from time t3 to time t4, the smaller the time difference t4-t3. In some cases, due to the combination of the slower transistor and the rapid signal swing of the input voltage signal PAD, the time difference t3*-t3 is greater than the time difference t4-t3, and therefore time t3* is later than time t4.

[0103] During the time interval from time t4 to time t3*, the upper branch enable signal ENUPB is at logic true (at logic low voltage), which causes the first switch 131 to be in the connected state, while the lower branch enable signal ENDN is also at logic true (at logic high voltage), which causes the second switch 132 to be in the connected state. Because both the first switch 131 and the second switch 132 are in the connected state between time t4 and time t3*, a short circuit may induce a malfunction in the asymmetrical upper threshold detector 114.

[0104] Figure 3 Part E is Figure 1C The waveform of the lower branch enable signal ENDN at the output of the asymmetric lower threshold detector 124 in the input buffer circuit 100C is shown. Since the asymmetric lower threshold detector 124 in the input buffer circuit 100C is an asymmetric threshold detector based on an asymmetric MOSFET threshold, the fall time of the lower branch enable signal ENDN, which begins to change from logic high to logic low at time t1, is greater than the rise time of the lower branch enable signal ENDN, which begins to change from logic low to logic high at time t4. In some cases, such as... Figure 3 As shown in section E, the lower branch enable signal ENDN reaches a logic low voltage at time t1*, which is later than time t2 (time t2 is the moment when the input voltage signal PAD rises above the upper threshold voltage VTH). The slower the transistor in the asymmetric lower threshold detector 124, the larger the time difference t1*-t1. The faster the input voltage signal PAD increases at the rising edge from time t1 to time t2, the smaller the time difference t2-t1. In some cases, due to the combination of the slower transistor and the rapid signal swing of the input voltage signal PAD, the time difference t1*-t1 is greater than the time difference t2-t1, and therefore time t1* is later than time t2.

[0105] During the time interval from time t2 to time t1*, the lower branch enable signal ENDN is at logic true (at logic high voltage), which causes the second switch 132 to be in the connected state, while the upper branch enable signal ENUPB is also at logic true (at logic low voltage), which causes the first switch 131 to be in the connected state. Because both the first switch 131 and the second switch 132 are in the connected state between time t2 and time t1*, a short circuit may induce a malfunction in the asymmetrical lower threshold detector 124.

[0106] Figure 3 The F part is Figure 1C The waveform of the voltage at the buffer output node BufOut in the input buffer circuit 100C shown. Figure 3In part F, the asymmetric lower threshold detector 124 is at risk of failure from time t+ to time t1*, and the asymmetric upper threshold detector 114 is at risk of failure from time t- to time t3*. This is addressed by an improved input buffer circuit (e.g., Figures 4A to 4B The input buffer circuits 400A to 400B in the circuit reduce the risk of failure in the asymmetrical upper threshold detector 114 and asymmetrical lower threshold detector 124 due to the rapid signal swing of the input voltage signal PAD.

[0107] Integrated circuits often have multiple examples of input buffer circuits, and therefore often have multiple examples of asymmetric upper threshold detectors and multiple examples of lower threshold detectors. Due to process, voltage, and temperature variations ("PVT variations") and changes in reliability degradation tolerance, the time t3* associated with each example of the asymmetric upper threshold detector 114 and the time t1* associated with each example of the asymmetric lower threshold detector 124 all vary according to some statistical distribution. The statistical distribution of time t3* corresponds to the time spread of time t3*, which is... Figure 3 In part D, multiple trajectories between times t3 and t3* are plotted. The statistical distribution of time t1* corresponds to the time extension of time t1*, which is... Figure 3 In part E, multiple trajectories between time t1 and t1* are plotted.

[0108] The greater the PVT variation, the greater the time extension of time t3*. A greater time extension of time t3* results in a greater number of examples of asymmetric upper threshold detectors 114 with a failure risk due to an unwanted positive time delay T3*-T4>0. As the operating frequency of the integrated circuit increases, the failure risk between time t4 and time t3* also increases. Similarly, the greater the PVT variation, the greater the time extension of time t1*. A greater time extension of time t1* results in a greater number of examples of asymmetric lower threshold detectors 124 with a failure risk due to an unwanted positive time delay t1*-t2>0. As the operating frequency of the integrated circuit increases, the failure risk between time t2 and time t1* also increases. For high-speed operation of multiple examples of integrated circuits with input buffer circuits, the... Figure 1C Compared to the input buffer circuit 100C, Figures 4A to 4B The input buffer circuits 400A to 400B provide improved reliability and reduced failures.

[0109] Figures 4A to 4B This is a schematic diagram of an input buffer circuit with a variable threshold in a threshold circuit, according to some embodiments. Figures 4A to 4BEach of the input buffer circuits 400A to 400B includes an asymmetric upper threshold circuit 410 and an asymmetric lower threshold circuit 420, both configured to receive a threshold selection signal 450. Based on the threshold selection signal 450 received by the asymmetric upper threshold circuit 410, the asymmetric upper threshold circuit 410 is configured to operate as an asymmetric upper threshold detector 114 or as an auxiliary upper threshold detector 116. In response to the threshold selection signal 450 indicating that the input voltage signal PAD increases at the rising edge, the asymmetric upper threshold circuit 410 operates as an asymmetric upper threshold detector 114 with a primary upper threshold VTH. Conversely, in response to the threshold selection signal 450 indicating that the input voltage signal PAD decreases at the falling edge, the asymmetric upper threshold circuit 410 operates as an auxiliary upper threshold detector 116 with an auxiliary upper threshold VTH+. The auxiliary upper threshold VTH+ is higher than the main upper threshold VTH.

[0110] Based on the threshold selection signal 450 received by the asymmetric lower threshold circuit 420, the asymmetric lower threshold circuit 420 is configured to operate as either an asymmetric lower threshold detector 124 or an auxiliary lower threshold detector 126. In response to the threshold selection signal 450 indicating that the input voltage signal PAD decreases at the falling edge, the asymmetric lower threshold circuit 420 operates as an asymmetric lower threshold detector 124 with a primary lower threshold VTL. Conversely, in response to the threshold selection signal 450 indicating that the input voltage signal PAD increases at the rising edge, the asymmetric lower threshold circuit 420 operates as an auxiliary lower threshold detector 126 with an auxiliary lower threshold VTL-. The auxiliary lower threshold VTL- is lower than the primary lower threshold VTL.

[0111] Figure 5 It is a modified input buffer circuit according to some embodiments (e.g.) Figures 4A to 4B Waveform diagrams of signals at input nodes, output nodes, and various other nodes in the input buffer circuit (400A or 400B). Figure 5 Part A is the waveform of the input voltage signal PAD at input node 102. Figure 5 Part B is the waveform of the upward tracking signal PADUP at the output of the high-side tracker 112. Figure 5 Part C is the waveform of the downward tracking signal PADDN at the output of the low-side tracker 122. Figure 5 The D part is the waveform of the upper branch enable signal ENUPB at the output of the asymmetric upper threshold circuit 410. Figure 5 The E part is the waveform of the lower branch enable signal ENDN at the output of the asymmetric lower threshold circuit 420. Figure 5The F part is the waveform of the voltage at the buffer output node BufOut. Although Figure 5 Part A and Figure 5 The F part is correspondingly the same as Figure 2 Part A and Figure 2 The F part, but Figure 5 Part B to Figure 5 Part E is modified accordingly from Figure 3 Part B to Figure 3 Part E.

[0112] along with Figure 5 In section A, the input voltage signal PAD increases at the rising edge from time ta to time tb. The asymmetric upper threshold circuit 410 operates as an asymmetric upper threshold detector 114 with a main upper threshold VTH, and the asymmetric lower threshold circuit 420 operates as an auxiliary lower threshold detector 126 with an auxiliary lower threshold VTL-. In response to... Figure 5 The downward tracking signal PADDN in section C rises before t1 across the auxiliary lower threshold VTL-, and the lower branch enable signal ENDN at the output of the asymmetric lower threshold circuit 420 (in Figure 5 In section E, the logic voltage changes from high to low. The lower branch enable signal ENDN reaches logic low before time t2. Here, time t2 is... Figure 5 The upward tracking signal PADUP in part B rises across the main upper threshold VTH at the moment. That is, time t2 is the time when the upper branch enable signal ENUPB (in the asymmetric upper threshold circuit 410) at the output of the circuit 410. Figure 5 (In part D) the moment when the logic voltage changes from high to low.

[0113] exist Figure 5 In section E, since the asymmetric lower threshold circuit 420 operates as an auxiliary lower threshold detector 126 with an auxiliary lower threshold VTL-, the downward tracking signal PADDN (in Figure 5 In section C, after the lower branch enable signal ENDN rises above the auxiliary lower threshold VTL- before time t1, it reaches a logic low voltage before time t2. For comparison, in... Figure 3 In section E, the downward tracking signal PADDN (in Figure 3 In part C, after rising above the lower threshold VTL at time t1, Figure 1C In the input buffer circuit 100C shown, the lower branch enable signal ENDN reaches a logic low voltage at time t1*, which is later than time t2. Figure 1C The input buffer circuit 100C shown is... Figure 1CThe input buffer circuit 100C shown has a risk of circuit failure between time t2 and time t1*, unlike the improved input buffer circuit (e.g., because the lower branch enable signal ENDN reaches a logic low voltage before time t2). Figures 4A to 4B The input buffer circuit (400A or 400B) reduces the risk of circuit failure after time t2. Time spread of time t1* after time t2 is suppressed, such as... Figure 5 The arrow in section E points to the true-to-false descent edge near time t1.

[0114] when Figure 5 When the input voltage signal PAD in section A decreases at the falling edge from time tc to time td, the asymmetric upper threshold circuit 410 operates as an auxiliary upper threshold detector 116 with an auxiliary upper threshold VTH+, and the asymmetric lower threshold circuit 420 operates as an asymmetric lower threshold detector 124 with a main lower threshold VTL. In response to... Figure 5 In section B, the upward tracking signal PADUP falls across the auxiliary upper threshold VTH+, and the upper branch enable signal ENUPB at the output of the asymmetric upper threshold circuit 410 (in Figure 5 In section D, the voltage changes from logic low to logic high. The upper support enable signal ENUPB reaches logic high before time t4. Here, time t4 is... Figure 5 The downward tracking signal PADDN in section C falls across the main lower threshold VTL at the moment. That is, time t4 is the time when the lower branch enable signal ENDN at the output of the asymmetric lower threshold circuit 420 (in Figure 5 (In part E) the moment when the logic voltage changes from low to high.

[0115] exist Figure 5 In part D, since the asymmetric upper threshold circuit 410 operates as an auxiliary upper threshold detector 116 with an auxiliary upper threshold VTH+, therefore... Figure 5 In part B, the upward tracking signal PADUP drops across the upper auxiliary threshold VTH+ before time t3, after which the upper support enable signal ENUPB (in Figure 5 In section D, the logic high voltage is reached before time t4. For comparison, in... Figure 3 In part D, Figure 3 In part B, the upward tracking signal PADUP drops at time t3 after crossing the upper threshold VTH. Figure 1C The upper branch enable signal ENUPB in the input buffer circuit 100C shown reaches a logic high voltage at time t3*, which is later than time t4. Figure 1CThe input buffer circuit 100C shown is... Figure 1C The input buffer circuit 100C shown has a risk of circuit failure between time t4 and time t3*, unlike the improved input buffer circuit (e.g., which has a circuit failure risk between time t4 and time t3*). This is because the upper branch enable signal ENUPB reaches a logic high voltage before time t4. Figures 4A to 4B The input buffer circuit (400A or 400B) in the circuit eliminates the risk of circuit failure after time t4. Time spread of time t3* after time t4 is suppressed, as... Figure 5 The arrow pointing to the rising edge from true to false near time t3 in part D is shown.

[0116] Figure 4B The input buffer circuit 400B in the middle (provides Figure 4A (An exemplary implementation of the input buffer circuit 400A in the example) modified from Figure 1C The input buffer circuit 100C is shown. Based on... Figure 1C The input buffer circuit 100C shown is supplemented with transmission gates 118 and 128 as components of the input buffer circuit 400B.

[0117] exist Figure 4B In the input buffer circuit 400B, there are an asymmetric upper threshold circuit 410 and an asymmetric lower threshold circuit 420. Figure 4B The asymmetric upper threshold circuit 410 in the middle (modified from Figure 1C The asymmetric upper threshold detector 114 in the middle includes a transfer gate 118 connected between the drain terminal of the PMOS transistor P1u and the drain terminal of the NMOS transistor N1u. Figure 4B The asymmetric lower threshold circuit 420 in the middle (modified from Figure 1C The asymmetric lower threshold detector 124 in the middle includes a transfer gate 128 connected between the drain terminal of the PMOS transistor P1d and the drain terminal of the NMOS transistor N4d.

[0118] In operation, each of the transmission gates 118 and 128 is controlled by the threshold selection signal 450. The operating modes of the asymmetric upper threshold circuit 410 and the asymmetric lower threshold circuit 420 depend on the received threshold selection signal 450.

[0119] In response to the threshold selection signal 450 indicating that the input voltage signal PAD increases at the rising edge, the transmission gate 118 is set to the non-transmission state (which blocks the direct conductive connection between the drain terminals of PMOS transistor P1u and NMOS transistor N1u) and the transmission gate 128 is set to the transmission state (which forms a direct conductive connection between the drain terminals of PMOS transistor P1d and NMOS transistor N4d). Therefore, at the rising edge of the input voltage signal PAD, the asymmetric upper threshold circuit 410 operates as an asymmetric upper threshold detector 114 with a main upper threshold VTH, and the asymmetric lower threshold circuit 420 operates as an auxiliary lower threshold detector 126 with an auxiliary lower threshold VTL-.

[0120] In response to the threshold selection signal 450 indicating that the input voltage signal PAD decreases at the falling edge, the transmission gate 118 is set to the transmission state (which forms a direct conductive connection between the drain terminals of the PMOS transistor P1u and the NMOS transistor N1u) and the transmission gate 128 is set to the non-transmission state (which blocks the direct conductive connection between the drain terminals of the PMOS transistor P1d and the NMOS transistor N4d). Therefore, at the falling edge of the input voltage signal PAD, the asymmetric upper threshold circuit 410 operates as an auxiliary upper threshold detector 116 with an auxiliary upper threshold VTH+, and the asymmetric lower threshold circuit 420 operates as an asymmetric lower threshold detector 124 with a main lower threshold VTL.

[0121] exist Figure 4B In the input buffer circuit 400B, both transmit gates 118 and 128 are controlled by a threshold selection signal 450. In some alternative embodiments, transmit gates 118 and 128 are controlled by two independent and related threshold selection signals. In some embodiments, the threshold selection signal 450 or other related threshold selection signals are generated based on the voltage signal at the buffer output node BufOut of the input buffer circuit. Figure 6 To reveal an instance method for generating a threshold selection signal.

[0122] Figure 6 This is a schematic diagram of an input buffer circuit 600 according to some embodiments, the input buffer circuit 600 having a threshold circuit controlled by a threshold selection signal. Figure 6 The input buffer circuit 600 in the middle is modified from Figure 4B The input buffer circuit 400B is used. Figure 6 In the middle, threshold selection signals 450U and 450D replace Figure 4BThe threshold selection signal 450 in the middle controls the transmission gates 118 and 128 accordingly. Level shifters 140U and 140D replace... Figure 4B The level shifter 140 is included. Delay circuits 610U and 610D, as well as an inverter 620, are added. Delay circuit 610U is coupled between level shifter 140U and transmit gate 118. Delay circuit 610D and inverter 620 are coupled between level shifter 140D and transmit gate 128.

[0123] In operation, the control of transmission gates 118 and 128 is based on the voltage signal at the buffer output node BufOut of the input buffer circuit. For example... Figure 5 Part A and Figure 5 As shown in section F, the voltage signal at the buffer output node BufOut is logic low before the input voltage signal PAD increases at the rising edge. The threshold selection signal 450U is set to logic false, induced by the voltage signal at the buffer output node BufOut via the delay circuit 610U. The threshold selection signal 450D is set to logic true, induced by the voltage signal at the buffer output node BufOut via the delay circuit 610D and the inverter 620. Because the threshold selection signal 450U is logic false, the transmit gate 118 is set to the non-transmit state. Because the threshold selection signal 450D is logic true, the transmit gate 128 is set to the transmit state.

[0124] In addition, such as Figure 5 Part A and Figure 5 As shown in section F, the voltage signal at the buffer output node BufOut is logic high before the input voltage signal PAD decreases at the falling edge. The threshold selection signal 450U is set to logic true, induced by the voltage signal at the buffer output node BufOut via the delay circuit 610U. The threshold selection signal 450D is set to logic false, induced by the voltage signal at the buffer output node BufOut via the delay circuit 610D and the inverter 620. In response to the threshold selection signal 450U being logic true, the transmit gate 118 is set to the transmit state. In response to the threshold selection signal 450D being logic false, the transmit gate 128 is set to the non-transmit state. Figure 6 In this circuit, the threshold selection signal 450U is generated by a first threshold selection signal circuit having a delay circuit 610U, and the threshold selection signal 450D is generated by a second threshold selection signal circuit having a delay circuit 610D and an inverter 620.

[0125] exist Figure 4B and Figure 6In some embodiments, each of the transmission gates 118 and 128 is used as a linear switch. In some alternative embodiments, either or both of the transmission gates 118 and 128 are replaced by other forms of linear switches.

[0126] Figure 7 This is a flowchart of a method 700 for generating an output voltage signal based on an input voltage signal, according to some embodiments. Figure 7 The sequence of operations used to illustrate method 700 is for illustrative purposes only; the operations of method 700 can be combined with... Figure 7 The sequences shown in the diagram can be executed using different sequences. It should be understood that... Figure 7 Additional operations are performed before, during, and / or after method 700 as illustrated herein, and some other processes may be described only briefly. See also Figure 5 Part A to Figure 5 The waveforms in part F and Figure 4B The operation of method 700 is illustrated by the input buffer circuit 400B in the diagram.

[0127] In operation 705 of method 700, the input buffer circuit determines whether the input voltage signal PAD is rising or falling. If the input voltage signal PAD is rising, the process proceeds to operation 710. If the input voltage signal PAD is falling, the process proceeds to operation 720.

[0128] In operation 710, in response to the input voltage signal PAD rising above the auxiliary lower threshold VTL- (e.g.) Figure 5 As shown in Part C), the input buffer circuit changes the lower-level enable signal from logic true to logic false (e.g., Figure 5 (As shown in section E). In Figure 4B In the embodiments, for the lower branch enable signal ENDN, logic true is represented by a logic high voltage (e.g., voltage VDDL), and logic false is represented by a logic low voltage (e.g., voltage VSS).

[0129] Then, in operation 714 following operation 710, the second switch 132 is driven to the open state. Figure 4B In one embodiment, a logic low voltage (e.g., voltage VSS) is applied to the gate terminal of the NMOS transistor MN1, which drives the second switch 132 to the off state.

[0130] In operation 730, in response to the input voltage signal PAD rising above the main upper threshold VTH (e.g. Figure 5 As shown in Part B), the input buffer circuit changes the upper-part enable signal from logic false to logic true (as shown in Part B). Figure 5 (As shown in section D). In Figure 4B In the embodiments, for the upper branch enable signal ENUPB, the logical true is represented by a logic low voltage (e.g., voltage VSSH), and the logical false is represented by a logic high voltage (e.g., voltage VDDH).

[0131] Then, in operation 734 following operation 730, the first switch 131 is driven to the connected state. Figure 4B In one embodiment, a logic low voltage (e.g., voltage VSSH) is applied to the gate terminal of the PMOS transistor MP1, which drives the first switch 131 to the connected state. After operation 734, the process proceeds to operation 705.

[0132] If the input buffer circuit determines that the input voltage signal PAD is decreasing in operation 705, the process proceeds to operation 720. In operation 720, in response to the input voltage signal PAD decreasing and crossing the auxiliary upper threshold VTH+ (e.g., ... Figure 5 As shown in Part B), the input buffer circuit changes the upper-part enable signal from logic true to logic false (e.g., Figure 5 (As shown in section D). In Figure 4B In the embodiments, for the upper branch enable signal ENUPB, the logical true is represented by a logic low voltage (e.g., voltage VSSH), and the logical false is represented by a logic high voltage (e.g., voltage VDDH).

[0133] Then, in operation 724 following operation 720, the first switch 131 is driven to the open state. Figure 4B In one embodiment, a logic high voltage (e.g., voltage VDDH) is applied to the gate terminal of the PMOS transistor MP1, which drives the first switch 131 to the off state.

[0134] In operation 740, in response to the input voltage signal PAD falling across the primary lower threshold VTL (e.g. Figure 5 As shown in Part C), the input buffer circuit changes the lower-level enable signal from logic false to logic true (as shown in Part C). Figure 5 (As shown in section E). In Figure 4B In the embodiments, for the lower branch enable signal ENDN, logic true is represented by a logic high voltage (e.g., voltage VDDL), and logic false is represented by a logic low voltage (e.g., voltage VSS).

[0135] Then, in operation 744 following operation 740, the second switch 132 is driven to the connected state. Figure 4B In one embodiment, a logic high voltage (e.g., voltage VDDL) is applied to the gate terminal of the NMOS transistor MN1, which drives the second switch 132 to the connected state.

[0136] In such Figure 1C , Figure 4B and Figure 6 In the exemplary embodiments shown, the asymmetric upper threshold detector 114 includes four PMOS transistors P1u to P4u stacked together and includes an NMOS transistor N1u, and the asymmetric lower threshold detector 124 includes four NMOS transistors N1d to N4d stacked together and includes a PMOS transistor P1d. In some alternative embodiments, the asymmetric upper threshold detector 114 includes fewer or more than four PMOS transistors. In some alternative embodiments, the asymmetric lower threshold detector 124 includes fewer or more than four NMOS transistors. Embodiments of the asymmetric upper threshold detector 114 with multiple stacks of PMOS transistors instead of four stacked PMOS transistors are within the scope of this disclosure. Embodiments of the asymmetric lower threshold detector 124 with multiple stacks of NMOS transistors instead of four stacked NMOS transistors are also within the scope of this disclosure.

[0137] In some embodiments, in the asymmetric upper threshold detector 114, each of the four PMOS transistors P1u to P4u is a standard threshold transistor. In some alternative embodiments, PMOS transistor P1u is a low threshold transistor, while the remaining three PMOS transistors P2u to P4u are standard threshold transistors. In still other alternative embodiments, the four stacked PMOS transistors P1u to P4u in the asymmetric upper threshold detector 114 are replaced by a plurality of stacked PMOS transistors P1u, P2u, ..., and Pku, where k is an integer greater than two. Among the plurality of stacked PMOS transistors, PMOS transistor P1u is a low threshold transistor, while the remaining (k-1) PMOS transistors P2u to Pku are standard threshold transistors. Because PMOS transistor P1u changes from a standard threshold transistor to a low threshold transistor, the transition speed of the upper branch enable signal ENUPB at the output of the asymmetric upper threshold detector 114 from logical true to logical false is increased. Figure 8A To illustrate some other embodiments of the asymmetric upper threshold detector 114.

[0138] In some embodiments, in the asymmetric lower threshold detector 124, each of the four NMOS transistors N1d to N4d is a standard threshold transistor. In some alternative embodiments, NMOS transistor N4d is a low threshold transistor, while the remaining three NMOS transistors N1d to N3d are standard threshold transistors. In still other alternative embodiments, the four stacked NMOS transistors N1d to N4d in the asymmetric lower threshold detector 124 are replaced by a plurality of stacked NMOS transistors N1d, N2d, ..., and Nkd, where k is an integer greater than two. Among the plurality of stacked NMOS transistors, NMOS transistor Nkd is a low threshold transistor, while the remaining (k-1) NMOS transistors N1d, N2d, ..., and N(k-1)d are standard threshold transistors. Because NMOS transistor Nkd changes from a standard threshold transistor to a low threshold transistor, the transition speed of the lower branch enable signal ENDN from logical true to logical false at the output of the asymmetric lower threshold detector 124 is improved. Figure 8B To illustrate some other embodiments of the asymmetric lower threshold detector 124.

[0139] Figure 8A This is a schematic diagram of an asymmetric upper threshold circuit according to some embodiments. Figure 8A The asymmetric upper threshold detector in the asymmetric upper threshold circuit 810 shown is modified from [previous design]. Figure 4B The asymmetric upper threshold detector in the asymmetric upper threshold circuit 410 is shown. The modification includes connecting the channel of NMOS transistor N2u between the source terminal of NMOS transistor N1u and the power supply voltage VSSH. The gate terminal of NMOS transistor N2u is biased at an N-type "intermediate bias" voltage, thus making NMOS transistor N2u function as a resistive component. Figure 8A The asymmetric upper threshold detector in the asymmetric upper threshold circuit 810 shown has an upper threshold voltage VTH+DVu, which is relatively... Figure 4B The upper threshold voltage VTH of the asymmetric upper threshold detector in the asymmetric upper threshold circuit 410 shown is greater than the positive value of DVu.

[0140] Figure 8B This is a schematic diagram of an asymmetric lower threshold circuit according to some embodiments. Figure 8B The asymmetric lower threshold detector in the asymmetric lower threshold circuit 820 shown is modified from [previous design]. Figure 4BThe asymmetric lower threshold detector in the asymmetric lower threshold circuit 420 is shown. The modification includes connecting the channel of PMOS transistor P2d between the source terminal of PMOS transistor P1d and the power supply voltage VDDL. The gate terminal of PMOS transistor P2d is biased at a P-type "intermediate bias" voltage, thus making PMOS transistor P2d function as a resistive component. Figure 8B The asymmetric lower threshold detector in the asymmetric lower threshold circuit 820 shown has a lower threshold voltage VTL-DVd, which is relatively... Figure 4B The positive value of the lower threshold voltage VTL of the asymmetric lower threshold detector in the asymmetric lower threshold circuit 420 shown.

[0141] In some embodiments, for Figure 4B The input buffer circuit 400B shown is modified to obtain an improved input buffer circuit. The modification includes utilizing... Figure 8A The asymmetric upper threshold circuit 810 shown is used to replace Figure 4B The asymmetric upper threshold circuit 410 shown utilizes Figure 8B The asymmetric lower threshold circuit 820 shown is used to replace Figure 4B The asymmetric lower threshold circuit 420 is shown. After modification, the improved input buffer circuit has an increased hysteresis window (VTH+ΔVu)-(VTL-ΔVd), which is a positive value of DVu+DVd.

[0142] This disclosure relates to an integrated circuit. The integrated circuit includes: an asymmetric upper threshold circuit having an upper branch output node configured to output an upper branch enable signal generated based on an input voltage signal; an asymmetric lower threshold circuit having a lower branch output node configured to output a lower branch enable signal generated based on the input voltage signal; and a control circuit configured to change the output voltage signal from a first voltage level to a second voltage level in response to continuous changes in the logic levels of the upper branch enable signal and the lower branch enable signal. The asymmetric upper threshold circuit is configured to set the upper branch enable signal to a first upper branch logic level in response to the input voltage signal rising above a primary upper threshold and is configured to set the upper branch enable signal to a second upper branch logic level in response to the input voltage signal falling below an auxiliary upper threshold. The auxiliary upper threshold is higher than the primary upper threshold. The asymmetric lower threshold circuit is configured to set the lower branch enable signal to a first lower branch logic level in response to a drop in the input voltage signal crossing a major lower threshold, and is configured to set the lower branch enable signal to a second lower branch logic level in response to a rise in the input voltage signal crossing an auxiliary lower threshold. The auxiliary lower threshold is lower than the major lower threshold.

[0143] According to some embodiments, the control circuit is configured to change the output voltage signal from the first voltage level to the second voltage level in response to the situation where the logic level of the upper branch enable signal is changed after the logic level of the lower branch enable signal has changed.

[0144] According to some embodiments, the control circuit is configured to change the output voltage signal from the second voltage level to the first voltage level in response to the condition that the logic level of the upper branch enable signal is changed before the logic level of the lower branch enable signal is changed.

[0145] According to some embodiments, the asymmetric upper threshold circuit includes: an N-channel metal-oxide-semiconductor transistor having a drain terminal connected to the upper branch output node; a plurality of P-channel metal-oxide-semiconductor transistors having a channel connected in series between a first voltage node and the drain terminal of the N-channel metal-oxide-semiconductor transistor; and wherein the gate terminal of the N-channel metal-oxide-semiconductor transistor is connected together with the gate terminals of the plurality of P-channel metal-oxide-semiconductor transistors.

[0146] According to some embodiments, the asymmetric lower threshold circuit includes: a P-channel metal-oxide-semiconductor transistor having a drain terminal connected to the upper branch output node; a plurality of N-channel metal-oxide-semiconductor transistors having a channel connected in series between the second voltage node and the drain terminal of the P-channel metal-oxide-semiconductor transistor; and wherein the gate terminal of the P-channel metal-oxide-semiconductor transistor is connected together with the gate terminals of the plurality of N-channel metal-oxide-semiconductor transistors.

[0147] According to some embodiments, the asymmetric upper threshold circuit further includes: a transmission gate connected between the drain terminal of the P-channel metal-oxide-semiconductor transistor and the drain terminal of one of the plurality of N-channel metal-oxide-semiconductor transistors, the conduction state of the transmission gate being controlled by a threshold selection signal.

[0148] According to some embodiments, the integrated circuit further includes: a threshold selection signal circuit having a delay circuit, and the threshold selection signal circuit being configured to generate a threshold selection signal in response to a change in the output voltage signal.

[0149] According to some embodiments, the control circuit includes: a first switch configured to be controlled by an upper branch enable signal from the upper branch output node; a second switch configured to be controlled by a lower branch enable signal from the lower branch output node; and a buffer output node located at the electrical connection between the first switch and the second switch.

[0150] According to some embodiments, the first switch is electrically connected between the first voltage node and the buffer output node; and the second switch is electrically connected between the buffer output node and the second voltage node.

[0151] According to some embodiments, the integrated circuit further includes: a regenerative circuit electrically coupled to the buffer output node and configured to maintain the voltage at the buffer output node during a time period in which the first switch is in an off state and the second switch is in an off state.

[0152] Another aspect of this disclosure relates to a method. The method includes: generating an upper branch enable signal based on a comparison of an input voltage signal with a primary upper threshold or an auxiliary upper threshold; generating a lower branch enable signal based on a comparison of the input voltage signal with a primary lower threshold or an auxiliary lower threshold; and changing an output voltage signal from a first voltage level to a second voltage level in response to continuous changes in the logic level of the upper branch enable signal and the logic level of the lower branch enable signal. Generating the upper branch enable signal includes: changing the logic level of the upper branch enable signal to a first upper branch logic level in response to the input voltage signal rising above the primary upper threshold; and changing the logic level of the upper branch enable signal to a second upper branch logic level in response to the input voltage signal falling below the auxiliary upper threshold. The auxiliary upper threshold is higher than the primary upper threshold. Generating the lower branch enable signal includes: changing the logic level of the lower branch enable signal to a first lower branch logic level in response to the input voltage signal falling below the main lower threshold; and changing the logic level of the lower branch enable signal to a second lower branch logic level in response to the input voltage signal rising above the auxiliary lower threshold. The auxiliary lower threshold is lower than the main lower threshold.

[0153] According to some embodiments, changing the output voltage signal includes changing the output voltage signal from the first voltage level to the second voltage level in response to the situation where the logic level of the upper branch enable signal is changed after the logic level of the lower branch enable signal has been changed.

[0154] According to some embodiments, changing the output voltage signal includes changing the output voltage signal from the second voltage level to the first voltage level in response to the case that the logic level of the upper branch enable signal is changed before the logic level of the lower branch enable signal is changed.

[0155] According to some embodiments, the method further includes: controlling a first switch using the upper branch enable signal, wherein the first switch is electrically connected between a first voltage node and a buffer output node, wherein the first switch is configured to be controlled by the upper branch enable signal; and controlling a second switch using the lower branch enable signal, wherein the second switch is electrically connected between the buffer output node and a second voltage node.

[0156] Another aspect of this disclosure relates to an integrated circuit. The integrated circuit includes: an asymmetric upper threshold circuit configured to output an upper branch enable signal at an upper branch output node; an asymmetric lower threshold circuit configured to output a lower branch enable signal at a lower branch output node; a first switch configured to be controlled by the upper branch enable signal from the upper branch output node; and a second switch configured to be controlled by the lower branch enable signal from the lower branch output node. Each of the asymmetric upper threshold circuit and the asymmetric lower threshold circuit includes: a first type transistor having a gate terminal and a drain terminal, the gate terminal being configured as an input terminal, the drain terminal being configured as either the upper branch output node or the lower branch output node; and a plurality of second type transistors having a channel connected in series between a voltage node and the drain terminal of the first type transistor. The plurality of second type transistors have gate terminals, all of which are connected to the gate terminal of the first type transistor.

[0157] According to some embodiments, the first type of transistor in the asymmetric upper threshold circuit is an N-channel metal-oxide-semiconductor transistor; and the plurality of second type transistors in the asymmetric upper threshold circuit are P-channel metal-oxide-semiconductor transistors.

[0158] According to some embodiments, the first type of transistor in the asymmetric lower threshold circuit is a P-channel metal-oxide-semiconductor transistor; and the plurality of second type transistors in the asymmetric lower threshold circuit are N-channel metal-oxide-semiconductor transistors.

[0159] According to some embodiments, the integrated circuit further includes: a linear switch connected between the drain terminal of the first type transistor and the drain terminal of one of the plurality of second type transistors, the on state of the linear switch being controlled by a threshold selection signal.

[0160] According to some embodiments, the integrated circuit further includes: a threshold selection signal circuit having a delay circuit, and the threshold selection signal circuit being configured to generate the threshold selection signal in response to a change in the output voltage signal from a first voltage level to a second voltage level.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An integrated circuit with a variable threshold circuit, characterized in that, include: An asymmetric upper threshold circuit has an upper branch output node configured to output an upper branch enable signal generated based on an input voltage signal. The asymmetric upper threshold circuit is configured to set the upper branch enable signal to a first upper branch logic level in response to the input voltage signal rising above a major upper threshold and is configured to set the upper branch enable signal to a second upper branch logic level in response to the input voltage signal falling below an auxiliary upper threshold, wherein the auxiliary upper threshold is higher than the major upper threshold. An asymmetric lower threshold circuit has a lower branch output node configured to output a lower branch enable signal generated based on the input voltage signal, wherein the asymmetric lower threshold circuit is configured to set the lower branch enable signal to a first lower branch logic level in response to a drop in the input voltage signal crossing a major lower threshold and is configured to set the lower branch enable signal to a second lower branch logic level in response to a rise in the input voltage signal crossing an auxiliary lower threshold, wherein the auxiliary lower threshold is lower than the major lower threshold; as well as The control circuit is configured to change the output voltage signal from a first voltage level to a second voltage level in response to a continuous change in the logic level of the upper branch enable signal and the logic level of the lower branch enable signal.

2. The integrated circuit of claim 1, wherein, The control circuit is configured to change the output voltage signal from the first voltage level to the second voltage level in response to the situation where the logic level of the upper support enable signal is changed after the logic level of the lower support enable signal has changed. Alternatively, the control circuit is configured to change the output voltage signal from the second voltage level to the first voltage level in response to the case that the logic level of the upper branch enable signal is changed before the logic level of the lower branch enable signal is changed.

3. The integrated circuit of claim 1, wherein, The asymmetric upper threshold circuit includes: An N-channel metal-oxide-semiconductor transistor having a drain terminal connected to the upper branch output node; A plurality of P-channel metal-oxide-semiconductor transistors, each having a channel connected in series between a first voltage node and the drain terminal of the N-channel metal-oxide-semiconductor transistor; and The gate terminals of the N-channel metal-oxide-semiconductor transistors are connected together with the gate terminals of the plurality of P-channel metal-oxide-semiconductor transistors.

4. The integrated circuit of claim 3, wherein, The asymmetric upper threshold circuit further includes: A transmission gate is connected between the drain terminal of the N-channel metal-oxide-semiconductor transistor and the drain terminal of one of the plurality of P-channel metal-oxide-semiconductor transistors, and the conduction state of the transmission gate is controlled by a threshold selection signal.

5. The integrated circuit of claim 1, wherein, The asymmetric lower threshold circuit includes: A P-channel metal-oxide-semiconductor transistor having a drain terminal connected to the upper branch output node; A plurality of N-channel metal-oxide-semiconductor transistors, each having a channel connected in series between a second voltage node and the drain terminal of the P-channel metal-oxide-semiconductor transistor; and The gate terminals of the P-channel metal-oxide-semiconductor transistors are connected together with the gate terminals of the plurality of N-channel metal-oxide-semiconductor transistors.

6. The integrated circuit of claim 5, wherein, The asymmetric upper threshold circuit further includes: A transmission gate is connected between the drain terminal of the P-channel metal-oxide-semiconductor transistor and the drain terminal of one of the plurality of N-channel metal-oxide-semiconductor transistors, and the conduction state of the transmission gate is controlled by a threshold selection signal.

7. An integrated circuit having a variable threshold circuit, comprising: include: The asymmetric upper threshold circuit is configured to output an upper branch enable signal at the upper branch output node; The asymmetric lower threshold circuit is configured to output a lower branch enable signal at the lower branch output node; The first switch is configured to be controlled by the upper branch enable signal from the upper branch output node; as well as The second switch is configured to be controlled by the lower branch enable signal from the lower branch output node, wherein each of the asymmetric upper threshold circuit and the asymmetric lower threshold circuit includes: A first type of transistor has a gate terminal and a drain terminal, the gate terminal being configured as an input terminal and the drain terminal being configured as either the upper branch output node or the lower branch output node. A plurality of second-type transistors have channels connected in series between a voltage node and the drain terminal of a first-type transistor. The plurality of second-type transistors have gate terminals, all of which are connected to the gate terminal of the first-type transistor.

8. The integrated circuit according to claim 7, characterized in that: The first type of transistor in the asymmetric upper threshold circuit is an N-channel metal-oxide-semiconductor transistor; and The plurality of second-type transistors in the asymmetric upper threshold circuit are P-channel metal-oxide-semiconductor transistors.

9. The integrated circuit according to claim 7, characterized in that: The first type of transistor in the asymmetric lower threshold circuit is a P-channel metal-oxide-semiconductor transistor; and The plurality of second-type transistors in the asymmetric lower threshold circuit are N-channel metal-oxide-semiconductor transistors.

10. The integrated circuit according to claim 7, characterized in that, Including: A linear switch is connected between the drain terminal of the first type of transistor and the drain terminal of one of the plurality of second type transistors, and the conduction state of the linear switch is controlled by a threshold selection signal.

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