Post-packaging trimming circuit for special chip for electronic cigarette
By designing a post-packaging adjustment circuit in a dedicated chip for electronic cigarettes, the problem of post-packaging EFUSE adjustment was solved, enabling parameter correction after packaging, avoiding chip scrapping, and reducing resource waste and circuit complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HANGZHOU YIXIN MICRO TECH CO LTD
- Filing Date
- 2025-03-27
- Publication Date
- 2026-04-21
AI Technical Summary
In the existing technology, it is difficult to adjust EFUSE after the electronic cigarette dedicated chip is packaged, which leads to incorrect adjustment before packaging, resulting in chip scrap, waste of resources and increased costs.
Design a post-package adjustment circuit that allows modification of parameters stored in EFUSE after packaging by adding an interface circuit inside the chip. Utilize the chip's original pins to achieve flexible switching of input/output functions, including improvements to the VCC, VDD, and OUT port circuits.
This allows for the correction of EFUSE parameters after packaging, preventing chip scrap, reducing resource waste, lowering circuit complexity and failure risk, and avoiding an increase in chip area and design complexity.
Smart Images
Figure CN224140198U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic cigarette dedicated chip technology, specifically to a post-packaging adjustment circuit for electronic cigarette dedicated chips. Background Technology
[0002] With the continuous development of e-cigarette technology, the performance and safety requirements for dedicated e-cigarette chips are becoming increasingly stringent. EFUSE (Electronic Fuse), as a one-time programmable storage component, is frequently used to store critical configuration information for chips. However, in the design and manufacturing process of some chips, it is often difficult to further adjust the EFUSE after chip packaging. This can lead to situations where, after chip packaging, errors are discovered in the EFUSE, or adjustments to the data in the EFUSE are needed to meet different requirements. In such cases, effective adjustments cannot be made to the chip after packaging, resulting in wasted production costs and limiting the flexibility of chip functionality.
[0003] In the existing technology, EFUSE adjustment is mainly completed before chip packaging. Once packaging is completed, the circuit will be wrapped by the packaging material and physically isolated from the outside, making it difficult to operate EFUSE. If EFUSE information is found to be incorrect after packaging, it cannot be easily corrected, and the chip can only be discarded, resulting in waste of resources and increased costs. Utility Model Content
[0004] To address the shortcomings of existing technologies, this application proposes a post-packaging adjustment circuit for electronic cigarette-specific chips, which allows for the correction of parameters stored in EFUSE after chip packaging, avoiding chip scrapping due to pre-packaging adjustment errors and reducing resource waste.
[0005] This utility model provides the following technical solution: a post-packaging adjustment circuit for a dedicated chip in electronic cigarettes, comprising: a chip; the SE port of the chip is connected to a capacitive sensor; the OUT port of the chip is connected to a load resistor; the LED port of the chip is connected to an LED; a first capacitor and a lithium battery are connected in parallel to the VDD port of the chip; the other ends of the LED, the load resistor, the capacitive sensor, the first capacitor, and the lithium battery are grounded; the VDD port of the chip is connected to a VDD port circuit; the VCC port of the chip is connected to a VCC port circuit; and the OUT port of the chip is connected to an OUT port circuit.
[0006] As a preferred embodiment of this utility model, the VCC port circuit includes a third resistor, a third capacitor, and a VCC interface logic circuit.
[0007] The VCC port is connected to the third resistor, and the other end of the third resistor is connected in parallel with the third capacitor and the VCC interface logic circuit. The other end of the third capacitor is grounded.
[0008] As a preferred embodiment of this utility model, the VDD port circuit includes an amplifier, a first resistor, an NMOS transistor, a resistor string, and a second resistor;
[0009] The VDD port is connected to the first resistor, the other end of the first resistor is connected to the drain of the NMOS transistor, the source of the NMOS transistor is connected to the second resistor and the input of the amplifier, the output of the amplifier is connected to the gate of the NMOS transistor, the other end of the second resistor is connected to a resistor string, and the TRIMCODE input interface of the resistor string is used to input the adjustment code. The resistor string adjusts the reference voltage according to the input TRIMCODE.
[0010] As a preferred embodiment of this invention, the amplifier uses a 1.2V reference voltage as its input.
[0011] As a preferred embodiment of this utility model, the VCC port circuit includes a comparator, a fourth resistor, a second capacitor, and a hysteresis circuit.
[0012] The OUT port is connected to the fourth resistor, the other end of the fourth resistor is connected to the second capacitor and the input of the comparator, the other end of the second capacitor is grounded, the output of the comparator is connected to the hysteresis circuit, and the other end of the hysteresis circuit is used for output.
[0013] The beneficial effects of this utility model are:
[0014] 1. In this utility model, the parameters stored in EFUSE can be corrected after chip packaging, avoiding chip scrapping due to incorrect adjustment before packaging and reducing resource waste;
[0015] 2. In this utility model, the input / output function can be flexibly switched through the original pins of the chip, without the need to add new pins, thus avoiding the problems of increased chip area, increased design complexity and increased production cost;
[0016] 3. In this utility model, only an interface circuit needs to be added inside the chip, without the need for complex external components, which reduces circuit complexity and failure risk. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of an electronic cigarette chip circuit system.
[0018] Figure 2 The interface circuit for receiving external adjustment commands at the VCC terminal;
[0019] Figure 3 This is a timing diagram for read / write modes;
[0020] Figure 4 This is a schematic diagram of the reference voltage divider.
[0021] Figure 5This is a schematic diagram of the circuit connected to the VDD port.
[0022] In the diagram: 100, Chip; 101, Capacitive Sensor; 102, LED; 103, First Capacitor; 105, VCC Port; 106, Ground Terminal; 107, Load Resistor; 108, Lithium Battery; 201, Amplifier; 202, First Resistor; 203, NMOS Transistor; 204, Resistor String; 205, Second Resistor; 301, Comparator; 302, Fourth Resistor; 303, Second Capacitor; 304, Hysteresis Circuit; 401, Third Resistor; 402, Third Capacitor; 403, VCC Interface Logic Circuit. Detailed Implementation
[0023] To make the technical problems solved by this utility model, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of this utility model will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0024] Example
[0025] like Figures 1 to 5 As shown, a post-packaging adjustment circuit for an electronic cigarette-specific chip 100 includes:
[0026] Chip 100, the SE port of chip 100 is connected to capacitive sensor 101, and the other end of capacitive sensor 101 is connected to ground terminal 106;
[0027] The OUT port of chip 100 is connected to load resistor 107, and the other end of load resistor 107 is connected to ground terminal 106;
[0028] The LED port of chip 100 is connected to LED 102, and the other end of LED 102 is connected to ground terminal 106;
[0029] A first capacitor 103 and a lithium battery 108 are connected in parallel to the VDD port of chip 100, and the other end of the first capacitor 103 and the lithium battery 108 are connected to the ground terminal 106.
[0030] The GND port of chip 100 is grounded at terminal 106.
[0031] In this embodiment, the VCC port 105 of the chip 100 is connected to the VCC port 105 circuit. The VCC port circuit includes a third resistor 401, a third capacitor 402, and a VCC interface logic circuit 403. The VCC interface logic circuit 403 is used to determine whether to enter the programming mode or the reading mode based on the level signal. The VCC port 105 is connected to the third resistor 401. The other end of the third resistor 401 is connected in parallel with the third capacitor 402 and the VCC interface logic circuit 403. The other end of the third capacitor 402 is connected to the ground terminal 106.
[0032] The VCC port 105 circuit is an interface circuit for receiving external tuning commands and is used to detect whether to enter tuning mode. If this interface circuit receives 8 square wave signal inputs within a 100ms time window, the output terminal CS of the VCC interface logic circuit 403 will output a high-level signal, while the output terminal RW will output a low-level signal. This signal combination clearly indicates that the system has entered the programming mode within the tuning mode, in which the system can program the efuse. If the interface circuit receives 16 square wave signal inputs within the same 100ms time range, then both the output terminals CS and RW of the VCC interface logic circuit 403 will be high-level. This output state indicates that the system will enter the efuse data reading mode within the tuning mode.
[0033] In this embodiment, the VDD port of chip 100 is connected to a VDD port circuit, which includes an amplifier 201, a first resistor 202, an NMOS transistor 203, a resistor string 204, and a second resistor 205. The VDD port is connected to the first resistor 202, the other end of which is connected to the drain of the NMOS transistor 203. The source of the NMOS transistor 203 is connected to the second resistor 205 and the input terminal of the amplifier 201. The output terminal of the amplifier 201 is connected to the gate of the NMOS transistor 203. The amplifier 201 uses a 1.2V reference voltage as its input. The other end of the second resistor 205 is connected to the resistor string 204. The TRIMCODE input interface of the resistor string 204 is used to input a tuning code. The resistor string 204 adjusts the reference voltage according to the input TRIMCODE.
[0034] The output of amplifier 201 and its connected resistor string 204 have an impact. Amplifier 201 uses VREF = 1.2V as a reference input, performs voltage division through resistor string 204, and resistor string 204 adjusts the voltage of vrefn according to the tuning code of the TRI MCODE input interface.
[0035] In this embodiment, the OUT port of chip 100 is connected to the OUT port circuit, and the VCC port 105 circuit includes a comparator 301, a fourth resistor 302, a second capacitor 303, and a hysteresis circuit 304. The OUT port is connected to the fourth resistor 302, the other end of the fourth resistor 302 is connected to the second capacitor 303 and the input terminal of the comparator 301, the other end of the second capacitor 303 is connected to the ground terminal 106, the output terminal of the comparator 301 is connected to the hysteresis circuit 304, and the other end of the hysteresis circuit 304 provides an output.
[0036] Implementation: The VCC port 105 circuit receives external adjustment commands and checks whether adjustment mode needs to be entered. If the interface circuit receives 8 square wave signal inputs within a 100ms time window, the output terminal CS of the VCC interface logic circuit 403 will output a high-level signal, while the output terminal RW will output a low-level signal, entering the programming mode within the adjustment mode. If the interface circuit receives 16 square wave signal inputs within the same 100ms time range, then both the output terminals CS and RW of the VCC interface logic circuit 403 will be high-level, entering the efuse data reading mode within the adjustment mode.
[0037] Reading mode: The LED terminal becomes the data output port for the efuse resistor, while the OUT terminal, originally an output, becomes an input, acting as the SCLK for the efuse resistor to select the data for a specific efuse resistor. A CLK signal must be input for each efuse resistor.
[0038] Programming mode: Both the LED terminal and the OUT terminal will change from input terminals to input terminals. The OUT terminal is still responsible for inputting the SCLK signal, which is used as the basis for selecting a specific efuse resistor. The LED terminal is used to control the programming operation of the selected efuse resistor, that is, to determine whether the programming operation is performed on the efuse resistor.
[0039] After entering the adjustment mode, the chip 100 can exit the adjustment mode in two ways. The first way is to power on again, by cutting off the current power supply and then restoring the power supply, the chip 100 will exit the adjustment mode. The second way is to apply a continuous high-level signal to the VCC terminal of the chip 100 and maintain the high-level state for a time range of 100ms, the chip 100 will exit the adjustment mode.
[0040] This invention allows for the correction of parameters stored in EFUSE after chip 100 is packaged, avoiding chip 100 scrap due to incorrect adjustment before packaging and reducing resource waste; it enables flexible switching of input / output functions through the original pins of chip 100 without the need for additional pins, avoiding the problems of increased chip 100 area, increased design complexity and increased production costs; it only requires adding interface circuits inside chip 100, without the need for complex external components, reducing circuit complexity and failure risk.
[0041] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.
[0042] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. A post-package trimming circuit for a chip dedicated to an electronic cigarette, characterized in that, Includes: a chip, the SE port of the chip is connected to a capacitive sensor, the OUT port of the chip is connected to a load resistor, the LED port of the chip is connected to an LED, the VDD port of the chip is connected in parallel with a first capacitor and a lithium battery, the other end of the LED, load resistor, capacitive sensor, first capacitor and lithium battery is grounded, the VDD port of the chip is connected to the VDD port circuit, the VCC port of the chip is connected to the VCC port circuit, and the OUT port of the chip is connected to the OUT port circuit.
2. The post-package trimming circuit for the chip specially used in the electronic cigarette according to claim 1, characterized in that, The VCC port circuit includes a third resistor, a third capacitor, and VCC interface logic circuitry. The VCC port is connected to a third resistor, and the other end of the third resistor is connected in parallel with a third capacitor and the VCC interface logic circuit. The other end of the third capacitor is grounded.
3. The post-package trimming circuit for the chip specially used in the electronic cigarette according to claim 1, characterized in that, The VDD port circuit includes an amplifier, a first resistor, an NMOS transistor, a resistor string, and a second resistor. The VDD port is connected to the first resistor, the other end of which is connected to the drain of the NMOS transistor. The source of the NMOS transistor is connected to the second resistor and the input terminal of the amplifier. The output terminal of the amplifier is connected to the gate of the NMOS transistor. The other end of the second resistor is connected to the resistor string. The TRIMCODE input interface of the resistor string is used to input a trimming code. The resistor string adjusts the reference voltage according to the input TRIMCODE.
4. The post-package trimming circuit for the chip specially used in the electronic cigarette according to claim 3, characterized in that, The amplifier uses a 1.2V reference voltage as its input.
5. The post-package trimming circuit for the chip specially used in the electronic cigarette according to claim 1, characterized in that, The VCC port circuit includes a comparator, a fourth resistor, a second capacitor, and a hysteresis circuit. The OUT port is connected to the fourth resistor, the other end of the fourth resistor is connected to the second capacitor and the input of the comparator, the other end of the second capacitor is grounded, the output of the comparator is connected to the hysteresis circuit, and the other end of the hysteresis circuit is used for output.