Intelligent charging system

Abstract

The utility model discloses an intelligent power supply system, and specifically relates to the power supply management field, the intelligent power supply system comprises an input filter network, the input filter network comprises a resistor R7, one end of the resistor R7 is connected with an input terminal VIN, the other end of the resistor R7 is successively connected with three parallel capacitors, the three parallel capacitors are respectively a capacitor C2, a capacitor C3 and a capacitor C4, and the capacitor C2, the capacitor C3 and the capacitor C4 are connected with the input terminal VIN. The other ends of the three parallel capacitors are all connected with a ground wire GND and are used for filtering ripples of the input end VIN and stabilizing voltage; and the boost power conversion module comprises an inductor L1, one end of the inductor L1 is connected with an output node of the input filter network, and the other end of the inductor L1 is connected with a boost node N1. By constructing a multi-stage coupling control access including input filtering, boost control, overvoltage clamping, current sampling and output feedback regulation, a quick response to power disturbance, load fluctuation and an abnormal state and a self-adaptive power supply regulation mechanism are realized.

Description

Technical Field

[0001] This utility model relates to the field of power management technology, and more specifically, to an intelligent power replenishment system. Background Technology

[0002] In the existing technology, for power supply scenarios of lithium batteries or portable devices, conventional power replenishment circuits mostly rely on fixed topology and simple PWM control to achieve boost output. However, such circuits usually lack dynamic response mechanisms to input voltage fluctuations, output load changes and overcurrent abnormalities. Especially in high-frequency interference, power instability or load start-up, problems such as output voltage jitter, unstable MOSFET drive or feedback lag are likely to occur.

[0003] In addition, the existing system lacks real-time monitoring and overvoltage protection for the current state of the power transistor, which makes it easy for the device to break down or the whole machine to fail when there is a pulse current disturbance or a load short circuit, seriously affecting the stability and safety of the system.

[0004] Therefore, how to construct an intelligent power supply system with multiple coupled mechanisms such as input filtering, overvoltage clamping, current sampling, output feedback and drive buffering has become a key issue in improving power supply reliability. Utility Model Content

[0005] To overcome the aforementioned deficiencies of the prior art, embodiments of this utility model provide an intelligent power replenishment system. By constructing a multi-level coupled control path including input filtering, boost control, overvoltage clamping, current sampling, and output feedback regulation, it achieves a rapid response and adaptive power replenishment regulation mechanism to power disturbances, load fluctuations, and abnormal states, thereby solving the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: an intelligent power replenishment system, comprising:

[0007] An input filtering network includes a resistor R7. One end of the resistor R7 is connected to the input terminal VIN, and the other end of the resistor R7 is connected to three parallel capacitors: capacitor C2 (0.1μF, labeled 104), capacitor C3 (0.1μF, labeled 104), and capacitor C4 (100μF). The other ends of the three parallel capacitors are all connected to ground GND to achieve ripple filtering and voltage stabilization of the input terminal VIN.

[0008] A boost power conversion module includes an inductor L1 (with an inductance value of 150μH), one end of which is connected to the output node of the input filter network, and the other end of which is connected to a boost node N1; the boost node N1 is sequentially connected to device one, device two, and device three.

[0009] The main power switch control network includes an N-channel MOSFET Q1, the drain of which is connected to the boost node N1. The source of the MOSFET Q1 is connected to two parallel resistors R16 and R17, both with a resistance of 0.024Ω, and they are grounded together. The gate of the MOSFET Q1 is connected to the collector of an NPN transistor Q2 through a series resistor R13 (15Ω) and a pull-up resistor R14 (10KΩ). A resistor R10 (10Ω) and a capacitor C10 (2.2nF, reference numeral 222) are also connected in parallel between the drain of the MOSFET Q1 and the cathode of the Schottky diode D1.

[0010] The control chip U1 (model U3500C) includes the following pin connections:

[0011] Pin 1 (EN) and pin 8 (VIN) are both connected to the cathode of the Schottky diode D1;

[0012] Pin 7, VS, is connected to the cathode of D1;

[0013] Pin 6 SW is connected to the drain of the MOSFET Q1;

[0014] Pin 3 IS is connected to the source node of the MOSFET Q1 via resistor R9 (10Ω);

[0015] A capacitor C8 (1nF, labeled 102) is connected in parallel between pin 3 IS and ground;

[0016] Pin 2, FB, is connected to the output feedback network;

[0017] Pin 5 (VB) and pin 4 (GND) are both connected to ground (GND).

[0018] In a preferred embodiment, device one is a parallel branch consisting of resistor R3 (resistance value of 10Ω) and capacitor C1 (capacity of 2.2nF, labeled 222), used for spike suppression;

[0019] Device 2 is a Schottky diode D1, whose anode is connected to the output terminal of the parallel branch, and whose cathode is connected in sequence to the VIN pin (pin 8), EN pin (pin 1) and VS pin (pin 7) of the control chip U1;

[0020] Device 3 is a MOSFET Q1, whose drain is directly connected to the boost node N1, forming the main power switching path.

[0021] In a preferred embodiment, the overvoltage clamping control module includes:

[0022] The transistor Q2 (model 5551) has its emitter grounded and its base connected to the input terminal of the inductor L1 through a series resistor R18 (3KΩ) and a resistor R19 (100KΩ).

[0023] Zener diode D2 (12V regulated voltage) has its cathode connected to the junction of resistors R18 and R19, and its anode grounded.

[0024] The collector of transistor Q2 is connected to the gate of MOSFET Q1 to achieve overvoltage protection and clamping control of MOSFET Q1.

[0025] A capacitor C12 (labeled 104) is connected in parallel between the collector of transistor Q2 and ground to suppress drive spike voltage.

[0026] In a preferred embodiment, the output filtering and feedback control network includes:

[0027] Resistor R8 (47KΩ) is connected in series between the VIN pin of the control chip U1 and the output voltage terminal VOUT;

[0028] Three parallel capacitors C5 (0.1μF, labeled 104), C6 (0.1μF, labeled 104) and C7 (100μF) form an output filter network. The common terminal of the three parallel capacitors is connected to the output voltage terminal VOUT, and the other terminal is grounded.

[0029] Three-stage series resistor voltage divider: resistors R5 (56KΩ), R6 (270KΩ) and R12 (15KΩ) are connected in series and connected to the output voltage terminal VOUT. One end is grounded and the other end is connected to the FB pin (pin 2) of the control chip U1 to realize output voltage feedback regulation.

[0030] The current limiting protection network consists of resistor R11 (330Ω) and resistor R15 (1KΩ) connected in series and connected between the output voltage terminal VOUT and ground; the output voltage terminal VOUT is also connected in parallel with a set of capacitor C9 marked NC (unconnected), resistor R4, and parallel capacitor C11 as a reserved space for filter expansion.

[0031] In a preferred embodiment, the signal interface network includes signal test interface terminals numbered 1 to 8:

[0032] Connect resistor R1 (470KΩ) to interface 1, and connect resistor R2 (marked NC) to interface 2;

[0033] Interface 3 is the output voltage terminal VOUT;

[0034] Interfaces 4 and 5 are the midpoints of the voltage divider;

[0035] Interfaces 6, 7, and 8 are all connected to ground (GND).

[0036] In a preferred embodiment, the IS pin of the control chip U1 is connected to the source of the MOSFET Q1 through a current-limiting resistor R9. The source of the MOSFET Q1 is grounded through parallel resistors R16 and R17. A capacitor C8 is connected in parallel between the third pin IS and ground to construct a current sampling and overcurrent feedback path, thereby enabling real-time monitoring of the current of the MOSFET Q1 in the on state.

[0037] In a preferred embodiment, resistors R5, R6, and R12 in the output filtering and feedback control network constitute a multi-stage series voltage divider. The connection node between resistors R6 and R12 in the voltage divider is connected to the FB pin of the control chip U1. The output terminal of the output filtering and feedback control network is also connected in parallel with capacitors C5, C6, and C7 to stabilize the output voltage. Resistors R11 and R15 are provided in the branch output to ground for current limiting protection. At the same time, parallel branch capacitors C9, R4, and C11 are reserved at the output terminal for filter structure expansion.

[0038] The technical effects and advantages of this utility model are as follows:

[0039] 1. By constructing an input filter network consisting of resistors and three capacitors of different capacitance values ​​on the input side, the high-frequency interference and voltage ripple in the input power supply are effectively reduced, providing a stable voltage foundation for the subsequent boost process. This solves the fundamental problem of existing power supply systems being prone to output jitter and startup failure when the power supply is unstable.

[0040] 2. By setting a spike absorption branch consisting of a resistor and a capacitor after the inductor L1, and introducing a boost channel consisting of a fast Schottky diode and a MOSFET Q1, the voltage spikes during high-frequency switching are suppressed and energy is rectified efficiently.

[0041] 3. By designing an overvoltage clamping control module based on transistor Q2, Zener diode D2 and resistor divider, the MOS gate is pulled low in time when the voltage at the boost node rises abnormally, forming a closed-loop clamping channel to avoid MOSFET mis-conduction or chip breakdown caused by overvoltage.

[0042] 4. By setting a dual-resistor parallel sampling path at the source of the MOSFET, and combining a current-limiting resistor and a filter capacitor, the signal is introduced into the IS pin of the control chip U1 to achieve real-time sampling feedback of the conduction current.

[0043] 5. By constructing a three-stage series voltage divider network at the output end and feeding it back to the FB pin of the control chip, and in conjunction with a current limiting branch and a filter capacitor bank, dynamic detection and error correction of the output voltage can be achieved. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the main circuit structure of the intelligent power replenishment system in this utility model. Detailed Implementation

[0045] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0046] Refer to the instruction manual appendix Figure 1 An embodiment of the present invention provides an intelligent power replenishment system, comprising:

[0047] An input filtering network includes a resistor R7. One end of the resistor R7 is connected to the input terminal VIN, and the other end of the resistor R7 is connected to three parallel capacitors: capacitor C2 (0.1μF, labeled 104), capacitor C3 (0.1μF, labeled 104), and capacitor C4 (100μF). The other ends of the three parallel capacitors are all connected to ground GND to achieve ripple filtering and voltage stabilization of the input terminal VIN.

[0048] A boost power conversion module includes an inductor L1 (with an inductance value of 150μH), one end of which is connected to the output node of the input filter network, and the other end of which is connected to a boost node N1; the boost node N1 is sequentially connected to device one, device two, and device three.

[0049] The main power switch control network includes an N-channel MOSFET Q1, the drain of which is connected to the boost node N1. The source of the MOSFET Q1 is connected to two parallel resistors R16 and R17, both with a resistance of 0.024Ω, and they are grounded together. The gate of the MOSFET Q1 is connected to the collector of an NPN transistor Q2 through a series resistor R13 (15Ω) and a pull-up resistor R14 (10KΩ). A resistor R10 (10Ω) and a capacitor C10 (2.2nF, reference numeral 222) are also connected in parallel between the drain of the MOSFET Q1 and the cathode of the Schottky diode D1.

[0050] The control chip U1 (model U3500C) includes the following pin connections:

[0051] Pin 1 (EN) and pin 8 (VIN) are both connected to the cathode of the Schottky diode D1;

[0052] Pin 7, VS, is connected to the cathode of D1;

[0053] Pin 6 SW is connected to the drain of the MOSFET Q1;

[0054] Pin 3 IS is connected to the source node of the MOSFET Q1 via resistor R9 (10Ω);

[0055] A capacitor C8 (1nF, labeled 102) is connected in parallel between pin 3 IS and ground;

[0056] Pin 2, FB, is connected to the output feedback network;

[0057] Pin 5 (VB) and pin 4 (GND) are both connected to ground (GND).

[0058] In a preferred embodiment, device one is a parallel branch consisting of resistor R3 (resistance value of 10Ω) and capacitor C1 (capacity of 2.2nF, labeled 222), used for spike suppression;

[0059] Device 2 is a Schottky diode D1, whose anode is connected to the output terminal of the parallel branch, and whose cathode is connected in sequence to the VIN pin (pin 8), EN pin (pin 1) and VS pin (pin 7) of the control chip U1;

[0060] Device 3 is a MOSFET Q1, whose drain is directly connected to the boost node N1, forming the main power switching path.

[0061] In a preferred embodiment, the overvoltage clamping control module includes:

[0062] The transistor Q2 (model 5551) has its emitter grounded and its base connected to the input terminal of the inductor L1 through a series resistor R18 (3KΩ) and a resistor R19 (100KΩ).

[0063] Zener diode D2 (12V regulated voltage) has its cathode connected to the junction of resistors R18 and R19, and its anode grounded.

[0064] The collector of transistor Q2 is connected to the gate of MOSFET Q1 to achieve overvoltage protection and clamping control of MOSFET Q1.

[0065] A capacitor C12 (labeled 104) is connected in parallel between the collector of transistor Q2 and ground to suppress drive spike voltage.

[0066] In a preferred embodiment, the output filtering and feedback control network includes:

[0067] Resistor R8 (47KΩ) is connected in series between the VIN pin of the control chip U1 and the output voltage terminal VOUT;

[0068] Three parallel capacitors C5 (0.1μF, labeled 104), C6 (0.1μF, labeled 104) and C7 (100μF) form an output filter network. The common terminal of the three parallel capacitors is connected to the output voltage terminal VOUT, and the other terminal is grounded.

[0069] Three-stage series resistor voltage divider: resistors R5 (56KΩ), R6 (270KΩ) and R12 (15KΩ) are connected in series and connected to the output voltage terminal VOUT. One end is grounded and the other end is connected to the FB pin (pin 2) of the control chip U1 to realize output voltage feedback regulation.

[0070] The current limiting protection network consists of resistor R11 (330Ω) and resistor R15 (1KΩ) connected in series and connected between the output voltage terminal VOUT and ground; the output voltage terminal VOUT is also connected in parallel with a set of capacitor C9 marked NC (unconnected), resistor R4, and parallel capacitor C11 as a reserved space for filter expansion.

[0071] In a preferred embodiment, the signal interface network includes signal test interface terminals numbered 1 to 8:

[0072] Connect resistor R1 (470KΩ) to interface 1, and connect resistor R2 (marked NC) to interface 2;

[0073] Interface 3 is the output voltage terminal VOUT;

[0074] Interfaces 4 and 5 are the midpoints of the voltage divider;

[0075] Interfaces 6, 7, and 8 are all connected to ground (GND).

[0076] In a preferred embodiment, the IS pin of the control chip U1 is connected to the source of the MOSFET Q1 through a current-limiting resistor R9. The source of the MOSFET Q1 is grounded through parallel resistors R16 and R17. A capacitor C8 is connected in parallel between the third pin IS and ground to construct a current sampling and overcurrent feedback path, thereby enabling real-time monitoring of the current of the MOSFET Q1 in the on state.

[0077] In a preferred embodiment, resistors R5, R6, and R12 in the output filtering and feedback control network constitute a multi-stage series voltage divider. The connection node between resistors R6 and R12 in the voltage divider is connected to the FB pin of the control chip U1. The output terminal of the output filtering and feedback control network is also connected in parallel with capacitors C5, C6, and C7 to stabilize the output voltage. Resistors R11 and R15 are provided in the branch output to ground for current limiting protection. At the same time, parallel branch capacitors C9, R4, and C11 are reserved at the output terminal for filter structure expansion.

[0078] It should be further noted that, with lithium battery-powered devices and portable terminals gradually evolving towards higher power and multitasking capabilities, traditional power replenishment system designs are no longer sufficient to meet the comprehensive requirements of "stability, high-speed response, and self-protection against abnormal conditions." Conventional power replenishment circuits mostly employ a single topology and static PWM boost strategy. While this design can maintain basic operation under ideal power supply and constant load scenarios, it faces a series of problems in real-world applications:

[0079] When the input power supply has ripple, voltage drop, or rapid load switching, such systems usually lack sufficient input buffering and feedback regulation capabilities, leading to unstable phenomena such as output voltage jitter, control signal lag, or even system restart. When a large current surge or short-circuit fault occurs, the lack of dynamic detection and protection mechanisms for the power channel current state can easily cause MOSFET breakdown or system failure, seriously threatening power supply safety. In addition, the feedback system is often overly simplified in structure, unable to finely adjust the output response path, resulting in low energy efficiency and large output fluctuations.

[0080] This solution addresses the aforementioned issues and is not a simple superposition of traditional boost topologies. Instead, it is an intelligent power supply system architecture composed of "input filtering, boost conversion, drive protection, feedback control, and signal sampling." Its core design concept is to build a full-stack power output platform with multi-path adjustment capabilities and anomaly self-suppression capabilities, with real-time response capability as the main axis.

[0081] The input filter network introduces a π-type filter structure consisting of resistor R7 and three parallel capacitors (C2, C3, C4), which effectively alleviates high-frequency interference and low-frequency ripple in the input voltage and provides a stable voltage foundation for the subsequent boost module.

[0082] The boost section uses inductor L1 to construct an energy storage channel, with the back end of the inductor connected to boost node N1. Three key components are designed here: first, a parallel branch of resistor R3 and capacitor C1, which absorbs the spike pulses generated by the instantaneous switching of the MOS switch; second, a Schottky diode D1, which quickly rectifies the output and introduces the energy into the input pin of the control chip U1; and third, a MOSFET Q1, which acts as the main switching unit, controlling the energy release of inductor L1 and determining the output boost effect.

[0083] The control system uses the U3500C chip, which has multiple functions such as internal PWM generation, current sampling processing, and feedback error amplification. The gate of Q1 is controlled by transistor Q2 to achieve a "clamping drive" design. Specifically, the base of Q2 samples the voltage at the front end of L1 through R18 and R19. Once the voltage rises abnormally, Q2 turns on to clamp the gate of Q1 to a low potential, thus achieving overvoltage protection. Zener diode D2 and capacitor C12 are also designed in this path for voltage regulation and spike suppression to ensure the reliability of the entire control channel.

[0084] A parallel sampling resistor R16 and R17 is set at the source of the power transistor, and then sent to the IS pin of U1 through R9 to detect the current status and build an overcurrent protection closed loop; at the same time, sampling and filtering are performed through C8 to avoid transient fluctuations from affecting control accuracy.

[0085] The output design reflects the system's "precise feedback regulation capability": the output voltage VOUT passes through a triple voltage divider network composed of R5, R6, and R12, with the middle node fed into the FB pin of U1 to achieve real-time sampling and feedback correction of the output voltage; to ensure output quality, three filter capacitors (C5, C6, and C7) are connected in parallel at the output to suppress ripple and low-frequency fluctuations; at the same time, a current-limiting branch composed of R11 and R15 is also set up to cope with abnormal loads;

[0086] The system architecture also includes a signal interface network consisting of interfaces 1 to 8, which are used for applications such as output sampling, feedback midpoint, and debugging grounding, providing system scalability and test accessibility.

[0087] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. An intelligent power compensation system, characterized in that, include: An input filtering network is provided, comprising a resistor R7. One end of the resistor R7 is connected to the input terminal VIN, and the other end of the resistor R7 is connected to three parallel capacitors, namely capacitor C2, capacitor C3, and capacitor C4. The other ends of the three parallel capacitors are all connected to ground GND, which is used to filter out the ripple and stabilize the voltage at the input terminal VIN. A boost power conversion module includes an inductor L1, one end of which is connected to the output node of the input filter network, and the other end of which is connected to a boost node N1. The boost node N1 is sequentially connected to device one, device two, and device three. Device two is a Schottky diode D1. The main power switch control network includes an N-channel MOSFET Q1, the drain of which is connected to the boost node N1. The source of the MOSFET Q1 is connected to two parallel resistors R16 and R17, both with a resistance of 0.024Ω, and they are grounded together. The gate of the MOSFET Q1 is connected to the collector of an NPN transistor Q2 through a series resistor R13 and a pull-up resistor R14. A resistor R10 and a capacitor C10 are also connected in parallel between the drain of the MOSFET Q1 and the cathode of the Schottky diode D1. Control chip U1, the control chip U1 includes the following pin connections: Pin 1 (EN) and pin 8 (VIN) are both connected to the cathode of the Schottky diode D1; Pin 7, VS, is connected to the cathode of D1; Pin 6 SW is connected to the drain of the MOSFET Q1; Pin 3 IS is connected to the source node of the MOSFET Q1 via resistor R9; A capacitor C8 is connected in parallel between pin 3 IS and ground; Pin 2, FB, is connected to the output feedback network; Pin 5 (VB) and pin 4 (GND) are both connected to ground (GND).

2. The intelligent power replenishment system according to claim 1, characterized in that: Device 1 is a parallel branch consisting of resistor R3 and capacitor C1, used for peak suppression; The anode of device 2 is connected to the output terminal of the parallel branch, and the cathode is connected in sequence to the VIN pin, EN pin and VS pin of control chip U1; Device 3 is a MOSFET Q1, whose drain is directly connected to the boost node N1, forming the main power switching path.

3. The intelligent power makeup system of claim 2, wherein, Also includes: Overvoltage clamping control module, the overvoltage clamping control module includes: Transistor Q2 has its emitter grounded and its base connected to the input terminal of inductor L1 through series resistors R18 and R19. Zener diode D2 has its cathode connected to the junction of resistors R18 and R19, and its anode grounded. The collector of transistor Q2 is connected to the gate of MOSFET Q1 to achieve overvoltage protection and clamping control of MOSFET Q1. A capacitor C12 is connected in parallel between the collector of transistor Q2 and ground to suppress driving voltage spikes.

4. The intelligent power makeup system of claim 3, wherein, Also includes: An output filtering and feedback control network, comprising: Resistor R8 is connected in series between the VIN pin of control chip U1 and the output voltage terminal VOUT; The three parallel capacitors C5, C6 and C7 form the output filter network. One common terminal of the three parallel capacitors is connected to the output voltage terminal VOUT, and the other terminal is grounded. Three-stage series resistor voltage divider: Resistors R5, R6 and R12 are connected in series and connected to the output voltage terminal VOUT. One end is grounded and the other end is connected to the FB pin of the control chip U1 to realize output voltage feedback regulation. The current limiting protection network consists of resistors R11 and R15 connected in series and connected between the output voltage terminal VOUT and ground. The output voltage terminal VOUT is also connected in parallel with a set of capacitors C9 and R4 marked NC, as well as a parallel capacitor C11, as a reserved space for filter expansion.

5. The intelligent power makeup system of claim 4, wherein, Also includes: The signal interface network includes signal test interface terminals numbered 1 to 8: Connect resistor R1 to interface 1 and resistor R2 to interface 2; Interface 3 is the output voltage terminal VOUT; Interfaces 4 and 5 are the midpoints of the voltage divider; Interfaces 6, 7, and 8 are all connected to ground (GND).

6. The intelligent power replenishment system according to claim 5, characterized in that: The IS pin of the control chip U1 is connected to the source of the MOSFET Q1 through a current-limiting resistor R9. The source of the MOSFET Q1 is grounded through parallel resistors R16 and R17. A capacitor C8 is connected in parallel between the third pin IS and ground to construct a current sampling and overcurrent feedback path, thereby enabling real-time monitoring of the current of the MOSFET Q1 in the on state.

7. The intelligent power replenishment system according to claim 6, characterized in that: The resistors R5, R6, and R12 in the output filtering and feedback control network form a multi-stage series voltage divider. The connection node between resistors R6 and R12 in the voltage divider is connected to the FB pin of the control chip U1. The output terminal of the output filtering and feedback control network is also connected in parallel with capacitors C5, C6, and C7 to stabilize the output voltage. Resistors R11 and R15 are set in the branch output to ground for current limiting protection. At the same time, parallel branch capacitors C9, R4, and C11 are reserved at the output terminal for filter structure expansion.

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