Circuit capable of rapidly turning off MOS (Metal Oxide Semiconductor) output

Abstract

The utility model belongs to the technical field of MOS driving, and discloses a circuit for rapidly turning off MOS output, which comprises an input circuit and a rapid turn-off circuit, the input circuit is used for inputting MOS driving signals, the rapid turn-off circuit comprises a resistor RDQ2, a diode DQ2, a triode QD1, a triode QD2, a resistor RDQ4, a resistor RDQ5 and a resistor RDQ6, one end of the resistor RDQ2 is connected with the input circuit, the other end of the resistor RDQ2 is connected with the diode DQ2, and the other end of the resistor RDQ2 is connected with the diode DQ2. The other end of the resistor RDQ2 is connected with a positive electrode of a diode DQ2, a negative electrode of the diode DQ2 is connected with an emitting electrode of a triode QD1, a base electrode of the triode QD1 and a collector electrode of a triode QD2 are connected and are jointly connected to one end of a resistor RDQ4, one end of the resistor RDQ4 is connected with an input circuit, and an emitting electrode of the triode QD2 is connected with a resistor RDQ6; the collector electrode of the triode QD1 and the base electrode of the triode QD2 are connected with one end of the resistor RDQ5, and the other ends of the resistor RDQ4, the resistor RDQ5 and the resistor RDQ6 are connected with the source electrode of the MOS.

Description

Technical Field

[0001] This utility model relates to the field of MOS driving technology, and in particular to a circuit for quickly turning off the MOS output. Background Technology

[0002] A fast-turn-off MOS output circuit refers to a circuit that rapidly reduces the Vgs voltage of the MOS transistor only during the MOS turn-off period, thus shortening the MOS turn-off time. When the MOS transistor is on, the drive signal acts on the MOS gate through the diode. When the MOS needs to be turned off, the voltage at the positive terminal of the diode decreases quickly, while the voltage at the negative terminal decreases relatively slowly due to the parasitic capacitance of the MOS transistor. When the voltage difference across the diode reaches a certain level, a combination circuit of devices such as a PNP transistor operates, releasing the MOS gate voltage and achieving fast MOS turn-off.

[0003] In battery management systems (BMS), MOSFETs are the most commonly used power devices. As the output power of batteries increases, the current-carrying capacity of MOSFETs also increases, leading to an increasing number of MOSFETs connected in parallel to meet the demands of high-power applications. However, individual differences in MOSFETs and the number of MOSFETs connected in parallel directly affect the BMS's turn-off time. Excessive MOSFET turn-off time can cause overload damage. This manifests as subtle differences in turn-on voltage, junction capacitance, and internal resistance. Among these, the junction capacitance is directly related to the MOSFET turn-off time. When multiple MOSFETs are connected in parallel, the overall gate-source (GS) junction capacitance is superimposed. The more MOSFETs connected in parallel, the larger the junction capacitance, and the longer the MOSFET turn-off time. This results in instability in the overall MOSFET turn-off condition, and in severe cases, overload damage. Utility Model Content

[0004] The purpose of this invention is to provide a circuit for quickly turning off the output of a MOS, which aims to minimize the difference in turn-off time between individual MOS components and shorten the overall turn-off time when multiple MOS components are connected in parallel, thereby avoiding damage to individual MOS components due to differences in their operation and ensuring successful execution of the protection turn-off output.

[0005] To achieve this objective, the present invention adopts the following technical solution:

[0006] This invention provides a circuit for quickly turning off the output of a MOS transistor, comprising an input circuit and a fast turn-off circuit. The input circuit is used to input a MOS drive signal.

[0007] The fast shutdown circuit includes resistor RDQ2, diode DQ2, transistors QD1 and QD2, resistors RDQ4, RDQ5, and RDQ6. One end of resistor RDQ2 is connected to the input circuit, and the other end of resistor RDQ2 is connected to the anode of diode DQ2. The cathode of diode DQ2 is connected to the emitter of transistor QD1. The base of transistor QD1 and the collector of transistor QD2 are connected and together connected to one end of resistor RDQ4. One end of resistor RDQ4 is connected to the input circuit. The emitter of transistor QD2 is connected to resistor RDQ6. The collector of transistor QD1 and the base of transistor QD2 are connected to one end of resistor RDQ5. The other ends of resistors RDQ4, RDQ5, and RDQ6 are all connected to the source of a MOS transistor.

[0008] Preferably, the input circuit includes a DSG drive signal input terminal and a diode DQ1. The DSG drive signal input terminal is connected to the positive terminal of the diode DQ1 and one end of the resistor RDQ4, and the negative terminal of the diode DQ1 is connected to one end of the RDQ2.

[0009] Preferably, a current-limiting resistor RDQ1 is also included, one end of which is connected to the negative terminal of the diode DQ1. The MOS drive signal is formed into the GD signal of the MOS transistor through the diode DQ1 and the current-limiting resistor RDQ1.

[0010] Preferably, the transistor QD1 is a PNP transistor.

[0011] Preferably, the transistor QD2 is an NPN transistor.

[0012] Preferably, the input voltage at the DSG drive signal input terminal is 12V.

[0013] The beneficial effects of this utility model are as follows: under the premise of multiple MOS parallel application, the difference in turn-off time of individual MOS is not large and the overall turn-off time is short, avoiding the phenomenon of individual MOS damage caused by the difference in individual MOS application, optimizing the sensitivity to the unexpected triggering of the fast turn-off circuit, having high sensitivity, fast turn-off time, and being able to adapt to BMS of more power devices with different parameter specifications. Attached Figure Description

[0014] Figure 1 This is a circuit schematic diagram of a fast MOS output shutdown provided in an embodiment of this utility model. Detailed Implementation

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not the entire structure.

[0016] In the description of this utility model, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0017] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0018] In the description of this embodiment, the terms "upper," "lower," "right," and "left," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first" and "second" are only used for distinction in description and have no special meaning.

[0019] Currently, to prevent MOS damage during turn-off, existing technologies require the addition of hardware circuitry to release the gate-gate voltage in the MOS drive circuit. Most market applications employ the following two methods:

[0020] Option 1: Add a PNP transistor to the series diode driven by the gate, with the base connected to the positive terminal of the diode, the emitter connected to the negative terminal of the diode, and the collector connected to the source of the MOS transistor.

[0021] Scheme 1 involves adding a PNP transistor to the gate-driven diode. This provides high trigger sensitivity during turn-off, low gate-source voltage after release, and a fast turn-off time, making it suitable for applications with a small number of parallel transistors. However, when a large current is output, the voltage between the MOS source and the negative terminal (B-) of the BMS battery is raised, causing a decrease in the positive voltage of the driving diode. Because of the junction capacitance at the gate-source junction, the gate voltage also increases when the source voltage is raised, as the capacitance voltage cannot change abruptly. This results in the negative diode voltage being higher than the positive voltage, potentially causing the MOS to unexpectedly turn off. Factors influencing this include current magnitude, the internal resistance of the sampling resistor, and PCB traces. Higher output current, larger sampling resistors, and longer PCB traces increase the likelihood of unexpected turn-off, leading to output disconnection even when the BMS fails to perform protection.

[0022] or;

[0023] Option 2 involves adding two PNP transistors to the series diode driven by the gate. In this case, the collectors of the two PNP transistors are connected together, the emitter of the first transistor is connected to the negative terminal of the diode, the base of the second transistor is connected to the positive terminal of the diode, and the base of the first transistor is connected to the emitter of the second transistor.

[0024] Scheme 2 incorporates two PNP transistors. This results in low trigger sensitivity during MOS turn-off, higher gate-source voltage after release, and faster turn-off time, making it suitable for scenarios with multiple parallel MOS transistors. However, when a large number of MOS transistors are connected in parallel, and often the number of parallel sampling resistors also increases, the internal resistance decreases, leading to a larger current during external short circuits. This places even greater demands on the sensitivity and release time of the fast turn-off circuit. The trigger voltage for this circuit is approximately twice that of Scheme 1, meaning its sensitivity is lower, increasing the risk.

[0025] Addressing the shortcomings of existing technologies, such as Figure 1 As shown, this utility model provides a circuit for quickly turning off the output of a MOS, including an input circuit and a fast turn-off circuit, wherein the input circuit is used to input the MOS drive signal.

[0026] The fast shutdown circuit includes resistor RDQ2, diode DQ2, transistors QD1 and QD2, resistors RDQ4, RDQ5, and RDQ6. One end of resistor RDQ2 is connected to the input circuit, and the other end of resistor RDQ2 is connected to the anode of diode DQ2. The cathode of diode DQ2 is connected to the emitter of transistor QD1. The base of transistor QD1 and the collector of transistor QD2 are connected and together connected to one end of resistor RDQ4. One end of resistor RDQ4 is connected to the input circuit. The emitter of transistor QD2 is connected to resistor RDQ6. The collector of transistor QD1 and the base of transistor QD2 are connected to one end of resistor RDQ5. The other ends of resistors RDQ4, RDQ5, and RDQ6 are all connected to the source of a MOS transistor. The fast shutdown circuit is connected to the DS connection terminal, which is a MOS source and is connected to the negative battery terminal B- of the BMS (not shown) via a sampling resistor (not shown).

[0027] Specifically, the input circuit includes a DSG drive signal input terminal and a diode DQ1. The DSG drive signal input terminal is connected to the positive terminal of the diode DQ1 and one end of the resistor RDQ4, and the negative terminal of the diode DQ1 is connected to one end of the RDQ2.

[0028] Preferably, a current-limiting resistor RDQ1 is also included, one end of which is connected to the negative terminal of the diode DQ1. The MOS drive signal is formed into the GD signal of the MOS transistor through the diode DQ1 and the current-limiting resistor RDQ1.

[0029] Preferably, the transistor QD1 is a PNP transistor.

[0030] Preferably, the transistor QD2 is an NPN transistor.

[0031] Preferably, the input voltage at the DSG drive signal input terminal is 12V. When the 12V MOS drive signal DSG (usually around 12V) passes through diode DQ1 and then through current-limiting resistor RDQ1, it forms a GD signal, which acts on the MOS drive.

[0032] Specifically, the principle of this invention is as follows:

[0033] When the BMS needs to turn off the MOS, the DSG drive signal, after being stopped by the BMS's main control chip, rapidly decreases through discharge via resistor RDQ4. Due to the junction capacitance of the MOS, the GD signal voltage decreases slowly, and since diode DQ1 has unidirectional conductivity, voltage cannot be reversed to the DSG drive signal input. When the negative voltage of diode DQ1 is higher than the positive voltage, and their voltage difference is greater than or equal to the forward voltage drop of diode DQ2 plus the voltage Vbe between the base and emitter of transistor QD1, the fast turn-off circuit starts working. Transistor QD1 turns on. At this time, the collector of transistor QD1 and the base of transistor QD2 maintain a relatively high voltage under the current limiting effect of resistor RDQ5, so transistor Q2 turns on at this time. Under the condition that transistor QD2 is turned on, the base of transistor QD1 and the collector of transistor QD2 are simultaneously carried by the high voltage through the PN junction of transistor QD1. The voltage is rapidly released and reduced through resistor RDQ4 when transistor QD2 is turned on, further maintaining the conduction of transistors QD1 and QD2, and can continuously and rapidly release the GD voltage. During this process, the reduction speed of the GD signal can be adjusted by the resistance values ​​of current-limiting resistors RDQ1, RDQ2, and RDQ6. The forward voltage drop of diode DQ2 should not be too large, as this can easily reduce the sensitivity of the fast turn-off circuit; conversely, the forward voltage drop should not be too small, as this would lead to excessively high sensitivity. Furthermore, diodes with smaller voltage drops are more expensive, which is not suitable for practical applications. Since changing the resistance value can modulate the ideal turn-off time (i.e., the smaller the resistance, the faster the turn-off speed), those skilled in the art can select and adjust the resistance values ​​of current-limiting resistors RDQ1, RDQ2, and RDQ6 according to the actual voltage magnitude. This invention does not impose any limitations on this. When the aforementioned voltage difference is less than the forward voltage drop of diode DQ2 plus the voltage Vbe between the base and emitter of transistor QD1, transistors QD1 and QD2 are turned off, and the fast turn-off operation ends. At this time, the GD signal voltage should theoretically not exceed 1V, which is much less than the MOS turn-on voltage, and the MOS is turned off.

[0034] This invention can prevent accidental shutdown of the output due to high current in the device, PCB, and battery. It is applicable to BMS for various types of PACK applications and has a wider range of operating conditions. Moreover, its shutdown speed is adjustable. The shutdown speed can be changed by changing the value of the current limiting resistor. The ideal time determined after actual verification can be used for mass production. In addition, the cost of the components is low, making it highly practical.

[0035] Obviously, the above embodiments of this utility model are merely examples for clearly illustrating the present utility model, and are not intended to limit the implementation of the present utility model. Those skilled in the art can make various obvious changes, readjustments, and substitutions without departing from the protection scope of this utility model. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the protection scope of the claims of this utility model.

Claims

1. A circuit for quickly turning off a MOS output, comprising an input circuit and a fast turn-off circuit, wherein the input circuit is used to input a MOS drive signal, characterized in that, The fast shutdown circuit includes resistor RDQ2, diode DQ2, transistors QD1 and QD2, resistors RDQ4, RDQ5, and RDQ6. One end of resistor RDQ2 is connected to the input circuit, and the other end of resistor RDQ2 is connected to the anode of diode DQ2. The cathode of diode DQ2 is connected to the emitter of transistor QD1. The base of transistor QD1 and the collector of transistor QD2 are connected and together connected to one end of resistor RDQ4. One end of resistor RDQ4 is connected to the input circuit. The emitter of transistor QD2 is connected to resistor RDQ6. The collector of transistor QD1 and the base of transistor QD2 are connected to one end of resistor RDQ5. The other ends of resistors RDQ4, RDQ5, and RDQ6 are all connected to the source of a MOS transistor.

2. The circuit for fast turn-off MOS output of claim 1, wherein, The input circuit includes a DSG drive signal input terminal and a diode DQ1. The DSG drive signal input terminal is connected to the positive terminal of the diode DQ1 and one end of the resistor RDQ4, and the negative terminal of the diode DQ1 is connected to one end of the RDQ2.

3. The circuit for quickly turning off a MOS output of claim 2, wherein, It also includes a current-limiting resistor RDQ1, one end of which is connected to the negative terminal of the diode DQ1. The MOS drive signal is formed into the GD signal of the MOS transistor through the diode DQ1 and the current-limiting resistor RDQ1.

4. The circuit for fast turn-off MOS output of claim 1, wherein, The transistor QD1 is a PNP transistor.

5. The circuit for fast turn-off MOS output of claim 1, wherein, The transistor QD2 is an NPN transistor.

6. The circuit for fast turn-off MOS output of claim 2, wherein, The input voltage at the DSG drive signal input terminal is 12V.

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