Display device and glasses-type electronic device for displaying virtual reality or augmented reality

Abstract

A display device and a glasses-type electronic device for displaying virtual reality or augmented reality are provided. The display device includes: a display panel; a pie lens for controlling a path of the display light output from the display panel; a light receiving sensor overlapping a dummy area of the display panel, the dummy area being at an outer edge of a field of view of the pie lens; a circuit substrate including a driving circuit for driving the display panel and a power circuit; and a light source configured to output near-infrared light to be recognized by the light receiving sensor.

Description

Technical Field

[0001] One or more embodiments of this disclosure relate to display devices and electronic devices. Background Technology

[0002] A wearable device is being developed that, in the form of glasses or a helmet, focuses at a short distance from the user's eyes. For example, the wearable device could be a head-mounted display (HMD) or augmented reality (AR) glasses. Such a wearable device would provide the user with AR or virtual reality (VR) visuals.

[0003] Wearable devices such as HMDs or AR glasses can appropriately use a display specification of at least approximately 2000 PPI (pixels per inch) to allow users to use the wearable device for extended periods without experiencing dizziness. For this purpose, organic light-emitting diode-on-silicon (OLEDoS) technology has emerged, associated with high-resolution, compact organic light-emitting display devices. OLEDoS technology is used to arrange organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) semiconductors are positioned.

[0004] When displaying AR or VR visuals, wearable devices track the user's eye movements and adjust the screen resolution based on these movements. For example, the wearable device detects the direction of the user's gaze and determines the corresponding central visual area and peripheral visual areas. Foveated rendering technology, used to display high-resolution images in the central visual area and low-resolution images in the peripheral visual areas, can be applied to wearable devices. The wearable device can illuminate the user's eyes with near-infrared light having an output wavelength of approximately 780 nm to approximately 1400 nm to track eye movements and can detect the near-infrared light reflected from the user's eyes. Utility Model Content

[0005] Some aspects of embodiments of this disclosure include display devices and electronic devices capable of reducing weight and size by optimizing the position of a light-receiving sensor that receives near-infrared light for eye-tracking functions.

[0006] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description.

[0007] According to some embodiments of this disclosure, the display device includes: a display panel; a disc lens for controlling the path of display light output from the display panel; a light receiving sensor overlapping a dummy area of ​​the display panel, the dummy area being at the outer edge of the field of view of the disc lens; a circuit substrate including driving circuitry and power circuitry for driving the display panel; and a light source configured to output near-infrared light to be identified by the light receiving sensor.

[0008] The display panel may include a first corner region, a second corner region, a third corner region, and a fourth corner region located at the outer edge of the field of view of the disc lens, wherein a light receiving sensor overlaps with the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0009] The light receiving sensor can be located at the top of the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0010] The light receiving sensor can be positioned between the display panel and the disc lens.

[0011] The light receiving sensor can be located at the bottom of the first corner region, the second corner region, the third corner region, and the fourth corner region, wherein the first corner region, the second corner region, the third corner region, and the fourth corner region include transparent areas, and no light-emitting element is positioned in the transparent areas.

[0012] The light receiving sensor can be placed between the display panel and the circuit substrate.

[0013] The light receiving sensor can be configured to detect near-infrared light.

[0014] The display panel may include a silicon substrate and light-emitting elements on the silicon substrate.

[0015] The driving circuit is configured to track the user's eye movement using a light receiving sensor and to control the display panel's image based on the eye movement.

[0016] The driving circuit can be included in the timing controller.

[0017] According to some embodiments of this disclosure, an eyeglass-type electronic device for displaying virtual reality or augmented reality includes: a display panel; a pie lens for controlling the path of display light output from the display panel; a light receiving sensor overlapping a dummy area of ​​the display panel, the dummy area being at the outer edge of the field of view of the pie lens; a circuit substrate including driving circuitry and power circuitry for driving the display panel; and a light source configured to output near-infrared light to be recognized by the light receiving sensor.

[0018] The display panel may include a first corner region, a second corner region, a third corner region, and a fourth corner region at the outer edge of the field of view of the disc lens, wherein the light receiving sensor overlaps with the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0019] The light receiving sensor can be located at the top of the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0020] The light receiving sensor can be positioned between the display panel and the disc lens.

[0021] The light receiving sensor can be located at the bottom of the first corner region, the second corner region, the third corner region, and the fourth corner region, wherein the first corner region, the second corner region, the third corner region, and the fourth corner region include transparent areas, and no light-emitting element is positioned in the transparent areas.

[0022] The light receiving sensor can be placed between the display panel and the circuit substrate.

[0023] The light receiving sensor can be configured to detect near-infrared light.

[0024] The display panel may include a silicon substrate and light-emitting elements on the silicon substrate.

[0025] The driving circuit is configured to track the user's eye movement using a light receiving sensor and to control the display panel's image based on the eye movement.

[0026] The driving circuit can be included in the timing controller.

[0027] The display device and electronic device according to the embodiments can reduce weight and size by optimizing the position of the light receiving sensor that receives near-infrared light for eye tracking function. Attached Figure Description

[0028] The above and other embodiments of this disclosure will become more apparent from the accompanying drawings, which describe aspects of some embodiments of this disclosure, in which:

[0029] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments;

[0030] Figure 2 This is a block diagram illustrating a display device according to one or more embodiments;

[0031] Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments;

[0032] Figure 4 This is a layout diagram illustrating an example of a display panel according to one or more embodiments;

[0033] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram of an embodiment of the display area;

[0034] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1'-I1;

[0035] Figure 8 This is a perspective view showing a head-mounted display according to one or more embodiments;

[0036] Figure 9 It is shown Figure 8 An exploded perspective view of an example of a head-mounted display;

[0037] Figure 10 This is a perspective view illustrating another example of a head-mounted display according to one or more embodiments;

[0038] Figure 11 This is a schematic diagram of the configuration of an electronic device according to one or more embodiments;

[0039] Figure 12 These are examples of images output from a display panel according to one or more embodiments;

[0040] Figure 13 This is a conceptual diagram illustrating the FoV (field of view) of a disc lens;

[0041] Figures 14 to 17 It is a layout diagram of a light receiving sensor and a display panel according to one or more embodiments; and

[0042] Figure 18 This is a schematic diagram of the configuration of an electronic device according to one or more other embodiments. Detailed Implementation

[0043] The aspects and features of the embodiments of this disclosure, as well as methods of implementing them, can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques unnecessary for a full understanding of the aspects and features of this disclosure may not have been described for those skilled in the art.

[0044] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the accompanying drawings and written description, and therefore their description will not be repeated. Furthermore, portions unrelated to the description of one or more embodiments may not be shown to make the description clearer.

[0045] In the accompanying drawings, the relative dimensions of elements, layers, and areas may be exaggerated for clarity. Furthermore, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, or attributes.

[0046] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes of the shown areas, but will include deviations in shape due to factors such as manufacturing.

[0047] For example, an injection zone shown as rectangular may have circular or curved features at its edges and / or a gradient of injection concentration, rather than a binary change from an injection zone to a non-injection zone. Similarly, the burial zone formed by injection may result in some injection within the zone between the burial zone and the surface where the injection occurs. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the zones of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways, all without departing from the scope of this disclosure.

[0048] In this detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments may be practiced without these specific details or using one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0049] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” are used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the drawings, then an element described as “below,” “below,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged “above” a second component, this means that the first component is arranged on the upper or lower side of the second component, and not limited to the upper side of the second component based on the direction of gravity.

[0050] Furthermore, in this specification, the phrase "in a plane" or "in a plan view" means the target portion viewed from above, and the phrase "in a cross section" means the cross section formed by vertically cutting the target portion viewed from the side.

[0051] It will be understood that when an element, layer, area, or component is referred to as "formed on," "on," "connected to," or "coupled to" another element, layer, area, or component, the element, layer, area, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, area, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, area, or component, such that one or more intermediary elements, layers, areas, or components may exist. For example, when a layer, area, or component is referred to as "electrically connected" or "electrically coupled" to another layer, area, or component, the layer, area, or component may be directly electrically connected or directly electrically coupled to the other layer, area, or component, or an intermediary layer, area, or component may exist. However, "direct connection / direct coupling" refers to a component being directly connected or directly coupled to another component without an intermediary component. Similarly, other expressions describing relationships between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers.

[0052] For the purposes of this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the entire column of elements before / after a column of elements, without modifying individual elements within that column. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XY, XZ, YZ, and XZ or any variations thereof). Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more related column items. For example, expressions such as “A and / or B” can include A, B, or A and B. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure”.

[0053] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Therefore, without departing from the scope of this disclosure, the first element, first component, first area, first layer, or first section described below may be referred to as a second element, second component, second area, second layer, or second section.

[0054] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that, when used in this specification, the terms “comprising,” “including,” and “having” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0056] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), “about” or “approximately” includes the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0057] When one or more embodiments can be implemented differently, the specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description.

[0058] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges with the same numerical precision contained within the stated range. For example, the range “1.0 to 10.0” is intended to include all subranges between the stated minimum value of 1.0 and the stated maximum value of 10.0, such as a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (e.g., 2.4 to 7.6). Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0059] Electronic or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed in a single integrated circuit (IC) chip or a discrete IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-on package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0060] Furthermore, the various components of these devices can be processes or threads that execute computer program instructions and interact with other system components to perform the various functions described herein, running on one or more processors in one or more computing devices. The computer program instructions are stored in memory, which can be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs or flash drives. Moreover, those skilled in the art will recognize that, without departing from the scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0061] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense.

[0062] Figure 1This is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments.

[0063] Reference Figure 1 and Figure 2 The display device 10 according to one or more embodiments is a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. Alternatively, the display device 10 according to one or more embodiments can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for implementing virtual and augmented reality.

[0064] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply circuit (power supply unit) 500.

[0065] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but this specification is not limited thereto.

[0066] like Figure 2 As shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0067] The display area DAA includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0068] Multiple pixels (PX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend on the first direction DR1 and be arranged on the second direction DR2. Multiple data lines (DL) can extend on the second direction DR2 and be arranged on the first direction DR1.

[0069] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0070] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 3 The multiple pixel transistors shown can be formed using semiconductor processes and can be positioned on a semiconductor substrate SSUB (see [reference]). Figure 7 In this context, for example, multiple pixel transistors of multiple sub-pixels SP1, SP2, and SP3 can be formed using complementary metal-oxide-semiconductor (CMOS).

[0071] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a corresponding write scan line GWL, a corresponding control scan line GCL, a corresponding bias scan line GBL, a corresponding first emission control line EL1, a corresponding second emission control line EL2, and a corresponding data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0072] The non-display area NDA includes a scan driver 610, a transmit driver 620, and a data driver 700.

[0073] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 7 In CMOS, for example, multiple scanning transistors and multiple light-emitting transistors can be formed. Although in Figure 2The diagram shows the scan driver 610 positioned to the left of the display area DAA and the transmit driver 620 positioned to the right of the display area DAA, but this specification is not limited thereto. For example, both the scan driver 610 and the transmit driver 620 may be positioned to the left or right of the display area DAA.

[0074] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing controller 400, and may output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and may output the control scan signal sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may output the bias scan signal sequentially to the bias scan line GBL.

[0075] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing controller 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and can sequentially output the first transmit control signal to a first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and can sequentially output the second transmit control signal to a second transmit control line EL2.

[0076] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 7 In, for example, multiple data transistors can be formed using CMOS.

[0077] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0078] The heat dissipation layer 200 may overlap the display panel 100 on a third-direction DR3, where the third direction is the thickness direction of the display panel 100. The heat dissipation layer 200 may be positioned on a surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity (including silver (Ag), copper (Cu), or aluminum (Al)) or graphite.

[0079] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [link to PDA1]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be positioned on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. This one end of the circuit board 300 can be a first pad portion of the circuit board 300 connected to the display panel 100 (PDA1) using conductive adhesive members. Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end.

[0080] The timing controller 400 can receive externally supplied digital video data DATA and timing signals. In response to the timing signals, the timing controller 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing controller 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing controller 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0081] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and can supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0082] Each of the timing controller 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and can be attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing controller 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0083] Alternatively, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing controller 400 and power supply circuit 500 can be located in the non-display area NDA of the display panel 100. In this case, the timing controller 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor process]). Figure 7 In, for example, multiple sequential transistors and multiple power transistors can be formed by CMOS. Each of the timing controller 400 and the power supply circuit 500 can be located in the data driver 700 and the first pad portion of PDA1 (see...). Figure 4 )between.

[0084] Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments.

[0085] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first drive voltage VSS corresponding to a low potential voltage (see...). Figure 2 The first driving voltage line VSL applied, and the second driving voltage VDD corresponding to the high potential voltage (see...) Figure 2The second drive voltage line VDL applied, and the third drive voltage VINT corresponding to the initialization voltage (see...). Figure 2 The third driving voltage line VIL is applied. That is, the first driving voltage line VSL can be a low-potential voltage line, the second driving voltage line VDL can be a high-potential voltage line, and the third driving voltage line VIL can be the initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0086] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0087] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be positioned between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer positioned between the first electrode and the second electrode, but this specification is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0088] The first transistor T1 may be a driving transistor that controls the source-drain current (also referred to herein as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0089] A second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0090] The third transistor T3 can be positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. For this purpose, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0091] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0092] The fifth transistor T5 can be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0093] A sixth transistor T6 can be positioned between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal on the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD on the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0094] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0095] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0096] The first node N1 is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0097] Each of the first transistors T1 through T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 through T6 can be a P-type MOSFET, but this specification is not limited thereto. Each of the first transistors T1 through T6 can be an N-type MOSFET. Alternatively, some of the first transistors T1 through T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0098] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0099] In addition, the second sub-pixel SP2 (see Figure 2 The equivalent circuit diagram of ) and the third sub-pixel SP3 (see Figure 2 The equivalent circuit diagram of ) can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 is omitted in this specification.

[0100] Figure 4 This is a layout diagram illustrating an example of a display panel according to one or more embodiments.

[0101] Reference Figure 4The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0102] The scan driver 610 can be positioned on a first side of the display area DAA, and the transmit driver 620 can be positioned on a second side of the display area DAA. For example, the scan driver 610 can be positioned on one side of the display area DAA in a first direction DR1, and the transmit driver 620 can be positioned on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be positioned on the left side of the display area DAA, and the transmit driver 620 can be positioned on the right side of the display area DAA. However, this specification is not limited to this, and both the scan driver 610 and the transmit driver 620 can be positioned on either the first or second side of the display area DAA.

[0103] The first pad portion of PDA1 may include a connection to circuit board 300 via a conductive adhesive component (see...). Figure 1 Multiple first pads PD1 of pads or bumps. The first pad portion PDA1 can be positioned on the third side of the display area DAA. For example, the first pad portion PDA1 can be positioned on one side of the display area DAA in the second direction DR2.

[0104] The first pad portion of PDA1 can be positioned on the outside of the data driver 700 in the second direction DR2. That is, the first pad portion of PDA1 can be positioned closer to the edge of the display panel 100 than the data driver 700.

[0105] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0106] The first distribution circuit 710 distributes the data voltage applied through the first pad portion of PDA1 to multiple data lines DL (see...). Figure 2For example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be positioned on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be positioned on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can (e.g., in a plan view) be positioned on the lower side of the display area DAA.

[0107] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be positioned on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be positioned on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be positioned above the display area DAA.

[0108] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram of an embodiment of the display area.

[0109] Reference Figure 5 and Figure 6 Each of the multiple pixels PX includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0110] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in the plan view.

[0111] The maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1 can be substantially the same.

[0112] The maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0113] like Figure 5 and Figure 6 As shown, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape formed by six straight lines in the plan view, but this specification is not limited to this. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than hexagonal shapes in the plan view.

[0114] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0115] Alternatively, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 can be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction that is substantially perpendicular to the first diagonal direction DD1.

[0116] The first emission region EA1 can emit a first light, the second emission region EA2 can emit a second light, and the third emission region EA3 can emit a third light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band. For example, the blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0117] exist Figure 5 and Figure 6 The illustration shows that each of the plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but this specification is not limited thereto. That is, each of the plurality of pixels PX may include four emission regions.

[0118] Furthermore, the layout of the emission regions of multiple pixel PXs is not limited to Figure 5 and Figure 6 The layout shown is illustrated. For example, the emission regions of multiple pixels PX can be positioned as a strip structure in which the emission regions are arranged in a first direction DR1, or as a diamond-shaped arrangement. structure( (It is a registered trademark of Samsung Display Co., Ltd. of South Korea), or a emitting area that has a hexagonal shape in a plan view, such as Figure 6 The hexagonal structures arranged side by side are shown in the image.

[0119] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1'-I1.

[0120] Reference Figure 7 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an organic layer (APL), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0121] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating layers (SINS1 to SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be referenced... Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0122] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0123] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0124] The lower insulating layer (BINS) can be positioned between the gate electrode GE and the well region WA. The side insulating layer (SINS) can be positioned on the side surface of the gate electrode GE. The side insulating layer (SINS) can also be positioned on top of the lower insulating layer (BINS).

[0125] Each of the source region SA and drain region DA can be a region doped with type II impurities. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0126] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, the length of the channel region CH of each of the multiple pixel transistors PTR can be increased, thereby reducing or preventing the possibility of breakdown (or punch-through) and hot carrier phenomena that may be caused by short channels.

[0127] The first semiconductor insulating layer SINS1 can be positioned on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2) based materials. x The inorganic layer is formed, but this specification is not limited to this.

[0128] The second semiconductor insulating layer SINS2 can be positioned on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this specification is not limited to this.

[0129] Multiple contact terminals (CTEs) can be positioned on the second semiconductor insulating layer (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each of the multiple pixel transistors (PTRs) through holes penetrating the first semiconductor insulating layer (SINS1) and the second semiconductor insulating layer (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them.

[0130] The third semiconductor insulating layer, SINS3, can be positioned on the side surface of each of the plurality of contact terminals, CTEs. The top surface of each of the plurality of contact terminals, CTEs, can be exposed and not covered by the third semiconductor insulating layer, SINS3. The third semiconductor insulating layer, SINS3, can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this specification is not limited to this.

[0131] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate (such as a polyimide substrate). In this case, the thin-film transistor (e.g., a pixel transistor PTR) can be positioned within the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0132] The backplane (EBP) of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating layers INS1 to INS9. Additionally, the backplane (EBP) includes first conductive layers ML1 to eighth conductive layers ML8 located between the insulating layers INS1 to INS9.

[0133] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry for the first sub-pixel SP1 shown. For example, combined with... Figure 3The first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection between the first transistor T1 to the sixth transistor T6, the first capacitor CP1, and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0134] A first insulating layer INS1 may be positioned on the semiconductor backplane SBP. Each of a plurality of first vias VA1 may penetrate the first insulating layer INS1 to connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of a plurality of first conductive layers ML1 may be positioned on the first insulating layer INS1 and may connect to the first vias VA1.

[0135] A second insulating layer INS2 may be positioned on the first insulating layer INS1 and the first conductive layer ML1. Each of the plurality of second vias VA2 may penetrate the second insulating layer INS2 and may be connected to the exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 may be positioned on the second insulating layer INS2 and may be connected to the second via VA2.

[0136] A third insulating layer INS3 may be positioned on the second insulating layer INS2 and the second conductive layer ML2. Each of the plurality of third vias VA3 may penetrate the third insulating layer INS3 and may be connected to the exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 may be positioned on the third insulating layer INS3 and may be connected to the third via VA3.

[0137] A fourth insulating layer INS4 can be positioned on the third insulating layer INS3 and the third conductive layer ML3. Each of the plurality of fourth vias VA4 can penetrate the fourth insulating layer INS4 and can be connected to the exposed third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 can be positioned on the fourth insulating layer INS4 and can be connected to the fourth via VA4.

[0138] A fifth insulating layer INS5 may be positioned on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the plurality of fifth vias VA5 may penetrate the fifth insulating layer INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 may be positioned on the fifth insulating layer INS5 and may be connected to the fifth via VA5.

[0139] A sixth insulating layer INS6 can be positioned on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the plurality of sixth vias VA6 can penetrate the sixth insulating layer INS6 and can be connected to the exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 can be positioned on the sixth insulating layer INS6 and can be connected to the sixth via VA6.

[0140] A seventh insulating layer INS7 can be positioned on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the plurality of seventh vias VA7 can penetrate the seventh insulating layer INS7 and can be connected to the exposed sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 can be positioned on the seventh insulating layer INS7 and can be connected to the seventh via VA7.

[0141] The eighth insulating layer INS8 can be positioned on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the plurality of eighth vias VA8 can penetrate the eighth insulating layer INS8 and can be connected to the exposed seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 can be positioned on the eighth insulating layer INS8 and can be connected to the eighth via VA8.

[0142] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first insulating layers INS1 to INS8 can be made of substantially the same material. The first insulating layers INS1 to INS8 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this specification is not limited to this.

[0143] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately [missing information - likely a value]. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately [missing information]. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately [missing information].

[0144] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately [missing information]. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately [missing information].

[0145] The ninth insulating layer INS9 can be positioned on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this specification is not limited to this.

[0146] Each of the plurality of ninth vias VA9 can penetrate the ninth insulating layer INS9 and can connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the ninth via VA9 can be approximately [missing information].

[0147] The display element layer (EML) can be positioned on the light-emitting element backplane (EBP). The EML may include a light-emitting element (LE) comprising a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT), a reflective electrode layer (RL), a tenth insulating layer (INS10), an eleventh insulating layer (INS11), and a tenth via (VA10). The EML may also include a pixel-defining layer (PDL) and multiple trenches (TRC).

[0148] The reflective electrode layer RL can be positioned on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as... Figure 7 As shown, the reflective electrode layer RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0149] Each of the plurality of first reflective electrodes RL1 may be positioned on the ninth insulating layer INS9 and may be connected to the ninth via VA9. The first reflective electrodes RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride comprising any one of them. For example, the first reflective electrode RL1 may comprise titanium nitride (TiN).

[0150] Each of the plurality of second reflective electrodes RL2 may be positioned on a corresponding first reflective electrode RL1. The second reflective electrodes RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of these. For example, the second reflective electrode RL2 may comprise aluminum (Al).

[0151] Each of the plurality of third reflective electrodes RL3 may be positioned on a corresponding one of the second reflective electrodes RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride comprising any of these. For example, the third reflective electrode RL3 may comprise titanium nitride (TiN).

[0152] The fourth reflective electrode RL4 can be positioned on the third reflective electrode RL3. The fourth reflective electrode RL4 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0153] Because the second reflective electrode RL2 is essentially the electrode that reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately [missing information]. And the thickness of the second reflective electrode RL2 can be approximately [missing information].

[0154] The tenth insulating layer INS10 can be positioned on the ninth insulating layer INS9. The tenth insulating layer INS10 can be positioned between horizontally adjacent reflective electrode layers RL. The tenth insulating layer INS10 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this specification is not limited to this.

[0155] The eleventh insulating layer INS11 can be positioned on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 can be made of silicon oxide (SiO2). x An inorganic layer is formed, but this specification is not limited thereto. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light emitted from the light-emitting element LE is reflected by the reflective electrode layer RL.

[0156] To adjust the resonant distance of light emitted from the light-emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating layer INS10 or the eleventh insulating layer INS11 below the first electrode AND can be omitted. For example, in one or more embodiments, the first electrode AND of the first sub-pixel SP1 can be directly positioned on the reflective electrode layer RL. The eleventh insulating layer INS11 can be positioned below the first electrode AND of the second sub-pixel SP2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be positioned below the first electrode AND of the third sub-pixel SP3.

[0157] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2, and greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. However, the specification of this disclosure is not limited thereto.

[0158] Additionally, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in this specification, a twelfth insulating layer (not shown) may be attached and positioned below the first electrode AND of the first sub-pixel SP1. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer (not shown) may be positioned below the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer (not shown) may be positioned below the first electrode AND of the third sub-pixel SP3.

[0159] Each of the multiple tenth vias VA10 can penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second sub-pixel SP2 and the third sub-pixel SP3, and can be connected to the exposed fourth reflective electrode RL4. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0160] The first electrode AND of each of the plurality of light-emitting elements LE can be positioned on the eleventh insulating layer INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride comprising any one of them. For example, the first electrode AND of each of the plurality of light-emitting elements LE can be titanium nitride (TiN).

[0161] A pixel-defining layer (PDL) can be positioned on a portion of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL can be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0162] The first emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0163] The pixel definition layer (PDL) may include a first pixel definition layer (PDL1), a second pixel definition layer (PDL2), and a third pixel definition layer (PDL3). The first pixel definition layer (PDL1) may be positioned on the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs), the second pixel definition layer (PDL2) may be positioned on the first pixel definition layer (PDL1), and the third pixel definition layer (PDL3) may be positioned on the second pixel definition layer (PDL2). The first pixel definition layer (PDL1), the second pixel definition layer (PDL2), and the third pixel definition layer (PDL3) may be made of silicon oxide (SiO2). x An inorganic layer is formed, but this specification is not limited thereto. The first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 may each have approximately The thickness.

[0164] When the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 form a single pixel-defining layer, the height of this single pixel-defining layer increases, making it possible for the first encapsulation inorganic layer TFE1 to be cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film is to be cut on the inclined portion.

[0165] Therefore, to reduce or prevent the possibility of the first encapsulated inorganic layer TFE1 being cut off due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can have a cross-sectional structure with a step portion. For example, the width of the first pixel defining layer PDL1 can be greater than the width of the second pixel defining layer PDL2, and also greater than the width of the third pixel defining layer PDL3. The width of the second pixel defining layer PDL2 can be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the width in the first direction DR1 (see...). Figure 5 ) and / or second direction DR2 (see Figure 5 The horizontal length of the first pixel-defined layer PDL1 is defined above.

[0166] Each of the plurality of trench TRCs can penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. Furthermore, each of the plurality of trench TRCs can penetrate the eleventh insulating layer INS11. The tenth insulating layer INS10 can be partially recessed at each of the plurality of trench TRCs.

[0167] At least one trench TRC can be located between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7Two trench TRCs are shown positioned between adjacent sub-pixels SP1, SP2, and SP3, but this specification is not limited thereto.

[0168] The light-emitting stack (IL) can include multiple intermediate layers. Figure 7 The illustration shows a light-emitting stack IL having a three-tandem structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this specification is not limited thereto. For example, the light-emitting stack IL may have a double-tandem structure comprising two intermediate layers.

[0169] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different types of light. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first type of light, a second stacked layer IL2 that emits a third type of light, and a third stacked layer IL3 that emits a second type of light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0170] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting a first light, and a first electron transport layer are stacked in sequence. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting a third light, and a second electron transport layer are stacked in sequence. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting a second light, and a third electron transport layer are stacked in sequence.

[0171] A first charge-generating layer for supplying holes to the second stacked layer IL2 and for supplying electrons to the first stacked layer IL1 may be positioned between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type charge-generating layer that supplies holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0172] A second charge generation layer for supplying holes to the third stacked layer IL3 and for supplying electrons to the second stacked layer IL2 may be located between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0173] The first stacked layer IL1 can be positioned on the first electrode AND and the pixel defining layer PDL, and can be positioned on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. The second stacked layer IL2 can be positioned on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity or empty space ESS can be positioned between portions of the first stacked layer IL1 and portions of the second stacked layer IL2. The third stacked layer IL3 can be positioned on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can cover the second stacked layer IL2 in each of the plurality of trench TRCs. That is, in the three-in-series structure, each of the plurality of trench TRCs can be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the dual-series structure, each of the multiple trench TRCs can be a structure used to cut off the charge generation layer and the lower intermediate layer located between the lower intermediate layer and the upper intermediate layer.

[0174] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To cut the first stacked layer IL1, the second stacked layer IL2, and / or the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, an alternative structure can exist to replace the trench TRCs. For example, instead of trench TRCs, inverted conical partition walls can be positioned in the pixel defining layer PDL.

[0175] The number of stacked layers IL1, IL2, and IL3 emitting different colors of light is not limited to Figure 7 The quantities shown are as described. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be positioned between the two intermediate layers.

[0176] in addition, Figure 7The diagram shows that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all located within the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively; however, this specification is not limited to this. For example, the first stacked layer IL1 may be located within the first emission region EA1, but may not be located within the second emission region EA2 and the third emission region EA3. Similarly, the second stacked layer IL2 may be located within the second emission region EA2, but may not be located within the first emission region EA1 and the third emission region EA3. Furthermore, the third stacked layer IL3 may be located within the third emission region EA3, but may not be located within the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL can be omitted.

[0177] The second electrode CAT can be positioned on the third stacked layer IL3. The second electrode CAT can be positioned on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity effect.

[0178] The encapsulation layer TFE can be positioned on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0179] The first encapsulation inorganic layer TFE1 can be positioned on the second electrode CAT. The first encapsulation inorganic layer TFE1 can be formed in which silicon nitride (SiN) is selected. x ) layer, silicon oxynitride (SiO) x N y ) layer and silicon dioxide (SiO) x A multilayer structure consisting of one or more inorganic layers stacked alternately. The first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0180] The second encapsulation inorganic layer TFE2 can be positioned on top of the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO xThe second encapsulation inorganic layer TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0181] The organic layer APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL can be an organic layer comprising materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0182] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be positioned on the organic layer APL.

[0183] The first color filter CF1 may overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 may transmit first light (e.g., light in the blue wavelength band). The blue wavelength band may be from approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit the first light emitted from the first emission region EA1.

[0184] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit second light (e.g., light in the green wavelength band). The green wavelength band can be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit the second light emitted from the second emission region EA2.

[0185] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit third light (e.g., light in the red wavelength band). The red wavelength band can be approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 can transmit third light from the light emitted from the third emission region EA3.

[0186] Lenses LNS can be positioned on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS can be used to add a directional display device 10 (see...). Figure 1 The structure of the ratio of light in front of the lens. Each of the multiple lenses LNS can have a cross-sectional shape that is convex in the upward direction.

[0187] A filler layer (FIL) can be positioned on multiple lens elements (LNS). The filler layer (FIL) can have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens elements (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic layer comprising materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0188] A cover layer CVL can be positioned on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin substrate. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin substrate, it can be directly applied to the filler layer FIL.

[0189] The polarizer POL can be positioned on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this specification is not limited thereto. However, the polarizer POL can be omitted when the first color filter CF1, the second color filter CF2, and the third color filter CF3 sufficiently overcome the visibility degradation caused by reflection of external light.

[0190] Figure 8 This is a perspective view showing a head-mounted display according to one or more embodiments. Figure 9 It is shown Figure 8 An exploded perspective view of an example of a head-mounted display.

[0191] Reference Figure 8 and Figure 9 A head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0192] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2The display devices 10 described are essentially the same, so the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0193] The first optical component 1510 may be positioned between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be positioned between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0194] The intermediate frame 1400 can be positioned between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0195] The control circuit board 1600 can be positioned between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data (see...). Figure 2 It can transmit digital video data DATA to the first display device 10_1 and the second display device 10_2 via a connector.

[0196] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0197] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. A housing cover 1200 covers an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown positioned separately, but this specification is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0198] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0199] A headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned on the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, such as... Figure 10 As shown, the head-mounted display 1000 may be provided with eyeglass frames instead of the headband 1300.

[0200] Additionally, the head-mounted display 1000 may include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0201] Figure 10 This is a perspective view illustrating another example of a head-mounted display according to one or more embodiments.

[0202] Reference Figure 10 The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path changing component 1070, and a display device housing 1200_1.

[0203] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0204] Figure 10 The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but this specification is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in this case, the image displayed on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0205] Figure 11 This is a schematic diagram illustrating the configuration of an electronic device according to one or more embodiments. For example, Figure 11 The electronic device shown may be a glasses-type electronic device that displays virtual reality or augmented reality. Figure 11 The electronic device shown may include reference Figures 1 to 7 The described display device 10.

[0206] According to one or more embodiments, the electronic device for displaying virtual reality or augmented reality may be a display device 1700, and may include a display panel 1710, a light receiving sensor 1750 overlapping a dummy area of ​​the display panel 1710, a circuit substrate 1720 including driving circuitry and power circuitry for driving the display panel 1710, a disc lens (e.g., a disc lens unit) 1760 for controlling the path of the display light output from the display panel 1710, and a light source (e.g., a light source module) 1740 for outputting near-infrared light identified by the light receiving sensor 1750.

[0207] Display panel 1710 can be used as a reference. Figures 1 to 7 The described display panel 100. According to one or more embodiments, a circuit substrate 1720 may include driving circuitry and power circuitry for driving the display panel 1710, and may be positioned on the rear surface of the display panel 1710. The circuit substrate 1720 may be a reference... Figure 1 The circuit board 300 is described.

[0208] According to one or more embodiments, the drive circuitry located in the circuit substrate 1720 may be included in the reference... Figure 2 The timing controller 400 is described below. Such a drive circuit can control the display panel 1710, the light receiving sensor 1750, and the light source 1740. For example, the operation of the display panel 1710, the light receiving sensor 1750, and the light source 1740, as described below, can be controlled by the timing controller 400 (see [link to relevant documentation]). Figure 2 ) to execute.

[0209] Display panel 1710 can emit display light for displaying augmented reality (or virtual reality) images. For example, the display light emitted from display panel 1710 is directed to pie lens 1760. User 1770 can view objects in the augmented reality (or virtual reality) image by viewing the light directed by pie lens 1760.

[0210] Display device 1700 uses near-infrared light to detect eye movements of user 1770 and determine the direction of user 1770's gaze. Display device 1700 determines a central visual area corresponding to user 1770's gaze and also determines peripheral visual areas in addition to the central visual area. Display device 1700 adjusts the image displayed by display panel 1710 based on the tracked eye movements of user 1770.

[0211] The display device 1700 can be used with a foveated rendering technique that displays a high-resolution image in the central visual area and a low-resolution image in the peripheral visual area.

[0212] Display device 1700 may include a light source 1740 that emits near-infrared light to detect the gaze (i.e., eye movement) of user 1770, and may also include a light receiving sensor 1750 that detects the near-infrared light. Display device 1700 uses light source 1740 to emit near-infrared light. As indicated by arrow 1781, the near-infrared light emitted from light source 1740 is reflected from the eye of user 1770. The near-infrared light reflected from the eye of user 1770 is input to light receiving sensor 1750 via pie lens 1760.

[0213] The light receiving sensor 1750 can track the eye of the user 1770 by detecting input near-infrared light (e.g., reflected light) and generating an electrical signal corresponding to the input near-infrared light. For example, the light receiving sensor 1750 can be an optical sensor that optically identifies biometric information. The light receiving sensor 1750 may include a photodiode, but embodiments are not limited to the form of the light receiving sensor 1750.

[0214] According to one or more embodiments, the near-infrared light used to track the eye movement of user 1770 is light with an output wavelength of approximately 780 nm to approximately 1400 nm, and the light receiving sensor 1750 may be a sensor configured to identify the light.

[0215] Display device 1700 can convert reflected light detected by light receiving sensor 1750 into an electrical signal. Display device 1700 can obtain an eye image of user 1770 through the converted electrical signal. Display device 1700 can use the obtained eye image of user 1770 to track the gaze movement of user 1770.

[0216] According to one or more embodiments, a light receiving sensor 1750 may be positioned on the upper part of a display panel 1710 and may overlap with a dummy area of ​​the display panel 1710. The dummy area of ​​the display panel 1710 is positioned within the field of view (FoV) 2001 of the disc lens 1760 (see [link to documentation]). Figure 14 (Exterior. See below for details.) Figures 12 to 17 Describe in detail the dummy area located by the optical receiving sensor 1750.

[0217] The disc lens 1760 can be combined with the front surface of the display panel 1710. The display device 1700 can combine the disc lens 1760 on the display panel 1710 to make the image clearer and increase the resolution.

[0218] A disc lens 1760 is an optical device that selectively transmits and reflects light to change the direction of light travel by using a linear polarizer, a semi-reflective mirror, a reflective polarizer, or a retardation film. For example, a disc lens 1760 is a polarization-based optical system that increases the optical path by using the polarization properties of light.

[0219] According to one or more embodiments, the disc lens 1760 may include three or more lenses 1730, two quarter-wave plates (QWP), a half-reflective mirror, a reflective polarizer, and one or more absorptive polarizers.

[0220] Figure 12 These are examples of images output from a display panel according to one or more embodiments. Figure 13 This is a conceptual diagram illustrating the FoV (field of view) of a disc lens.

[0221] Reference Figure 11 , Figure 12 and Figure 13 The display panel 1710 can emit display light for displaying augmented reality (or virtual reality) images. However, when the display light emitted from the display panel 1710 passes through the disc lens 1760, it forms an effect similar to... Figure 13 The field of view (FoV) is shown in the figure.

[0222] Assume that display panel 1710 emits display light to display things such as... Figure 12 In the augmented reality image (or virtual reality image) 1800, the user 1770 may only see the field of view (FoV) 2001 positioned at the pie lens 1760 (see...). Figure 14 Some of the display lights within the ) (such as Figure 13 Augmented reality images (or virtual reality images) in 1900).

[0223] The portion of the display panel 1710 corresponding to the outer edge of the field of view (FoV) 2001 of the disc lens 1760 is a dummy area in which light emitted to the user 1770 is invisible to the user 1770 even when display light is emitted (e.g., invisible area 2012 (see [link]). Figures 14 to 17 For example, such as Figure 13 As shown by the dashed line 1901, the invisible area 2012 can be located at each corner of the display panel 1710, and the display light emitted from the invisible area 2012 of the display panel 1710 may not be visible to the user.

[0224] Figures 14 to 17 It is a layout diagram of a light receiving sensor and a display panel according to one or more embodiments.

[0225] Reference Figures 14 to 17 Display device 1700 (see Figure 11 It includes a light receiving sensor 1750 to overlap with an invisible region (e.g., a dummy region) 2012 of the display panel 1710 corresponding to the outer edge of the field of view (FoV) 2001 of the pie lens 1760.

[0226] The display panel 1710 can be divided into a visible area 2011 corresponding to the interior of the field of view (FoV) 2001 of the disc lens 1760 and an invisible area 2012 corresponding to the exterior of the field of view (FoV) 2001 of the disc lens 1760. When viewed on a flat surface, the field of view (FoV) 2001 of the disc lens 1760 has a circular shape. Therefore, the boundary of the visible area 2011 of the display panel 1710 can have a circular shape.

[0227] The invisible area 2012 of the display panel 1710 may be an area that is not visible to the user 1770 even when display light is emitted and is located outside the circular visible area 2011, and may be defined as a dummy area. The invisible area 2012 of the display panel 1710 (e.g., a dummy area) may include the four corner areas of the display panel 1710. For example, the invisible area 2012 of the display panel 1710 may include a first corner area, a second corner area, a third corner area, and a fourth corner area.

[0228] According to one or more embodiments, the light receiving sensor 1750 may overlap with at least one of the first corner region, the second corner region, the third corner region, and the fourth corner region. Since the light receiving sensor 1750 is positioned at the outer edge of the field of view (FoV) 2001 of the disc lens 1760, it will not cause interference from the display light emitted from the display panel 1710. Furthermore, because the position of the light receiving sensor 1750 is optimized, the weight and volume of the display device 1700 can be reduced.

[0229] According to one or more embodiments, such as Figure 14 As shown, the light receiving sensor 1750 can be positioned in each of the four corner regions of the display panel 1710. The light receiving sensor 1750 overlaps with each of the first, second, third, and fourth corner regions of the display panel 1710. The display device 1700 may include four light receiving sensors 1750, and the four light receiving sensors 1750 may be positioned on top of the first, second, third, and fourth corner regions, respectively.

[0230] According to one or more embodiments, such as Figure 15 As shown, the light receiving sensor 1750 may include three light receiving sensors 1750, and the three light receiving sensors 1750 may overlap with three corner regions selected from the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0231] According to one or more embodiments, such as Figure 16 As shown, the light receiving sensor 1750 may include two light receiving sensors 1750, and the two light receiving sensors 1750 may overlap with two corner regions selected from the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0232] According to one or more embodiments, such as Figure 17 As shown, the light receiving sensor 1750 may include a light receiving sensor 1750, and the light receiving sensor 1750 may overlap with a corner region selected from the first corner region, the second corner region, the third corner region and the fourth corner region.

[0233] Figure 18 This is a schematic diagram of the configuration of an electronic device according to one or more other embodiments.

[0234] Corresponding to Figure 18 One or more embodiments corresponding to Figure 11The difference in one or more embodiments is that the light receiving sensor 1750 is positioned on the rear surface of the display panel 1710. In embodiments, the light receiving sensor 1750 may be positioned at the bottom of the first corner region, the second corner region, the third corner region, and the fourth corner region.

[0235] Reference Figure 18 In the display device 1700, the light receiving sensor 1750 and the display panel 1710 correspond to the field of view (FoV) 2001 of the disc lens 1760 (see [link]). Figure 14 The dummy area of ​​the outer edge of the light receiving sensor overlaps with that of the display panel 1710, and the light receiving sensor 1750 is positioned on the rear surface of the display panel 1710. For example, the light receiving sensor 1750 is positioned between the display panel 1710 and the circuit substrate 1720.

[0236] According to one or more embodiments, since the light receiving sensor 1750 is positioned on the rear surface of the display panel 1710, the light receiving sensor 1750 detects near-infrared light passing through the display panel 1710. For this purpose, an invisible area 2012 of the display panel 1710 overlapping with the light receiving sensor 1750 (see...) Figure 14 (For example, dummy regions such as the first corner region, the second corner region, the third corner region, and / or the fourth corner region) can be designed as regions that can transmit light.

[0237] According to one or more embodiments, each of the first corner region, second corner region, third corner region, and fourth corner region of the invisible region 2012 of the display panel 1710 includes a non-positioned light-emitting element LE (see...). Figure 3 The transparent areas of ). For example, the conductive layers ML1 to ML8 of the transparent material in each of the first corner area, second corner area, third corner area and fourth corner area of ​​the invisible area 2012 can be omitted (see Figure 7 ) and display element layer EML (see Figure 7 For example, each of the first, second, third, and fourth corner regions of the invisible region 2012 may have a transmittance (e.g., a predetermined transmittance) (e.g., approximately 80% or greater transmittance), but this disclosure is not limited thereto.

[0238] However, it should be understood that the aspects and features of the embodiments of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains by referring to the claims, to which their equivalents will be included.

Claims

1. A display device, characterized in that, The display device includes: Display panel; A disc-shaped lens is used to control the path of the display light output from the display panel; A light receiving sensor overlaps with a dummy area of ​​the display panel, the dummy area being located at the outer edge of the field of view of the disc lens; A circuit substrate, including driving circuitry and power circuitry for driving the display panel; and The light source is configured to output near-infrared light that will be recognized by the light receiving sensor.

2. The display device according to claim 1, characterized in that, The display panel includes a first corner region, a second corner region, a third corner region, and a fourth corner region positioned at the outer edge of the field of view of the disc lens, and The light receiving sensor overlaps with the first corner region, the second corner region, the third corner region, and the fourth corner region.

3. The display device according to claim 2, characterized in that, The light receiving sensor is located at the top of the first corner region, the second corner region, the third corner region, and the fourth corner region.

4. The display device according to claim 3, characterized in that, The light receiving sensor is located between the display panel and the disc lens.

5. The display device according to claim 2, characterized in that, The light receiving sensor is located at the bottom of the first corner region, the second corner region, the third corner region, and the fourth corner region, and The first corner region, the second corner region, the third corner region, and the fourth corner region include transparent regions, and no light-emitting elements are positioned in the transparent regions.

6. The display device according to claim 5, characterized in that, The light receiving sensor is located between the display panel and the circuit substrate.

7. The display device according to claim 6, characterized in that, The light receiving sensor is configured to detect the near-infrared light.

8. The display device according to claim 1, characterized in that, The display panel includes a silicon substrate and light-emitting elements on the silicon substrate.

9. The display device according to claim 1, characterized in that, The driving circuit is configured to track the user's eye movement using the light receiving sensor, and is configured to control the image on the display panel based on the eye movement.

10. A glasses-type electronic device for displaying virtual reality or augmented reality, characterized in that, The eyeglass-type electronic device includes: Display panel; A disc-shaped lens is used to control the path of the display light output from the display panel; A light receiving sensor overlaps with a dummy area of ​​the display panel, the dummy area being located at the outer edge of the field of view of the disc lens; A circuit substrate, including driving circuitry and power circuitry for driving the display panel; and The light source is configured to output near-infrared light that will be recognized by the light receiving sensor.

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