On-off state detection circuit of magnetic latching relay

Abstract

The utility model discloses an on-off state detection circuit of a magnetic latching relay, which can avoid interference of an external superimposed magnetic field and is reliable and stable in detection result. The magnetic latching relay on-off state detection circuit comprises a first all-pole Hall effect chip, a second all-pole Hall effect chip, a power supply and an MCU. Power supply pins of the first all-pole Hall effect chip and the second all-pole Hall effect chip are respectively connected with a power supply, output pins of the first all-pole Hall effect chip and the second all-pole Hall effect chip are respectively connected with the MCU, and grounding pins of the first all-pole Hall effect chip and the second all-pole Hall effect chip are grounded; wherein the installation position of the first all-pole Hall effect chip is close to a permanent magnet in the magnetic latching relay to be detected and is tightly attached to the magnetic latching relay to be detected, and the installation position of the second all-pole Hall effect chip is far away from the permanent magnet and is tightly attached to the magnetic latching relay to be detected, so that the second all-pole Hall effect chip cannot detect a magnetic field generated by the permanent magnet.

Description

Technical Field

[0001] This utility model relates to the field of electrical control technology, specifically to a magnetic latching relay switch status detection circuit. Background Technology

[0002] In the field of electrical control, Hall effect detection has long been used as a non-contact detection method for online monitoring of the contact status of magnetic latching relays. Its technical principle is based on the magnetic field strength characteristics generated by the internal permanent magnet when the latching relay is closed. When the Hall sensor detects a value exceeding a preset threshold (e.g., the default value is >30mT for closed), the magnetic latching relay is determined to be in a closed state; otherwise, it is determined to be in an open state.

[0003] Traditional Hall effect detection schemes rely solely on a single-point magnetic field strength threshold for judgment. When interference sources such as motors, transformers, and wireless charging devices are present in the environment, the superimposed magnetic field can cause the detected value to exceed the threshold, leading to misjudgments of the on / off state of the magnetic latching relay contacts, such as being actually open but being identified as closed. Furthermore, traditional Hall effect detection schemes determine the state of the magnetic latching relay contacts only through the single dimension of magnetic field strength, and cannot distinguish the difference between the direction of the internal magnetic field of the relay and external interference (e.g., when the relay is closed, the internal magnetic field is N→S, while external interference may be S→N). Utility Model Content

[0004] The purpose of this invention is to overcome the defects in the existing technology and provide a magnetic latching relay switch state detection circuit that can avoid interference from external superimposed magnetic fields and provide reliable and stable detection results.

[0005] To achieve the above objectives, the technical solution of this utility model is to design a magnetic latching relay switch state detection circuit, which includes:

[0006] First omnipolar Hall effect chip, second omnipolar Hall effect chip, power supply and MCU;

[0007] The power supply pins of the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are respectively connected to the power supply, the output pins of the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are respectively connected to the MCU, and the ground pins of the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are both grounded;

[0008] The first omnipolar Hall effect chip is mounted close to and in close contact with the permanent magnet in the magnetic latching relay under test, while the second omnipolar Hall effect chip is mounted far from the permanent magnet and in close contact with the magnetic latching relay under test, so that the second omnipolar Hall effect chip cannot detect the magnetic field generated by the permanent magnet.

[0009] The MCU is used to determine the switching state of the magnetic latching relay under test based on the signals output by the first omnipolar Hall effect chip and the second omnipolar Hall effect chip.

[0010] Furthermore, the magnetic latching relay switch state detection circuit also includes a first pull-up resistor and a second pull-up resistor;

[0011] The first end of the first pull-up resistor is connected to the output pin of the first omnipolar Hall effect chip, and the second end of the first pull-up resistor is connected to the power supply.

[0012] The first end of the second pull-up resistor is connected to the output pin of the second omnipolar Hall effect chip, and the second end of the second pull-up resistor is connected to the power supply.

[0013] Furthermore, the MCU is specifically used to determine that the tested magnetic latching relay is in an open state when both the first omnipolar Hall effect chip and the second omnipolar Hall effect chip output high-level signals; to determine that the tested magnetic latching relay is in a closed state when the first omnipolar Hall effect chip outputs a low-level signal and the second omnipolar Hall effect chip outputs a high-level signal; and to determine that there is external magnetic field interference when both the first omnipolar Hall effect chip and the second omnipolar Hall effect chip output low-level signals.

[0014] Furthermore, the magnetic latching relay switch state detection circuit also includes a first capacitor;

[0015] The first terminal of the first capacitor is connected to the power supply pin of the first omnipolar Hall effect chip and the power supply connection line, and the second terminal of the first capacitor is grounded.

[0016] Furthermore, the magnetic latching relay switch state detection circuit also includes a second capacitor;

[0017] The first end of the second capacitor is connected to the power supply pin of the second omnipolar Hall effect chip and the power supply connection line, and the second end of the second capacitor is grounded.

[0018] Furthermore, the magnetic latching relay switch state detection circuit also includes a third capacitor;

[0019] The first end of the third capacitor is connected to the connection line between the output pin of the first omnipolar Hall effect chip and the MCU, and the second end of the third capacitor is grounded.

[0020] Furthermore, the magnetic latching relay switch state detection circuit also includes a fourth capacitor;

[0021] The first end of the fourth capacitor is connected to the connection line between the output pin of the second omnipolar Hall effect chip and the MCU, and the second end of the fourth capacitor is grounded.

[0022] Furthermore, the magnetic field sensing sensitivity of the first omnipolar Hall effect chip is higher than that of the second omnipolar Hall effect chip.

[0023] Furthermore, both the first and second omnipolar Hall effect chips are in close contact with the bottom of the magnetic latching relay under test. Furthermore, the outer surface of the blunt needle needs to undergo a polishing process.

[0024] The advantages and beneficial effects of this utility model are as follows: by using a holographic Hall effect chip close to the permanent magnet in the magnetic latching relay to detect the opening and closing state of the magnetic latching relay, and by using a holographic Hall effect chip far away from the permanent magnet in the magnetic latching relay to detect external magnetic field interference, the detection results of the opening and closing state of the magnetic latching relay can be avoided by external superimposed magnetic fields. This solves the problem of misjudgment of the opening and closing state of the magnetic latching relay caused by external superimposed magnetic fields, and makes the detection results of the switch state detection circuit reliable and stable. Attached Figure Description

[0025] Fig. 1 This is the circuit diagram for detecting the switch status of the magnetic latching relay of this utility model;

[0026] Fig. 2 This is a schematic diagram showing the installation location of the magnetic latching relay switch status detection circuit.

[0027] In the diagram: 10, MCU; IC1, first omnipolar Hall effect chip; IC2, second omnipolar Hall effect chip; 1, power supply pin; 2, output pin; 3, ground pin; 4, power supply pin; 5, output pin; 6, ground pin; VCC, power supply; R1, first pull-up resistor; R2, second pull-up resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; K1, magnetic latching relay under test; K11, permanent magnet. Detailed Implementation

[0028] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solution of this utility model and should not be construed as limiting the scope of protection of this utility model.

[0029] according to Figs. 1-2As shown, this utility model is a magnetic latching relay switch state detection circuit, including: a first omnipolar Hall effect chip IC1, a second omnipolar Hall effect chip IC2, a power supply VCC, and an MCU10; power supply pins 1 and 4 of the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 are respectively connected to the power supply VCC, output pins 2 and 5 of the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 are respectively connected to the MCU10, and ground pins 3 and 6 of the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 are respectively connected to the ground. Both are grounded to GND; wherein, the first omnipolar Hall effect chip IC1 is mounted close to and in close contact with the permanent magnet K11 in the magnetic latching relay K1 under test, and the second omnipolar Hall effect chip IC2 is mounted away from the permanent magnet K11 and in close contact with the magnetic latching relay K1 under test, so that the second omnipolar Hall effect chip IC2 cannot detect the magnetic field generated by the permanent magnet K11; the MCU10 is used to determine the switching state of the magnetic latching relay K1 under test based on the signals output by the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2.

[0030] The omnipolar Hall effect chip integrates a Hall sensor element, which triggers the switching action by sensing changes in the external magnetic field. When the magnetic field strength reaches the set threshold (operating point Bop), the chip output state changes; when the magnetic field weakens to the release point (Brp), the output state returns to normal.

[0031] The first omnipolar Hall effect chip IC1 is installed at position 1, close to the permanent magnet inside the magnetic latching relay K1, and in close contact with the magnetic latching relay K1. The second omnipolar Hall effect chip IC2 should be installed at position 2, in close contact with the magnetic latching relay K1.

[0032] When the magnetic latching relay K1 is in the open state, and the magnetic field inside the magnetic latching relay K1 does not change, the output pins 2 and 4 of the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 both output high-level signals to the MCU10.

[0033] When the switch state of the magnetic latching relay K1 changes from open to closed, the first omnipolar Hall effect chip IC1 senses the change in the magnetic field generated by the permanent magnet K11 inside the magnetic latching relay K1, thereby triggering the switch action and outputting a low-level signal to the MCU10 from pin 2. Since the second omnipolar Hall effect chip IC2 is far from the permanent magnet K11 inside the magnetic latching relay K1, it cannot sense the change in the magnetic field inside the magnetic latching relay K1 when the switch state of K1 changes, thus maintaining its initial state and outputting a high-level signal to the MCU10 from pin 4.

[0034] When there are interference sources such as motors, transformers, and wireless charging devices in the environment, the superimposed magnetic field will cause the magnetic field change detection value to exceed the threshold. The first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 will both detect the magnetic field change, causing the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 to trigger a switching action. The MCU10 judges that there is external magnetic field interference.

[0035] This invention detects the open / closed state of a magnetic latching relay by using an omnipolar Hall effect chip close to the permanent magnet in the relay and by using an omnipolar Hall effect chip far from the permanent magnet in the relay to detect external magnetic field interference. This avoids interference from external superimposed magnetic fields in the detection results of the magnetic latching relay's open / closed state, solves the problem of misjudgment of the magnetic latching relay's open / closed state caused by external superimposed magnetic fields, and makes the detection results of the switch state detection circuit reliable and stable.

[0036] To ensure that the output pins of the first and second omnipolar Hall effect chips stably output high-level signals when the tested magnetic latching relay switch is in the open state, preventing false triggering and thus improving the reliability of the switch state detection circuit, a further preferred embodiment of this invention further includes a first pull-up resistor R1 and a second pull-up resistor R2 in the magnetic latching relay switch state detection circuit; the first end of the first pull-up resistor R1 is connected to the output pin 2 of the first omnipolar Hall effect chip IC, and the second end of the first pull-up resistor R1 is connected to the power supply VCC; the first end of the second pull-up resistor is connected to the output pin 4 of the second omnipolar Hall effect chip IC2, and the second end of the second pull-up resistor R2 is connected to the power supply VCC.

[0037] To ensure stable and reliable detection results, the preferred embodiment of this utility model is as follows: the MCU is specifically used to determine that the tested magnetic latching relay K1 is in an open state when both the first omnidirectional Hall effect chip IC1 and the second omnidirectional Hall effect chip IC2 output high-level signals; to determine that the tested magnetic latching relay K1 is in a closed state when both the first omnidirectional Hall effect chip IC1 outputs a low-level signal and the second omnidirectional Hall effect chip IC2 outputs a high-level signal; and to determine that the test is due to external magnetic field interference when both the first omnidirectional Hall effect chip IC1 and the second omnidirectional Hall effect chip IC2 output low-level signals.

[0038] In order to filter out the high-frequency ripple and noise that may be generated when the power supply powers the first omnipolar Hall effect chip, a further preferred embodiment of the present invention includes a first capacitor C1 in the magnetic latching relay switch state detection circuit; the first end of the first capacitor C1 is connected to the connection line between the power supply pin 1 of the first omnipolar Hall effect chip IC1 and the power supply VCC, and the second end of the first capacitor C1 is grounded.

[0039] In order to filter out the high-frequency ripple and noise that may be generated when the power supply powers the second omnipolar Hall effect chip, a further preferred embodiment of the present invention includes a second capacitor C2 in the magnetic latching relay switch state detection circuit; the first end of the second capacitor C2 is connected to the connection line between the power supply pin 4 of the second omnipolar Hall effect chip IC2 and the power supply VCC, and the second end of the second capacitor C2 is grounded.

[0040] In order to filter out noise interference in the output pin of the first omnipolar Hall effect chip and the MCU connection line, and to ensure that the signal output by the first omnipolar Hall effect chip is purer and more stable, a further preferred embodiment of this utility model is that the magnetic latching relay switch state detection circuit also includes a third capacitor C3; the first end of the third capacitor C3 is connected to the connection line between the output pin 2 of the first omnipolar Hall effect chip IC1 and the MCU, and the second end of the third capacitor C3 is grounded.

[0041] To filter out noise interference in the output pins of the second omnipolar Hall effect chip and the MCU connection line, and to ensure that the signal output by the second omnipolar Hall effect chip is purer and more stable, the magnetic latching relay switch state detection circuit also includes a fourth capacitor C4; the first end of the fourth capacitor C4 is connected to the connection line between the output pin 5 of the second omnipolar Hall effect chip IC2 and the MCU, and the second end of the fourth capacitor C4 is grounded.

[0042] To ensure accurate and reliable test results, a further preferred embodiment of this invention is that the magnetic field sensing sensitivity of the first omnipolar Hall effect chip IC1 is higher than that of the second omnipolar Hall effect chip IC2.

[0043] The first omnipolar Hall effect chip IC1 must be a high-sensitivity omnipolar Hall effect chip, while the second omnipolar Hall effect chip IC2 must be a low-sensitivity omnipolar Hall effect chip. This ensures that the first omnipolar Hall effect chip IC1 can detect the change in the magnetic field of the permanent magnet caused by the change in the switching state of the magnetic latching relay K1, while the second omnipolar Hall effect chip IC2 cannot detect the change in the magnetic field of the permanent magnet caused by the change in the switching state of the magnetic latching relay K1.

[0044] In order to match the magnetic circuit characteristics of the permanent magnet and increase mechanical reliability, the preferred embodiment of this utility model is that the first omnipolar Hall effect chip IC1 and the second omnipolar Hall effect chip IC2 are both closely attached to the bottom of the magnetic latching relay K1 under test.

[0045] The permanent magnet's pole axis is perpendicular to the contact's movement direction, and the magnetic field vector direction in the bottom region is stable. Bottom mounting matches the permanent magnet's magnetic circuit characteristics. Furthermore, bottom mounting ensures that the pressure on the omnipolar Hall effect chip is aligned with the relay contact's movement direction, preventing displacement caused by shear forces.

[0046] The above are merely preferred embodiments of this utility model. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.

Claims

1. A magnetic latching relay switch state detection circuit, characterized in that, include: First omnipolar Hall effect chip, second omnipolar Hall effect chip, power supply and MCU; The power supply pins of the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are respectively connected to the power supply, the output pins of the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are respectively connected to the MCU, and the ground pins of the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are both grounded; The first omnipolar Hall effect chip is mounted close to and in close contact with the permanent magnet in the magnetic latching relay under test, while the second omnipolar Hall effect chip is mounted far from the permanent magnet and in close contact with the magnetic latching relay under test, so that the second omnipolar Hall effect chip cannot detect the magnetic field generated by the permanent magnet. The MCU is used to determine the switching state of the magnetic latching relay under test based on the signals output by the first omnipolar Hall effect chip and the second omnipolar Hall effect chip.

2. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, The magnetic latching relay switch state detection circuit further includes a first pull-up resistor and a second pull-up resistor; The first end of the first pull-up resistor is connected to the output pin of the first omnipolar Hall effect chip, and the second end of the first pull-up resistor is connected to the power supply. The first end of the second pull-up resistor is connected to the output pin of the second omnipolar Hall effect chip, and the second end of the second pull-up resistor is connected to the power supply.

3. The magnetic latching relay switch state detection circuit according to claim 2, characterized in that, Specifically, the MCU is used to determine that the tested magnetic latching relay is in an open state when both the first omnipolar Hall effect chip and the second omnipolar Hall effect chip output high-level signals; to determine that the tested magnetic latching relay is in a closed state when the first omnipolar Hall effect chip outputs a low-level signal and the second omnipolar Hall effect chip outputs a high-level signal; and to determine that external magnetic field interference occurs when both the first omnipolar Hall effect chip and the second omnipolar Hall effect chip output low-level signals.

4. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, The magnetic latching relay switch state detection circuit also includes a first capacitor; The first terminal of the first capacitor is connected to the power supply pin of the first omnipolar Hall effect chip and the power supply connection line, and the second terminal of the first capacitor is grounded.

5. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, The magnetic latching relay switch state detection circuit also includes a second capacitor; The first end of the second capacitor is connected to the power supply pin of the second omnipolar Hall effect chip and the power supply connection line, and the second end of the second capacitor is grounded.

6. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, The magnetic latching relay switch state detection circuit also includes a third capacitor; The first end of the third capacitor is connected to the connection line between the output pin of the first omnipolar Hall effect chip and the MCU, and the second end of the third capacitor is grounded.

7. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, The magnetic latching relay switch state detection circuit also includes a fourth capacitor; The first end of the fourth capacitor is connected to the connection line between the output pin of the second omnipolar Hall effect chip and the MCU, and the second end of the fourth capacitor is grounded.

8. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, The magnetic field sensing sensitivity of the first omnipolar Hall effect chip is higher than that of the second omnipolar Hall effect chip.

9. The magnetic latching relay switch state detection circuit according to claim 1, characterized in that, Both the first omnipolar Hall effect chip and the second omnipolar Hall effect chip are closely attached to the bottom of the magnetic latching relay under test.

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