Switch configuration circuit and switch

Abstract

The utility model discloses a switch configuration circuit and a switch, and relates to the technical field of circuits, the switch configuration circuit comprises a control unit and a switch chip, the control unit is connected with the switch chip through a plurality of switching branches; the switching branch comprises a switch unit and a storage unit, the control end of the switch unit is connected with the control unit, and the output end of the switch unit is connected with the first power supply end of the storage unit; the output end of the storage unit is connected with the switch chip; a reset branch is further connected between the control unit and the switch chip, and an output port of the reset branch is connected with a reset port of the switch chip. Thus, through switching of the switching branch on the hardware structure, different configurations required by the switch chip are realized, software code development is reduced, operation is simplified, and time is saved.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, and in particular to a switch configuration circuit and a switch. Background Technology

[0002] Typically, switch chips are configured only once after power-on, for example, to determine a fixed mirror port. However, in actual use, there are also situations where dynamic switching is required. This can be achieved by configuring the chip's internal registers through the SMC / I2C / SPI interface, and by using different data output from the MCU / FPGA to configure the switch chip.

[0003] However, configuring chips using MCUs / FPGAs requires software code development, which is complex and time-consuming. Utility Model Content

[0004] To address the aforementioned issues, this invention provides a switch configuration circuit and a switch, thereby reducing the operational complexity and time-consuming nature of software code development.

[0005] The present invention discloses the following technical solutions:

[0006] In a first aspect, this application provides a switch configuration circuit, including a control unit and a switch chip, wherein the control unit and the switch chip are connected through a switching branch, and the switching branch includes multiple branches;

[0007] The switching branch includes a switching unit and a storage unit. The control terminal of the switching unit is connected to the control unit, and the output terminal of the switching unit is connected to the first power supply terminal of the storage unit. The output terminal of the storage unit is connected to the switch chip.

[0008] A reset branch is also connected between the control unit and the switch chip, and the output port of the reset branch is connected to the reset port of the switch chip.

[0009] Optionally, the input terminal of the switching unit is connected to the second power supply terminal, and the input terminal of the switching unit is also connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded;

[0010] The output terminal of the switching unit is also connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

[0011] Optionally, the output terminal of the storage unit is configured with a pull-up resistor.

[0012] Optionally, if all of the switching branches are disconnected, the reset branch is turned on.

[0013] Optionally, each time the switch chip is powered on for configuration, one of the multiple switching branches is activated.

[0014] Optionally, the storage unit stores the configuration program for the mirror port of the switch chip, and the mirror port indicated by each storage unit in the multiple switching branches is different from the others.

[0015] Optionally, the storage unit is connected to the switch chip via an I2C interface.

[0016] Optionally, the storage unit is an electrically erasable programmable read-only memory.

[0017] Optionally, the switching unit is a load switch or a low-dropout regulator.

[0018] Secondly, this application also provides a switch that employs a switch configuration circuit as described in any of the above claims.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] This invention provides a switch configuration circuit and a switch, including a control unit and a switch chip. The control unit and the switch chip are connected via multiple switching branches. Each switching branch includes a switching unit and a storage unit. The control terminal of the switching unit is connected to the control unit, and the output terminal of the switching unit is connected to the first power supply terminal of the storage unit. The output terminal of the storage unit is connected to the switch chip. A reset branch is also connected between the control unit and the switch chip, and the output port of the reset branch is connected to the reset port of the switch chip. By setting a reset branch and multiple switching branches between the control unit and the switch chip, each switching branch includes a switching unit and a storage unit. The control unit controls the switching unit in one of the multiple switching branches to turn on, powering on the storage unit of that switching branch, thereby enabling the switch chip to read the start program in the storage unit. Multiple switching branches can correspond to multiple start programs, and the conduction of different switching branches allows the switch chip to be configured with the required program each time it is powered on. Furthermore, upon completion of the task, the control unit can output a reset signal to the switch chip via the reset branch to reset the switch chip. In this way, by switching the branch in the hardware structure, the different configurations required by the switch chip can be achieved, reducing software code development, simplifying operation, and saving time. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A reset timing diagram of a switch chip provided by this utility model;

[0023] Figure 2 A schematic diagram of a switch configuration circuit provided by this utility model;

[0024] Figure 3 A functional block diagram of a switching unit provided by this utility model;

[0025] Figure 4 A schematic diagram of the specific circuit structure of a switching unit and its corresponding storage unit provided by this utility model;

[0026] Figure 5 This is a schematic diagram of the structure of a pull-up resistor provided by this utility model. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Switch chips include a reset pin, such as the input pin RSTn of the JL6110-PC chip. Pulling the reset pin low or powering it on enables a hardware reset of the switch chip. Further details can be found below. Figure 1The diagram illustrates the reset timing of a switch chip. After the hardware reset is disconnected, the switch-level chip initializes itself by loading data from configuration pins, electrically erasable programmable read-only memory (EEPROM), or flash memory. After a power-on timeout (T0), it accesses registers via the SMC / I2C / SPI interface. Therefore, the chip's internal registers can be configured using EEPROM, SMC / I2C / SPI interfaces, etc. The SMC / I2C / SPI interface can be implemented using an MCU / FPGA, allowing different data outputs from the MCU / FPGA to configure the switch chip. However, configuring the switch chip using an MCU / FPGA requires software code development, which is time-consuming and more complex.

[0029] Based on this, see Figure 2 The diagram shows a schematic of a switch configuration circuit. The switch configuration circuit includes a control unit and a switch chip. The control unit and the switch chip are connected via a switching branch, which includes multiple switching branches. Each switching branch includes a switching unit and a storage unit. The control terminal of the switching unit is connected to the control unit, and the output terminal of the switching unit is connected to the first power supply terminal of the storage unit. The output terminal of the storage unit is connected to the switch chip. A reset branch is also connected between the control unit and the switch chip, and the output port of the reset branch is connected to the reset port of the switching chip.

[0030] The aforementioned switch is a type of network hardware that receives and forwards data to target devices through message exchange.

[0031] Optional, see Figure 2 The switching branch connecting the control unit and the switch chip can be configured with three branches. Each of the three switching branches is configured with a switching unit and a storage unit, such as... Figure 2 The three switching branches are the branch connected to switch unit 1 and storage unit 1, the branch connected to switch unit 2 and storage unit 2, and the branch connected to switch unit 3 and storage unit 3, respectively.

[0032] Optionally, the aforementioned multiple switching branches can store different start programs. These start programs are used for initialization and configuration of the switch chip. Thus, by controlling the switching units on different switching branches, see [link to documentation]. Figure 2 This causes the switch chip to load the start program of the memory unit on the corresponding switched branch.

[0033] Understandably, each time the switch chip is powered on for initial configuration and subsequent operation based on that initial configuration, the control unit controls the switching unit to keep one of the multiple switching branches connected to the switch chip in a conducting state, while keeping the other switching branches in a disconnected state.

[0034] When the switch chip is working, the connected switching branches must remain connected. When the switch chip finishes working and all the connected switching branches are disconnected, after the control unit controls the storage unit to power off, it needs to send a reset signal to the switch chip through the reset branch to perform a soft reset on the switch chip, so that the switch chip can enter a new loading process, so that the switch chip can be initialized and configured next time.

[0035] Optionally, the aforementioned switching unit can be a single-channel load switch with adjustable current, or a low-dropout regulator, or any other power control module capable of power transmission and interruption.

[0036] Optionally, when the switching unit is a load switch, the input terminal of the load switch needs to be connected to the power supply terminal to ensure that when the load switch is turned on, the output terminal of the load switch can power on the connected storage unit. For example, see... Figure 3 The diagram shows a functional block diagram of a switching unit. The switching unit may include an input terminal (see...). Figure 3 IN pin), output terminal (see IN pin), output terminal (see IN pin) Figure 3 The EN pin in the diagram) and the control terminal (see...) Figure 3 The input terminal of the switching unit can be connected to the second power supply terminal (OUT pin in the circuit), and the output terminal can be connected to the power supply terminal of the storage unit in the branch where the switching unit is located, and then connected to the control terminal of the switching unit through the control unit.

[0037] In addition, the input terminal of the switching unit is also connected to a first capacitor C. IN The first terminal, the first capacitor C IN The second terminal is grounded; the output terminal of the switching unit is also connected to a second capacitor C. OUT The first terminal, the second capacitor C OUT The second terminal is grounded.

[0038] Thus, the output voltage of the output terminal (out pin) is controlled by the control unit applying a high or low level to the control terminal (EN pin) of the switching unit. Specifically, when the control unit inputs a low level to the control terminal (EN pin), the output voltage of the output terminal (out pin) is 0; when the control unit inputs a high level to the control terminal (EN pin), the output voltage of the output terminal (out pin) is equal to VIN.

[0039] In one possible implementation, see Figure 4The diagram shown is a schematic diagram of the specific circuit structure of a switching unit and its corresponding storage unit. Figure 2 The three switching units in the middle can be respectively Figure 4 U177, U178, and U179 in the list, Figure 2 The three storage units can be respectively Figure 4 The three switch units, U171, U175, and U176, are listed in the original text. The input terminals of the three switch units, U177, U178, and U179, can be connected to a 3.3V power supply. When the control unit inputs a high level to the control terminal of a switch unit, that switch unit is turned on, and its output terminal can output a 3.3V voltage to the power supply terminal (VCC pin) of the corresponding connected memory unit.

[0040] In this way, the power supply to the storage unit can be controlled by the control unit controlling the switching unit. Only when the storage unit is powered normally can the switch chip load the start program in the storage unit.

[0041] Optionally, the above-mentioned storage unit can be an electrically erasable programmable read-only memory (EEPROM). For example, the storage unit of this application can be the AIP24C02 from AMEC, or other EEPROMs can be used.

[0042] The AIP24C02 mentioned above is a 2048-bit serial electrically erasable programmable read-only memory (EEPROM). The memory has a structure of 256x8 bits, internally divided into 32 pages, each page containing 8 bytes. A random word address requires an 8-bit data word address.

[0043] Each EEPROM storage unit can be connected to the corresponding pin of the switch chip via an I2C interface through SDA (data line) and SCL (clock line). Only two lines are needed for communication, reducing hardware resource configuration and lowering costs. Furthermore, the EEPROM is open-drain, meaning it only has the ability to output a low level, so power failure does not affect other branches, reducing interference. For an example, see [link to example]. Figure 4 Each memory cell outputs one I2C_SCL signal and one I2C_SDA signal.

[0044] For example, the aforementioned switch chip can be JL6110, which transmits the I2C_SCL and I2C_SDA signals output by the storage unit to the I2C master of the switch chip, and controls the I2C bus communication through the I2C master.

[0045] In one example, see Figure 5The diagram shows a pull-up resistor structure. A pull-up resistor is configured at the output terminal of the memory cell to output a high level. Specifically, as shown... Figure 5 The transmission line for transmitting the I2C_SCL signal from the memory cell is also connected to the first terminal of resistor R222, and the second terminal of resistor R222 is connected to the power supply terminal. Similarly, the transmission line for transmitting the I2C_SDA signal from the memory cell is also connected to the first terminal of resistor R219, and the second terminal of resistor R219 is connected to the power supply terminal.

[0046] Optionally, the aforementioned storage unit may store the configuration program of the mirror port of the switch chip, and the mirror port indicated by each storage unit in the multiple switching branches is different from each other.

[0047] Port mirroring allows for network monitoring by forwarding data traffic from one or more source ports to a designated port, known as the mirror port or destination port. Without significantly impacting the normal throughput of the source ports, network traffic can be monitored and analyzed through mirror ports. Port mirroring is a feature of switches or routers. Typically, the switching chip is configured to mirror the port only once after power-on, at which point the mirror port is fixed. However, in actual use, the mirror port may need to be dynamically switched.

[0048] This application is based on the fact that each memory cell in multiple switching circuits is configured with a different mirror port. Thus, each time the switch chip powers on and reads the start program in the memory cell of the activated switching circuit, it can configure the mirror port indicated in the start program of that memory cell. In this way, activating different switching branches allows the switch chip to configure different mirror ports.

[0049] Optionally, the control unit can be a microcontroller unit (MCU) or a field-programmable gate array (FPGA). The control unit is connected to the control terminal of the switching unit via an I / O port.

[0050] Based on the above embodiments, the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0051] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A switch configuration circuit, characterized in that, It includes a control unit and a switch chip, wherein the control unit and the switch chip are connected through a switching branch, and the switching branch includes multiple branches. The switching branch includes a switching unit and a storage unit. The control terminal of the switching unit is connected to the control unit, and the output terminal of the switching unit is connected to the first power supply terminal of the storage unit. The output terminal of the storage unit is connected to the switch chip. A reset branch is also connected between the control unit and the switch chip, and the output port of the reset branch is connected to the reset port of the switch chip.

2. The circuit according to claim 1, characterized in that, The input terminal of the switching unit is connected to the second power supply terminal, and the input terminal of the switching unit is also connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded. The output terminal of the switching unit is also connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

3. The circuit according to claim 1, characterized in that, The output terminal of the storage unit is equipped with a pull-up resistor.

4. The circuit according to any one of claims 1-3, characterized in that, When all of the aforementioned switching branches are disconnected, the reset branch is turned on.

5. The circuit according to claim 4, characterized in that, Each time the switch chip is powered on and configured, it activates one of the multiple switching branches.

6. The circuit according to claim 5, characterized in that, The storage unit stores the configuration program for the mirror port of the switch chip, and the mirror port indicated by each storage unit in the multiple switching branches is different from the others.

7. The circuit according to claim 5, characterized in that, The storage unit is connected to the switch chip via an I2C interface.

8. The circuit according to claim 5, characterized in that, The storage unit is an electrically erasable programmable read-only memory.

9. The circuit according to claim 1, characterized in that, The switching unit is a load switch or a low-dropout voltage regulator.

10. A switch, characterized in that, A switch configuration circuit according to any one of claims 1-9.

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