Semiconductor device and memory device

Abstract

An embodiment of the present disclosure provides a semiconductor device including a substrate, a logic device formed on the substrate, a plurality of metal wiring layers disposed over the substrate and having metal wiring connected to the logic device, and a plurality of multi-programmable non-volatile memory cells formed between the metal wiring layers. The non-volatile memory unit capable of being programmed for multiple times comprises a fin type field effect transistor, wherein the fin field effect transistor has a fin structure, a memory gate disposed around a channel region of the fin structure, a first control gate formed around a first sidewall of the memory gate and connected to the first word line, and a second control gate formed around a second sidewall of the memory gate and connected to the second word line.

Description

Semiconductor devices and memory devices Technical Field

[0001] This disclosure relates to semiconductor devices and memory devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Manufacturing semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern multiple material layers to form circuit components and elements on those components.

[0003] The semiconductor industry continuously improves the integration density of multiple electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, thus allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] The problem this disclosure seeks to solve is how to improve the integration density of electronic components, allowing more components to be integrated into a given area.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a plurality of metal wiring layers, and a plurality of reprogrammable non-volatile memory cells. The substrate has logic devices formed thereon. The metal wiring layers are disposed above the substrate and have metal wiring connected to the logic devices. The reprogrammable non-volatile memory cells are formed between the metal wiring layers. Each reprogrammable non-volatile memory cell includes a fin field-effect transistor (FFET). The fin field-effect transistor has a fin structure, a storage gate disposed around a channel region of the fin structure, a first control gate formed around a first sidewall of the storage gate and connected to a first word line, and a second control gate formed around a second sidewall of the storage gate and connected to a second word line.

[0006] According to some embodiments of this disclosure, a memory device includes a logic device, a plurality of metal wiring layers having metal wiring connected to the logic device, and a reprogrammable non-volatile memory cell located between the metal wiring layers. The reprogrammable non-volatile memory cell includes a fin field-effect transistor, the fin field-effect transistor having an indium gallium zinc oxide fin, a storage gate disposed around a channel region of the indium gallium zinc oxide fin, a first control gate formed around a first sidewall of the storage gate and connected to a first word line, and a second control gate formed around a second sidewall of the storage gate and connected to a second word line.

[0007] According to some embodiments of this disclosure, a semiconductor device includes a substrate having logic devices formed thereon, and a plurality of metal wiring layers disposed above the logic devices and the substrate and having metal wiring connected to the logic devices. The metal wiring layers include an upper metal wiring layer having a plurality of metal lines, a plurality of vias, and a flat oxide layer. The semiconductor device includes a fin structure above the oxide layer in the upper metal wiring layer, a high-dielectric-constant dielectric layer above the oxide layer and the fin structure, a memory gate above a channel region of the fin structure, a first control gate located on a first side of the memory gate and connected to a first word line, and a second control gate located on a second side of the memory gate and connected to a second word line. The vias and metal lines in the upper metal wiring layer connect at least one of the first control gate, the second control gate, and the source / drain regions of the fin structure to the logic device.

[0008] This disclosure provides a method for increasing the device density of NAND devices and / or NOR devices in integrated circuits using back-end processes, including fabricating reprogrammable non-volatile memory cells in an upper metallization layer of the back-end process to increase the density of reprogrammable non-volatile memory cells in integrated circuits. Attached Figure Description

[0009] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1A illustrates a schematic diagram of an example fin field-effect transistor according to several embodiments, wherein the fin field-effect transistor forms a memory cell capable of storing two bits of metadata;

[0011] Figure 1B illustrates a top view of an example fin field-effect transistor in a memory device according to several embodiments, the memory device being able to store two bits of metadata;

[0012] Figure 1C illustrates a cross-sectional view of an example fin field-effect transistor in a memory device along the cutting line AA′ of Figure 1B, according to several embodiments. The memory device can store two bits of metadata.

[0013] Figure 2A illustrates a top view of a portion of an example semiconductor device according to several embodiments;

[0014] Figure 2B illustrates a cross-sectional view along the X-axis of an example transistor of Figure 2A according to several embodiments;

[0015] Figure 2C illustrates a cross-sectional view along the Y-axis of an example transistor of Figure 2A according to several embodiments;

[0016] Figure 2D illustrates a schematic diagram of an example of a reprogrammable 4×4 NOR array of Figure 2A according to several embodiments;

[0017] Figures 3A and 3B illustrate cross-sectional views of a portion of an example semiconductor device;

[0018] Figure 4A illustrates a top view of a portion of an example semiconductor device according to several embodiments;

[0019] Figure 4B illustrates a cross-sectional view along the X-axis of an example transistor of Figure 4A according to several embodiments;

[0020] Figure 4C illustrates a cross-sectional view along the Y-axis of an example transistor of Figure 4A according to several embodiments;

[0021] Figure 4D illustrates a schematic diagram of an example of a reprogrammable NAND array of Figure 4A according to several embodiments;

[0022] Figures 5A and 5B illustrate cross-sectional views of a portion of an example semiconductor device according to various embodiments;

[0023] Figure 6 illustrates an example method flowchart for manufacturing a semiconductor device according to several embodiments.

[0024] [Symbol Explanation]

[0025] 102: Transistor

[0026] 104: Source Extreme

[0027] 105: Leakage extreme

[0028] 106: Oxide layer

[0029] 108: Fin Structure

[0030] 110: Storage gate

[0031] 112: First control gate

[0032] 114: Second control gate

[0033] 116: High dielectric constant dielectric layer

[0034] 118: First side

[0035] 120: Second side

[0036] 200: Semiconductor devices

[0037] 202: Transistor

[0038] 204: Array

[0039] 206: Oxide layer

[0040] 208: Fin structure

[0041] 210: Storage gate

[0042] 212: First control gate

[0043] 214: Second control gate

[0044] 215: line

[0045] 216: High dielectric constant dielectric layer

[0046] 217: Column

[0047] 218: First side

[0048] 219: Source Line

[0049] 220: Second side

[0050] 300: Semiconductor Devices

[0051] 302:Substrate

[0052] 304: Interconnection Structure

[0053] 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7: Metallization layer

[0054] 306: Logic Device

[0055] 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7: Intermetallic dielectric layer

[0056] 310: Metal wire

[0057] 312: Through hole

[0058] 316: Transistor

[0059] 318: Fin structure

[0060] 320: Memory gate

[0061] 322: First control gate

[0062] 324: Second control gate

[0063] 325: Through hole

[0064] 326: Through hole

[0065] 327: High dielectric constant dielectric layer

[0066] 328: Through hole

[0067] 330: Through hole

[0068] 332: Through hole

[0069] 400: Semiconductor Devices

[0070] 402: Transistor

[0071] 404: Array

[0072] 406: Oxide layer

[0073] 408: Fin Structure

[0074] 410: Storage gate

[0075] 412: First control gate

[0076] 414: Second control gate

[0077] 415: Line

[0078] 416: High dielectric constant dielectric layer

[0079] 417: Column

[0080] 418: First side

[0081] 419: Ground Selection Transistor

[0082] 420: Second side

[0083] 421: Bit line select transistor

[0084] 500: Semiconductor Devices

[0085] 502:Substrate

[0086] 504: Interconnection Structure

[0087] 504-1, 504-2, 504-3, 504-4, 504-5, 504-6, 504-7: Metallization layer

[0088] 506: Logic Device

[0089] 508-1, 508-2, 508-3, 508-4, 508-5, 508-6, 508-7: Intermetallic dielectric layer

[0090] 510: Metal wire

[0091] 512: Through hole

[0092] 516: Transistor

[0093] 518: Fin Structure

[0094] 520: Memory gate

[0095] 522: First control gate

[0096] 524: Second control gate

[0097] 525: Through hole

[0098] 526: Through hole

[0099] 527: High dielectric constant dielectric layer

[0100] 528: Through hole

[0101] 530: Through hole

[0102] 532: Through hole

[0103] 600: Method

[0104] 602, 604, 606, 608, 610, 612, 614, 616, 618: Squares

[0105] AA′: Cutting line

[0106] BL k BL k+1 BL k+2 BL k+3 BL m BL m+1 :bit line

[0107] SL m ,SL m+1 Source line

[0108] WL,WL′,WL0,WL0′,WL1,WL1′,WL n WL n ′,WL n+1 WL n+2 WL n+3 WL n+3 ′: Character line

[0109] X, Y, Z: Axes Detailed Implementation

[0110] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0111] For the sake of brevity, this document may not detail known techniques for manufacturing conventional semiconductor devices. Furthermore, the various steps and processes described herein can be combined into more comprehensive procedures or processes that have additional functionality not detailed herein. Specifically, many processes for manufacturing semiconductor devices are known; therefore, for the sake of brevity, many known processes will be briefly described, or known processes may be omitted entirely without providing details of known processes. Upon full review of this disclosure, those skilled in the art will understand that the structures disclosed herein can be applied to a variety of technologies and can be incorporated into a variety of semiconductor devices and products. It is further worth noting that semiconductor device structures may include a varying number of components, and a single component in the figures may represent multiple components.

[0112] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings of this document.

[0113] Furthermore, this document may use spatial relative terms such as “above,” “overlapping,” “on top,” “upper,” “top,” “below,” “under,” “below,” “lower,” “bottom,” etc., to describe the relationship of one element or feature to another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly. When a first element is described relative to a second element using, for example, the spatial relative terms listed above, the first element may be directly on top of the second element, or there may be elements or layers intervening between them.

[0114] Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0115] It is worth noting that when references are made to "an embodiment," "an example embodiment," "an exemplary embodiment," "exemplary," or "example," etc., it indicates that the embodiment may include specific features, structures, or characteristics, but not every embodiment needs to include specific features, structures, or characteristics. Furthermore, these terms do not need to represent the same embodiment. Moreover, when an embodiment is described using specific features, structures, or characteristics, those skilled in the art should understand that these features, structures, or characteristics may be relevant to other embodiments, regardless of whether other embodiments are explicitly described.

[0116] In some embodiments herein, a "material layer" is a layer comprising at least 50 wt% of the material, such as at least 60 wt% of the material, at least 75 wt% of the material, at least 90 wt% of the material, at least 95 wt% of the material, or at least 99 wt% of the material; and a "material" layer comprises at least 50 wt% of the material, such as at least 60 wt% of the material, at least 75 wt% of the material, at least 90 wt% of the material, at least 90 wt% of the material, or at least 99 wt% of the material. For example, in some embodiments, the respective aluminum layers and a layer of aluminum are a layer of aluminum comprising at least 50 wt%, at least 60 wt%, at least 75 wt%, at least 90 wt%, at least 95 wt%, or at least 90 wt%.

[0117] It should be understood that the wording or terminology used herein is descriptive and not restrictive, enabling those skilled in the art to understand the terminology or terminology of this disclosure in light of the teachings herein.

[0118] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. In the description herein, unless explicitly stated otherwise, the same reference numerals in the different figures represent the same or similar components formed using the same or similar materials and the same or similar methods.

[0119] Additional operations may be provided before, during, and / or after the stages described in the embodiments. For different embodiments, some stages may be replaced or omitted. Additional features may be added to the semiconductor device structure. For different embodiments, some features described below may be replaced or omitted. Although some embodiments are described as performing operations in a specific order, these operations may be performed in other logical orders.

[0120] In this paper, a “layer” is a region, such as a region with arbitrary boundaries, and does not need to have a uniform thickness. For example, a layer can be a region that includes at least some thickness variations.

[0121] Multiple-time programmable (MTP) non-volatile memory (NVM) cells can be formed as NAND devices or NOR devices. Embodiments herein provide methods for forming multiple-time programmable NVM cells during back-end of line (BEOL) processes. Embodiments herein provide methods for increasing the device density of NAND and / or NOR devices in integrated circuits using back-end processes. In several embodiments, multiple-time programmable NVM cells are fabricated in an upper metallization layer to increase the density of multiple-time programmable NVM cells in integrated circuits. In several embodiments, NAND and / or NOR devices are fabricated in an upper metallization layer to increase the device density of NAND and / or NOR devices in integrated circuits. In several embodiments, a single NVM cell is configured to store two bits of data to increase the density of multiple-time programmable NVM cells in integrated circuits.

[0122] According to several embodiments, FIG1A illustrates a schematic diagram of an example fin field-effect transistor 102, wherein the example fin field-effect transistor 102 forms a memory cell capable of storing two bits of metadata. According to several embodiments, FIG1B illustrates a top view of an example fin field-effect transistor 102 in a memory device capable of storing two bits of metadata. According to several embodiments, FIG1C illustrates a cross-sectional view of the example fin field-effect transistor 102 in the memory device of FIG1B along cut line AA′, wherein the memory device can store two bits of metadata. The example fin field-effect transistor 102 includes a source, a drain, and other elements. Depending on the context, the source / drain regions used herein may represent the source or drain independently or collectively.

[0123] As illustrated in Figures 1A to 1C, an example fin field-effect transistor 102 is formed on an oxide layer 106 in a metallization layer above a substrate. The example fin field-effect transistor 102 includes a fin structure 108 formed over a portion of the oxide layer 106, a storage gate 110 formed in a channel region of the fin structure 108 and over a portion of the oxide layer 106 to store electrons emitted by the fin structure 108, a first control gate 112 formed over the oxide layer 106 and on a first sidewall of the storage gate 110, and a second control gate 114 formed over the oxide layer 106 and on a second sidewall of the storage gate 110. The example fin field-effect transistor 102 further includes a high-dielectric-constant dielectric layer 116 disposed between the fin structure 108 and the storage gate 110, between the storage gate 110 and the oxide layer 106, between the first control gate 112 and the oxide layer 106, and between the second control gate 114 and the oxide layer 106. The example fin field-effect transistor 102 also includes a source terminal 104 and a drain terminal 105 on opposite ends of the fin structure 108.

[0124] During a write operation, the fin structure 108 can emit electrons stored in the storage gate 110. An example fin field-effect transistor 102 is configured to use a first control gate 112 to store a first bit value (based on the number of stored electrons) in a first side 118 of the storage gate 110, and is configured to use a second control gate 114 to store a second bit value (based on the number of stored electrons) in a second side 120 of the storage gate 110.

[0125] During a read operation, the example fin field-effect transistor 102 is configured to read a first bit value (based on the number of stored electrons) from a first side 118 of the storage gate 110 using a first control gate 112, and is configured to read a second bit value (based on the number of stored electrons) from a second side 120 of the storage gate 110 using a second control gate 114. Therefore, the example fin field-effect transistor 102 can be used in higher-density memory cells to store and access two bits of metadata, thus increasing memory array density compared to memory arrays that store and access a single bit of metadata per memory cell.

[0126] According to several embodiments, FIG2A illustrates a top view of a portion of an example semiconductor device 200. The example semiconductor device 200 includes a plurality of fin field-effect transistors 202 arranged as NOR devices in a multiprogrammable 4×4 NOR array 204. FIG2B illustrates a cross-sectional view of the example transistors 202 of FIG2A along the X-axis, and FIG2C illustrates a cross-sectional view of the example transistors 202 of FIG2A along the Y-axis. FIG2D illustrates a schematic diagram of the example multiprogrammable 4×4 NOR array 204 of FIG2A. For clarity, not all features of the semiconductor device 200 are shown in FIG2A, 2B, 2C, and 2D, and FIG2A, 2B, 2C, and 2D may only show a portion of the formed semiconductor structure. The example transistors 202 and the example NOR array 204 are fabricated within an upper metallization layer, for example, between a fifth and a sixth metallization layer or between a sixth and a seventh metallization layer.

[0127] As illustrated in Figures 2A, 2B, and 2C, the example fin field-effect transistor 202 is formed on an oxide layer 206 of a metallization layer, and includes a fin structure 208 formed on a portion of the oxide layer 206, a storage gate 210 formed in a channel region of the fin structure 208 and on a portion of the oxide layer 206 to store electrons emitted by the fin structure 208, a first control gate 212 formed on the oxide layer 206 and on a first sidewall of the storage gate 210, and a second control gate 214 formed on the oxide layer 206 and on a second sidewall of the storage gate 210. The example fin field-effect transistor 202 further includes a high-dielectric-constant dielectric layer 216 disposed between the fin structure 208 and the storage gate 210, between the storage gate 210 and the oxide layer 206, between the first control gate 212 and the oxide layer 206, and between the second control gate 214 and the oxide layer 206.

[0128] The example fin field-effect transistor 202 is configured to store a first bit value (based on the number of stored electrons) into a first side 218 of a storage gate 210 using a first control gate 212, and to store a second bit value (based on the number of stored electrons) into a second side 220 of a storage gate 210 using a second control gate 214. The example fin field-effect transistor 202 is also configured to read the first bit value (based on the number of stored electrons) from the first side 218 of the storage gate 210 using the first control gate 212, and to read the second bit value (based on the number of stored electrons) from the second side 220 of the storage gate 210 using the second control gate 214. This configuration allows each fin field-effect transistor 202 to store and access two bits of metadata, thereby increasing the density of the example NOR array 204.

[0129] As illustrated in Figures 2A, 2B, 2C, and 2D, in the example NOR array 204, four sets of fin structures 208 of four tandem fin field-effect transistors 202 are connected in series to form four rows 215. The row ends of each row 215 of the fin structures 208 are connected to different bit lines (BLs), and the source / drain connections between adjacent fin field-effect transistors 202 in a row 215 of the fin structures 208 are alternately connected to different source lines 219 or bit lines of the row 215 of the fin structures 208. In some embodiments of this disclosure, the source and drain may be used alternately, and the source and drain structures are substantially identical.

[0130] In the example NOR array 204, the first control gate 212 of the fin field-effect transistor 202 is connected to the second control gate 214 to form four double word line (WL) columns 217. Each double word line column 217 includes two distinct word lines, where the first control gate 212 of the fin field-effect transistor 202 in one column is connected to one of the word lines in that column, and the second control gate 214 of the fin field-effect transistor 202 in that column is connected to the other word line in that column. This configuration allows each fin field-effect transistor 202 to store and access two bits of metadata, thereby increasing the density of the example NOR array 204.

[0131] Figures 3A and 3B illustrate cross-sectional views of a portion of the example semiconductor device 300. For clarity, not all features of the semiconductor device 300 are shown in Figures 3A and 3B, and Figures 3A and 3B may only show a portion of the formed semiconductor structure. Figure 3A illustrates a cross-sectional view along the Y-axis, and Figure 3B illustrates a cross-sectional view along the X-axis. The example semiconductor device 300 includes a semiconductor substrate 302 and an interconnect structure 304.

[0132] Semiconductor substrate 302 may be, for example, a doped or undoped silicon semiconductor substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include semiconductor materials such as Si, Ge, Ga, Zn, In, or O. The semiconductor substrate may also include other semiconductor materials, such as compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0133] Semiconductor substrate 302 may include any number of conductive features and logic devices 306 formed in and / or on the semiconductor substrate. Conductive features may include, for example, plugs, interconnects, wires, etc. Logic devices 306 may include, for example, transistors, diodes, capacitors, and the logic devices formed thereto. For example, a transistor may be a metal oxide semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a planar field-effect transistor such as a p-channel field-effect transistor (PFET) or an n-channel field-effect transistor (NFET), a fin field-effect transistor, a gate-all-around (GAA) field-effect transistor device, or other suitable elements. In various embodiments, a transistor includes a source, a drain, a gate electrode, a gate dielectric, and a channel. The substrate 302 may further include isolation features (not shown), such as shallow trench isolation (STI), deep trench isolation (DTI), or local oxidation of silicon (LOCOS). Isolation features can define and separate multiple device elements.

[0134] Interconnect structure 304 provides routing and electrical connections between logic devices 306 formed in and / or on substrate 302. Interconnect structure 304 may include multiple metallization layers (also referred to herein as metal wiring layers), such as the first metallization layer 304-1, the second metallization layer 304-2, the third metallization layer 304-3, the fourth metallization layer 304-4, the fifth metallization layer 304-5, the sixth metallization layer 304-6, and the seventh metallization layer 304-7 shown as examples in Figures 3A and 3B.

[0135] Example: The first metallization layer 304-1, the second metallization layer 304-2, the third metallization layer 304-3, the fourth metallization layer 304-4, the fifth metallization layer 304-5, the sixth metallization layer 304-6, and the seventh metallization layer 304-7 respectively include a first inter-metal dielectric (IMD) layer 308-1, a second inter-metal dielectric layer 308-2, a third inter-metal dielectric layer 308-3, a fourth inter-metal dielectric layer 308-4, a fifth inter-metal dielectric layer 308-5, a sixth inter-metal dielectric layer 308-6, and a seventh inter-metal dielectric layer 308-7, and may include one or more conductive features. In this example, the conductive features include metal lines 310 and / or vias 312 formed in the metallization layers. The conductive features can be electrically connected to active and / or passive devices of the substrate 302 via contacts (not shown in the figures).

[0136] In several embodiments, interconnect structure 304 electrically connects the source, drain, gate electrode, gate dielectric and / or channel of transistors, as well as other features of substrate 302, to other features or logic devices 306 on substrate 302 or in interconnect structure 304.

[0137] In some embodiments, the interconnect structure 304 can be formed using damascene and / or dual damascene processes, via-first processes, or metal-first processes. In one embodiment, acceptable photolithography, deposition, and etching techniques can be used to form inter-metal dielectric layers (e.g., first inter-metal dielectric layer 308-1, second inter-metal dielectric layer 308-2, third inter-metal dielectric layer 308-3, fourth inter-metal dielectric layer 308-4, fifth inter-metal dielectric layer 308-5, sixth inter-metal dielectric layer 308-6, and seventh inter-metal dielectric layer 308-7) and openings (not shown) in the inter-metal dielectric layers. The first intermetallic dielectric layer 308-1, the second intermetallic dielectric layer 308-2, the third intermetallic dielectric layer 308-3, the fourth intermetallic dielectric layer 308-4, the fifth intermetallic dielectric layer 308-5, the sixth intermetallic dielectric layer 308-6, and the seventh intermetallic dielectric layer 308-7 may be, for example, or include oxide films, such as silicon oxide, undoped silicon glass (USG), fluorosilicate glass (FSG), boron doped silicate glass (BSG), phosphosilicate glass (PSG), boron phosphorous-doped silicate glass (BPSG), polyethylene oxide (PEOX), thermal oxides, silicon dioxide (SiO2), or other suitable dielectric materials. One or more intermetallic dielectric layers (e.g., first intermetallic dielectric layer 308-1, second intermetallic dielectric layer 308-2, third intermetallic dielectric layer 308-3, fourth intermetallic dielectric layer 308-4, fifth intermetallic dielectric layer 308-5, sixth intermetallic dielectric layer 308-6, and seventh intermetallic dielectric layer 308-7) may be formed of a low-k dielectric material, for example, a dielectric constant less than about 3.0 or less than about 2.5.

[0138] The conductive material of the metal line 310 and / or via 312 can be a conductive material formed in the opening of the intermetallic dielectric layer, such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), titanium (Ti), titanium nitride (TiN), gallium (Ga), zinc (Zn), ruthenium (Ru), molybdenum (Mo), indium tin oxide (ITO), combinations thereof, or other applicable materials. It can be formed in the opening using electrochemical plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), similar methods, or combinations thereof. After forming the conductive material, excess conductive material can be removed using, for example, a planarization process, such as chemical mechanical polishing (CMP), thereby leaving conductive features in the opening of the intermetallic dielectric layer. The process can then be repeated to form additional intermetallic dielectric layers and conductive features therein. The interconnect structure 304 in Figures 3A and 3B is merely an illustrative example. The interconnect structure 304 may include other configurations and may include one or more metal lines and inter-metal dielectric layers.

[0139] The example fin field-effect transistor 316 is formed on the oxide of the inter-metal dielectric layer 308-4 of the metallization layer 304-4, and the example fin field-effect transistor 316 includes a fin structure 318 formed above a portion of the inter-metal dielectric layer 308-4, a storage gate 320 formed in the channel region of the fin structure 318 and above a portion of the inter-metal dielectric layer 308-4, a first control gate 322 formed above the inter-metal dielectric layer 308-4 and on a first sidewall of the storage gate 320, and a second control gate 324 formed above the inter-metal dielectric layer 308-4 and on a second sidewall of the storage gate 320. The example fin field-effect transistor 316 further includes a high-dielectric-constant dielectric layer 327 (e.g., having a dielectric constant greater than about 3.0) disposed between the fin structure 318 and the storage gate 320, between the storage gate 320 and the intermetallic dielectric layer 308-4, between the first control gate 322 and the intermetallic dielectric layer 308-4, and between the second control gate 324 and the intermetallic dielectric layer 308-4.

[0140] Example fin field-effect transistor 316 is formed in the fifth metallization layer 304-5 and forms part of a NOR device, wherein the NOR device forms a reprogrammable non-volatile memory cell. In this example, the first source / drain region of the fin structure 318 can be connected to a source line or the source / drain region of another memory cell transistor via a via 325 connected to a metal line 310 in the sixth metallization layer 304-6. The second source / drain region of the fin structure 318 can be connected to a bit line or the source / drain region of another memory cell transistor via a via 326 connected to another metal line 310 in the sixth metallization layer 304-6, wherein the metal line 310 is connected to another metal line 310 in the seventh metallization layer 304-7 via a via 328. The first control gate 322 is connected to the first word line via a via 330 connected to a metal line 310 in the sixth metallization layer 304-6. The second control gate 324 is connected to the second word line via a via 332 connected to the metal line 310 in the sixth metallization layer 304-6. This configuration allows the fin field-effect transistor 316 to store and access two bits of metadata.

[0141] According to several embodiments, FIG4A illustrates a top view of a portion of an example semiconductor device 400. The example semiconductor device 400 includes a plurality of fin field-effect transistors 402 arranged as a NAND device in a multiprogrammable NAND array 404. FIG4B illustrates a cross-sectional view of the example transistors 402 of FIG4A along the X-axis, and FIG4C illustrates a cross-sectional view of the example transistors 402 of FIG4A along the Y-axis. FIG4D illustrates a schematic diagram of the example multiprogrammable NAND array 404 of FIG4A. For clarity, not all features of the semiconductor device 400 are depicted in FIG4A, 4B, 4C, and 4D, and FIG4A, 4B, 4C, and 4D may only depict a portion of the formed semiconductor structure. The example transistors 402 and the example NAND array 404 are fabricated within an upper metallization layer, for example, between a fifth and a sixth metallization layer or between a sixth and a seventh metallization layer.

[0142] As illustrated in Figures 4A, 4B, and 4C, the example fin field-effect transistor 402 is formed on an oxide layer 406 of a metallization layer. The example fin field-effect transistor 402 includes a fin structure 408 formed over a portion of the oxide layer 406, a storage gate 410 formed in a channel region of the fin structure 408 and over a portion of the oxide layer 406 to store electrons emitted by the fin structure 408, a first control gate 412 formed over the oxide layer 406 and on a first sidewall of the storage gate 410, and a second control gate 414 formed over the oxide layer 406 and on a second sidewall of the storage gate 410. The example fin field-effect transistor 402 further includes a high-dielectric-constant dielectric layer 416 disposed between the fin structure 408 and the storage gate 410, between the storage gate 410 and the oxide layer 406, between the first control gate 412 and the oxide layer 406, and between the second control gate 414 and the oxide layer 406.

[0143] The example fin field-effect transistor 402 is configured to store a first bit value (based on the number of stored electrons) into a first side 418 of the storage gate 410 using a first control gate 412, and to store a second bit value (based on the number of stored electrons) into a second side 420 of the storage gate 410 using a second control gate 414. The example fin field-effect transistor 402 is also configured to read the first bit value (based on the number of stored electrons) from the first side 418 of the storage gate 410 using the first control gate 412, and to read the second bit value (based on the number of stored electrons) from the second side 420 of the storage gate 410 using the second control gate 414. This configuration allows each fin field-effect transistor 402 to store and access two bits of metadata, thereby increasing the density of the example NOR array 404.

[0144] As illustrated in Figures 4A, 4B, 4C, and 4D, in the example NOR array 404, two sets of fin structures 408 of tandem fin field-effect transistors 402 are connected in series to form two rows 415. The row ends of each row 415 of the fin structures 408 are connected to different bit lines, and the other row end is connected to a ground select transistor 419. The source / drain of adjacent fin field-effect transistors 402 in one row 415 of the fin structures 408 is connected to each other. A bit line select transistor 421 (e.g., formed between metal wiring layers or on a substrate) is connected between a bit line and a first of a plurality of multiple programmable non-volatile memory cells (e.g., fin field-effect transistors 402), and a ground select transistor 419 (e.g., formed between metal wiring layers or on a substrate) is connected between a ground source and a second of a plurality of multiple programmable non-volatile memory cells (e.g., fin field-effect transistors 402).

[0145] In the example NAND array 404, the first control gate 412 of the fin field-effect transistor 402 is connected to the second control gate 414 to form a dual-word line array 417. Each dual-word line array 417 includes two distinct word lines, where the first control gate 412 of the fin field-effect transistor 402 in one column is connected to one of the word lines in that column, and the second control gate 414 of the fin field-effect transistor 402 in that column is connected to the other word line in that column. This configuration allows each fin field-effect transistor 402 to store and access two bits of metadata, thereby increasing the density of the example NAND array 404.

[0146] Figures 5A and 5B illustrate cross-sectional views of a portion of an example semiconductor device 500. For clarity, not all features of the semiconductor device 500 are shown in Figures 5A and 5B, and Figures 5A and 5B may only show a portion of the formed semiconductor structure. Figure 5A illustrates a cross-sectional view along the Y-axis, and Figure 5B illustrates a cross-sectional view along the X-axis. The example semiconductor device 500 includes a semiconductor substrate 502 and an interconnect structure 504.

[0147] Semiconductor substrate 502 may be, for example, a doped or undoped silicon semiconductor substrate, or an active layer of a semiconductor-on-insulator substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0148] Semiconductor substrate 502 may include any number of conductive features and logic devices 506 formed in and / or on the semiconductor substrate. Conductive features may include, for example, plugs, interconnects, wires, etc. Logic devices 506 may include, for example, transistors, diodes, capacitors, and the logic devices formed thereto. For example, a transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal-oxide-semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a flat field-effect transistor such as a p-channel MOSFET or an n-channel MOSFET, a fin MOSFET, a gate-all-around MOSFET device, or other suitable elements. In various embodiments, a transistor includes a source, a drain, a gate electrode, a gate dielectric, and a channel. Substrate 502 may further include isolation features (not shown), such as shallow trench isolation features, deep trench isolation features, or localized silicon oxide features. Isolation features can define and separate multiple device elements.

[0149] Interconnect structure 504 provides wiring and electrical connections between logic devices 506 formed in and / or on substrate 502. Interconnect structure 504 may include multiple metallization layers (also referred to herein as metal wiring layers), such as the first metallization layer 504-1, the second metallization layer 504-2, the third metallization layer 504-3, the fourth metallization layer 504-4, the fifth metallization layer 504-5, the sixth metallization layer 504-6, and the seventh metallization layer 504-7 shown as examples in Figures 5A and 5B.

[0150] Example: The first metallization layer 504-1, the second metallization layer 504-2, the third metallization layer 504-3, the fourth metallization layer 504-4, the fifth metallization layer 504-5, the sixth metallization layer 504-6, and the seventh metallization layer 504-7 respectively include a first inter-metal dielectric layer 508-1, a second inter-metal dielectric layer 508-2, a third inter-metal dielectric layer 508-3, a fourth inter-metal dielectric layer 508-4, a fifth inter-metal dielectric layer 508-5, a sixth inter-metal dielectric layer 508-6, and a seventh inter-metal dielectric layer 508-7, and may include one or more conductive features. In this example, the conductive features include metal lines 510 and / or vias 512 formed in the metallization layers. The conductive features can be electrically connected to active and / or passive devices of the substrate 502 via contacts (not shown in the figures).

[0151] In several embodiments, interconnect structure 504 electrically connects the source, drain, gate electrode, gate dielectric and / or channel of transistors, as well as other features of substrate 502, to other features or logic devices 506 on substrate 502 or in interconnect structure 504.

[0152] In some embodiments, the interconnect structure 504 may be formed using single damascene and / or dual damascene processes, via-first processes, or metal-first processes. In one embodiment, acceptable photolithography, deposition, and etching techniques may be used to form inter-metal dielectric layers (e.g., first inter-metal dielectric layer 508-1, second inter-metal dielectric layer 508-2, third inter-metal dielectric layer 508-3, fourth inter-metal dielectric layer 508-4, fifth inter-metal dielectric layer 508-5, sixth inter-metal dielectric layer 508-6, and seventh inter-metal dielectric layer 508-7) and openings (not shown) in the inter-metal dielectric layers. The first intermetallic dielectric layer 508-1, the second intermetallic dielectric layer 508-2, the third intermetallic dielectric layer 508-3, the fourth intermetallic dielectric layer 508-4, the fifth intermetallic dielectric layer 508-5, the sixth intermetallic dielectric layer 508-6, and the seventh intermetallic dielectric layer 508-7 may be, for example, oxide films, such as silicon oxide, undoped silicon glass, fluorosilicate glass, boron-doped silicate glass, phosphosilicate glass, boron-phosphorus-doped silicate glass, polyethylene oxide, thermal oxides, silicon dioxide, or other suitable dielectric materials. One or more intermetallic dielectric layers (e.g., first intermetallic dielectric layer 508-1, second intermetallic dielectric layer 508-2, third intermetallic dielectric layer 508-3, fourth intermetallic dielectric layer 508-4, fifth intermetallic dielectric layer 508-5, sixth intermetallic dielectric layer 508-6 and seventh intermetallic dielectric layer 508-7) may be formed of a low dielectric constant material, for example, a dielectric constant less than about 3.0 or less than about 2.5.

[0153] The conductive material of the metal lines 510 and / or vias 512 can be a conductive material formed in the openings of the intermetallic dielectric layer, such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), titanium (Ti), titanium nitride (TiN), gallium (Ga), zinc (Zn), ruthenium (Ru), molybdenum (Mo), indium tin oxide (ITO), combinations thereof, or other applicable materials. It can be formed in the openings using electrochemical plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, similar processes, or combinations thereof. After forming the conductive material, excess conductive material can be removed using, for example, a planarization process, such as chemical mechanical polishing, thereby leaving conductive features in the openings of the intermetallic dielectric layer. The process can then be repeated to form additional intermetallic dielectric layers and conductive features therein. The interconnect structure 504 in Figures 5A and 5B is merely an illustrative example. The interconnect structure 504 can include other configurations and can include one or more metal lines and intermetallic dielectric layers.

[0154] The example fin field-effect transistor 516 is formed on the oxide of the inter-metal dielectric layer 508-4 of the metallization layer 504-4, and the example fin field-effect transistor 516 includes a fin structure 518 formed on a portion of the inter-metal dielectric layer 508-4, a storage gate 520 formed in the channel region of the fin structure 518 and a portion of the inter-metal dielectric layer 508-4, a first control gate 522 formed on the inter-metal dielectric layer 508-4 and on a first sidewall of the storage gate 520, and a second control gate 524 formed on the inter-metal dielectric layer 508-4 and on a second sidewall of the storage gate 520. The example fin field-effect transistor 516 further includes a high-dielectric-constant dielectric layer 527 (e.g., having a dielectric constant greater than about 3.0) disposed between the fin structure 518 and the storage gate 520, between the storage gate 520 and the intermetallic dielectric layer 508-4, between the first control gate 522 and the intermetallic dielectric layer 508-4, and between the second control gate 524 and the intermetallic dielectric layer 508-4.

[0155] Example fin field-effect transistor 516 is formed in the fifth metallization layer 504-5 and forms part of a NAND device, wherein the NAND device forms a multiprogrammable non-volatile memory cell. In this example, the first source / drain region of the fin structure 518 can be connected to the source / drain region of a bit line select transistor or the source / drain region of another memory cell transistor via a via 525 connected to a metal line 510 in the sixth metallization layer 504-6. The second source / drain region of the fin structure 518 can be connected to the source / drain region of a ground select transistor or the source / drain region of another memory cell transistor via a via 526 connected to another metal line 510 in the sixth metallization layer 504-6, wherein the metal line 510 is connected to another metal line 510 in the seventh metallization layer 504-7 via a via 528. The first control gate 522 is connected to the first word line via a via 530 connected to a metal line 510 in the sixth metallization layer 504-6. The second control gate 524 is connected to the second word line via a via 532 connected to the metal line 510 in the sixth metallization layer 504-6. This configuration allows the fin field-effect transistor 516 to store and access two bits of metadata. In several embodiments, at least one of the first control gate 522, the second control gate 524, and the source / drain regions of the fin structure 518 is connected to the logic device 506.

[0156] Figure 6 illustrates a flowchart of an example method 600 for manufacturing a semiconductor device. Figures 2B-2C and 3A-3B are cross-referenced to provide an example embodiment following the completion of multiple blocks of the example method 600.

[0157] Example method 600 includes providing a substrate at block 602, wherein the substrate has logic devices formed on the substrate and interconnect structures formed above the substrate. In several embodiments, the interconnect structures include a plurality of metal wiring layers disposed above the substrate, wherein the metal wirings are connected to the logic devices. In several embodiments, the plurality of metal wiring layers include an upper metal wiring layer, wherein the metal wiring layers have metal lines, vias, and oxide layers. Referring to Figures 2B-2C and Figures 3A-3B, in an example embodiment of block 602, a substrate 302 is provided having logic devices 306 formed on the substrate and interconnect structures 304, wherein the interconnect structures 304 have a plurality of metal wiring layers (e.g., a first inter-metal dielectric layer 308-1, a second inter-metal dielectric layer 308-2, a third inter-metal dielectric layer 308-3, a fourth inter-metal dielectric layer 308-4, a fifth inter-metal dielectric layer 308-5, a sixth inter-metal dielectric layer 308-6, and a seventh inter-metal dielectric layer 308-7) disposed above the substrate. The metal wiring layers (e.g., first inter-metal dielectric layer 308-1, second inter-metal dielectric layer 308-2, third inter-metal dielectric layer 308-3, fourth inter-metal dielectric layer 308-4, fifth inter-metal dielectric layer 308-5, sixth inter-metal dielectric layer 308-6, and seventh inter-metal dielectric layer 308-7) include metal lines 310 and vias 312 connected to the logic device 306. The plurality of metal wiring layers (e.g., first inter-metal dielectric layer 308-1, second inter-metal dielectric layer 308-2, third inter-metal dielectric layer 308-3, fourth inter-metal dielectric layer 308-4, fifth inter-metal dielectric layer 308-5, sixth inter-metal dielectric layer 308-6, and seventh inter-metal dielectric layer 308-7) include an upper metal wiring layer (metallization layer 304-4) having metal lines 310, vias 312, and the fourth inter-metal dielectric layer 308-4. In several embodiments, the logic device 306 includes a transistor device, such as a planar field-effect transistor, a fin field-effect transistor, or a gate-all-around field-effect transistor. In several embodiments, the logic device includes a gate dielectric (e.g., HfO2, SiO2, HfO, La, SiON, SiCON, Zn, Zr, etc.), a gate electrode (e.g., polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C, etc.), a source electrode and a drain electrode (wherein the source / drain includes Si, Ge, C, P, B, etc.), and a nanosheet channel (e.g., Si). In several embodiments, the substrate includes Si, Ge, Ga, Zn, In, or O. In several embodiments, the substrate includes a logic device isolation structure. In several embodiments, the logic device isolation structure in the substrate includes localized silicon oxide, shallow trench isolation, and deep trench isolation.

[0158] In block 604, example method 600 includes planarizing the oxide layer of the upper metal wiring layer of the interconnect structure. In several embodiments, the oxide layer is planarized using a chemical mechanical polishing operation. Referring to Figures 2B-2C and 3A-3B, in an example embodiment of block 604, oxide layer 206 / fourth intermetallic dielectric layer 308-4 is planarized. In some embodiments, the oxide layer may be referred to as an interlayer dielectric (ILD). In some embodiments, the material of the oxide layer includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or a low dielectric constant material. The dielectric layer can be formed using any acceptable deposition process, such as spin coating, chemical vapor deposition, or other suitable methods.

[0159] In block 606, example method 600 includes forming a fin structure over a portion of an oxide layer. In several embodiments, forming the fin structure includes depositing an indium gallium zinc oxide (IGZO) layer. IGZO is a semiconductor material composed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). By using IGZO, fins can be formed at temperatures below 300°C. In several embodiments, IGZO is deposited using atomic absorption spectrometry (AES) or physical vapor deposition (PVD). In several embodiments, after depositing IGZO, the deposited IGZO forms the fin structure. In several embodiments, the fin structure is formed using photolithography, patterning, and etching techniques to cut and etch the IGZO layer into the fin structure. Referring to Figures 2B-2C and 3A-3B, in an example embodiment of block 606, fin structure 208 / fin structure 318 is formed over a portion of oxide layer 206 / fourth intermetallic dielectric layer 308-4.

[0160] In block 608, example method 600 includes forming a high-dielectric-constant dielectric layer over the oxide layer and fin structure. In various embodiments, the high-dielectric-constant dielectric layer is formed over the oxide layer and fin structure using a deposition process such as atomic layer deposition. In some embodiments, the high-dielectric-constant dielectric includes hafnium oxide (HfO). x In some embodiments, the high dielectric constant dielectric includes zirconium oxide (ZrO). x Referring to Figures 2B to 2C and Figures 3A to 3B, in an example embodiment of block 608, a high dielectric constant dielectric layer 216 / high dielectric constant dielectric layer 327 is formed over oxide layer 206 / intermetallic dielectric layer 308-4 and fin structure 208 / fin structure 318.

[0161] In block 610, example method 600 includes forming a storage gate over the channel region of the fin structure. In several embodiments, the storage gate is a nitride storage gate formed of silicon nitride (SiN) or titanium nitride (TiN). In several embodiments, the storage gate is formed using a deposition process, such as chemical vapor deposition or physical vapor deposition. Referring to Figures 2B-2C and Figures 3A-3B, in an example embodiment of block 610, storage gate 210 / storage gate 320 is formed over the channel region of fin structure 208 / fin structure 318.

[0162] In block 612, example method 600 includes forming a first control gate on a first side of the storage gate above the oxide layer, and forming a second control gate on a second side of the storage gate above the oxide layer. In various embodiments, forming the first and second control gates includes depositing a control gate material layer on and around the storage gate using a suitable deposition technique, and planarizing the control gate material layer using, for example, chemical mechanical polishing, to separate the first and second control gates. In various embodiments, the first and second control gates are formed of nitrides, such as titanium nitride (TiN) or tantalum nitride (TaN). Referring to Figures 2B to 2C and Figures 3A to 3B, in an example embodiment of block 612, a first control gate 212 / first control gate 322 is formed on a first side of the storage gate 210 / storage gate 320 above the oxide layer 206 / fourth intermetallic dielectric layer 308-4, and a second control gate 214 / second control gate 324 is formed on a second side of the storage gate 210 / storage gate 320 above the oxide layer 206 / fourth intermetallic dielectric layer 308-4.

[0163] In block 614, example method 600 includes connecting a first control gate to a first word line using vias and metal lines, and connecting a second control gate to a second word line. In various embodiments, connecting the first control gate to the first word line and connecting the second control gate to the second word line includes: depositing an IMD oxide layer over the fin structure, the first control gate, the second control gate, and the storage gate; patterning and etching the IMD oxide layer to cut openings for vias and metal lines to connect the first control gate to the first word line and the second control gate to the second word line; and depositing a metal layer for the vias and metal lines. In some embodiments, the material of the vias and metal lines may include metals such as copper, titanium, tungsten, aluminum, or combinations thereof. The vias and metal lines may be formed using chemical vapor deposition or electroplating. Referring to FIG3A, in an example embodiment of block 614, a first control gate 322 is connected to the first word line via a via 330 through a metal line 310, and a second control gate 324 is connected to the second word line via a via 332 through a metal line 310.

[0164] In block 616, example method 600 includes connecting at least one of a first control gate, a second control gate, a first source / drain region of a fin structure, and a second source / drain region of a fin structure to a logic device. Referring to FIG3B, in an example embodiment of block 616, the first source / drain region of fin structure 318 is connected to logic device 306 via via 325 through metal line 310 and via 312, and the second source / drain region of fin structure 318 is connected to logic device 306 via via 326 through metal line 310 and via 312. Referring to FIG3A, in an example embodiment of block 616, the first control gate 322 is connected to logic device 306 via via 330 through metal line 310 and via 312, and the second control gate 324 is connected to logic device 306 via via 332 through metal line 310 and via 312.

[0165] Method 600 may include further processing steps at block 618 to complete an integrated circuit. Further processing steps may include forming additional interconnects between multiple elements of a semiconductor device. In several embodiments, method 600 may include forming connections to form a NOR device. In several embodiments, method 600 may include forming connections to form a NAND device. In several embodiments, method 600 may include connecting a first source / drain region of a fin structure to a source line, connecting a second source / drain region of a fin structure to a bit line, and connecting a control gate to a word line. In several embodiments, method 600 may include connecting a first source / drain region of a fin structure to a source / drain region of a first series transistor, connecting a second source / drain region of a fin structure to a source / drain region of a second series transistor, and connecting a control gate to a word line.

[0166] In some embodiments, the technology described herein relates to a semiconductor device. The semiconductor device includes a substrate having logic devices formed thereon, a plurality of metal wiring layers disposed above the substrate and having metal wiring connected to the logic devices, and a plurality of multiple programmable non-volatile memory cells formed between the plurality of metal wiring layers. The memory cells include fin field-effect transistors, wherein the fin field-effect transistors have a fin structure, a storage gate disposed around a channel region of the fin structure to store electrons emitted by the fin structure, a first control gate formed around a first sidewall of the storage gate and connected to a first word line, and a second control gate formed around a second sidewall of the storage gate and connected to a second word line.

[0167] In some cases, the technology described herein relates to a device in which the memory cell includes a NOR device.

[0168] In some embodiments, the technology described herein relates to a device in which a first source / drain region of a fin structure is connected to a source line, and a second source / drain region of a fin structure is connected to a bit line.

[0169] In some cases, the technology described herein relates to devices in which memory cells include NAND devices.

[0170] In some embodiments, the technology described herein relates to a device in which a first source / drain region of a fin structure is connected to a source / drain region of a first series transistor, and a second source / drain region of a fin structure is connected to a source / drain region of a second series transistor.

[0171] In some cases, the technology described herein relates to a device in which the fin structure is formed of indium gallium zinc oxide.

[0172] In some cases, the technology described herein relates to a device in which the storage gate is formed of silicon nitride (SiN) or titanium nitride (TiN), and the control gate is formed of titanium nitride (TiN) or tantalum nitride (TaN).

[0173] In some embodiments, the technology described herein relates to a device that further includes a high-dielectric-constant dielectric layer formed between a storage gate and a fin structure, wherein the high-dielectric-constant dielectric layer comprises hafnium oxide (HfO). x ) or zirconium oxide (ZrO) x ).

[0174] In some embodiments, the technology described herein relates to a semiconductor manufacturing method. The method includes providing a substrate having logic devices formed thereon and a plurality of metal wiring layers disposed above the logic devices and the substrate and having metal wiring connected to the logic devices, wherein the metal wiring layers include an upper metal wiring layer having metal lines, vias, and a planar oxide layer; forming a fin structure in indium gallium zinc oxide over the oxide layer in the upper metal wiring layer; forming a high-dielectric-constant dielectric layer over the oxide layer and the fin structure; forming a memory gate over a channel region of the fin structure; forming a first control gate on a first side of the memory gate; forming a second control gate on a second side of the memory gate; connecting the first control gate to a first word line; connecting the second control gate to a second word line; and connecting at least one of the first control gate, the second control gate, and the source / drain regions of the fin structure to the logic devices using vias and metal lines.

[0175] In some embodiments, the techniques described herein are methods in which forming a fin structure with indium gallium zinc oxide over an oxide layer in an upper metal wiring layer includes depositing an indium gallium zinc oxide layer using atomic layer deposition or physical vapor deposition, and forming the deposited indium gallium zinc oxide layer into a fin structure using patterning and etching techniques.

[0176] In some cases, the techniques described herein are methods in which forming a high-dielectric-constant dielectric layer over an oxide layer and a fin structure includes depositing a high-dielectric-constant dielectric layer using atomic layer deposition, and wherein the high-dielectric-constant dielectric layer includes hafnium oxide (HfO). x ) or zirconium oxide (ZrO) x ).

[0177] In some cases, the techniques described herein are methods in which forming a memory gate includes forming a nitride memory gate using silicon nitride (SiN) or titanium nitride (TiN) by chemical vapor deposition or physical vapor deposition.

[0178] In some embodiments, the techniques described herein are methods in which forming a first control gate and forming a second control gate include depositing a control gate material layer on and around the storage gate in the form of titanium nitride (TiN) or tantalum nitride (TaN), and planarizing the control gate material layer using chemical mechanical polishing to separate the first control gate from the second control gate.

[0179] In some embodiments, the techniques described herein are methods that further include connecting a first source / drain region of the fin structure to a source line and connecting a second source / drain region of the fin structure to a bit line.

[0180] In some embodiments, the techniques described herein relate to a method that further includes connecting a first source / drain region of a fin structure to a source / drain region of a first series transistor, and connecting a second source / drain region of the fin structure to a source / drain region of a second series transistor.

[0181] In some embodiments, the technology described herein relates to a memory device. The memory device includes a logic device, a plurality of metal wiring layers having metal wiring connected to the logic device, and a multiple-programmable non-volatile memory cell formed in a back-end process and located between the plurality of metal wiring layers. The memory cell includes a fin field-effect transistor, wherein the fin field-effect transistor has an indium gallium zinc oxide fin, a storage gate disposed around a channel region of the indium gallium zinc oxide fin, a first control gate formed around a first sidewall of the storage gate and connected to a first word line, and a second control gate formed around a second sidewall of the storage gate and connected to a second word line.

[0182] In some cases, the technology described herein relates to memory devices in which memory cells are connected to multiple other memory cells to form a NOR device.

[0183] In some cases, the technology described herein relates to memory devices in which memory cells are connected to multiple other memory cells to form a NAND device.

[0184] In some cases, the technology described herein relates to a memory device, which further includes a high-dielectric-constant dielectric formed between a storage gate and an indium gallium zinc oxide fin.

[0185] In some cases, the techniques described herein relate to memory devices, where the logic devices include flat field-effect transistors, fin field-effect transistors, or gate-all-around field-effect transistor devices.

[0186] In some configurations, a reprogrammable nonvolatile memory cell is one of multiple memory cells in a NOR device or a NAND device.

[0187] In some embodiments, the technology described herein relates to a semiconductor device. The semiconductor device includes a substrate having logic devices formed thereon, and a plurality of metal wiring layers disposed above the logic devices and the substrate and having metal wiring connected to the logic devices. The metal wiring layers include an upper metal wiring layer having a plurality of metal lines, a plurality of vias, and a flat oxide layer. The semiconductor device includes a fin structure above the oxide layer in the upper metal wiring layer, a high-dielectric-constant dielectric layer above the oxide layer and the fin structure, a memory gate above a channel region of the fin structure, a first control gate located on a first side of the memory gate and connected to a first word line, and a second control gate located on a second side of the memory gate and connected to a second word line. The vias and metal lines in the upper metal wiring layer connect at least one of the first control gate, the second control gate, and the source / drain regions of the fin structure to the logic device.

[0188] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a logic device formed on the substrate; Multiple metal wiring layers are disposed above the substrate and have metal wiring connected to the logic device; and multiple reprogrammable non-volatile memory cells are formed between the multiple metal wiring layers. The multiple reprogrammable non-volatile memory cells include a fin field-effect transistor having a fin structure, a storage gate disposed around a channel region of the fin structure, a first control gate formed around a first sidewall of the storage gate and connected to a first word line, and a second control gate formed around a second sidewall of the storage gate and connected to a second word line.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of reprogrammable nonvolatile memory cells include a NOR device.

3. The semiconductor device as claimed in claim 1, characterized in that, The fin structure has a first source / drain region connected to a source line, and a second source / drain region connected to a bit line.

4. The semiconductor device as claimed in claim 1, characterized in that, The plurality of reprogrammable nonvolatile memory cells include a NAND device.

5. The semiconductor device as claimed in claim 1, characterized in that, A first source / drain region of the fin structure is connected to a source / drain region of a first series transistor, and a second source / drain region of the fin structure is connected to a source / drain region of a second series transistor.

6. A memory device, characterized in that, include: A logic device; Multiple metal wiring layers, with metal wiring connected to the logic device; And a reprogrammable non-volatile memory cell located between the plurality of metal wiring layers, the reprogrammable non-volatile memory cell including a fin field-effect transistor having an indium gallium zinc oxide fin, a storage gate disposed around a channel region of the indium gallium zinc oxide fin, a first control gate formed around a first sidewall of the storage gate and connected to a first word line, and a second control gate formed around a second sidewall of the storage gate and connected to a second word line.

7. The memory device as claimed in claim 6, characterized in that, It further includes a high dielectric constant dielectric material formed between the storage gate and the indium gallium zinc oxide fin.

8. The memory device as claimed in claim 6, characterized in that, The logic device includes a flat field-effect transistor, a fin field-effect transistor, or a gate-all-around field-effect transistor.

9. The memory device as claimed in claim 6, characterized in that, The reprogrammable nonvolatile memory cell is one of a plurality of memory cells in a NOR device or a AND device.

10. A semiconductor device, characterized in that, include: A substrate having a logic device formed on the substrate; Multiple metal wiring layers are disposed above the logic device and the substrate and have metal wiring connected to the logic device, wherein the multiple metal wiring layers include an upper metal wiring layer having multiple metal lines, multiple vias and a flat oxide layer; a fin structure located above the oxide layer in the upper metal wiring layer; and a high dielectric constant dielectric layer located above the oxide layer and the fin structure. A memory gate is located above the channel region of the fin structure; a first control gate is located on a first side of the memory gate and connected to a first word line; And a second control gate, located on a second side of the memory gate and connected to a second word line, wherein the plurality of vias and the plurality of metal lines in the upper metal wiring layer connect at least one of the first control gate, the second control gate and a source / drain region of the fin structure to the logic device.

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