Processor mainboard and computer equipment

Abstract

The embodiment of the utility model provides a processor mainboard and computer equipment, the processor mainboard comprises a plurality of calculation acceleration entities, the calculation acceleration entities are standardized entity units at least used for integrating calculation units, and each calculation acceleration entity comprises a calculation unit and a first connector; each computing unit comprises a plurality of first ports, the first ports are respectively connected to a bottom plate of the processor mainboard through the first connectors, and the first ports support a memory interconnection bus between the computing units; the backplane comprises a plurality of first interconnection channels, one first interconnection channel is in butt joint with one first port of each of the two computing acceleration entities, and the plurality of first interconnection channels cover interconnection among the plurality of computing acceleration entities. The processor mainboard provided by the embodiment of the utility model can provide a basis for data transmission among a plurality of computing units.

Description

Technical Field

[0001] This application relates to the field of processor technology, specifically to a processor motherboard and a computer device. Background Technology

[0002] The processor motherboard is the core hardware platform of a computer system, primarily connecting the computer system's computing units, processors, and other IP (Intellectual Property) components. Furthermore, the processor motherboard also connects the computer system's memory, storage bus, various other controllers, and expansion cards. A computing unit is an IP component designed to perform specific computational tasks within the computer system. For example, taking a deep learning computing unit as an example, a deep learning computing unit is an IP component in the computer system specifically designed to perform deep learning and machine learning tasks.

[0003] With the development of integrated circuit design technology, the number of IP components on processor motherboards is increasing. Consequently, processor motherboards can have multiple computing units. These computing units need to process large amounts of data and perform high-speed data exchange. Therefore, efficient interconnection between multiple computing units and with other components of the processor motherboard is particularly important. Against this backdrop, how to meet the interconnection requirements between multiple computing units in the design of processor motherboards has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] In view of this, embodiments of this application provide a processor motherboard and a computer device to meet the interconnection requirements between multiple computing units and to provide a basis for data transmission between multiple computing units.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a processor motherboard, comprising:

[0007] Multiple computing acceleration entities, each being a standardized entity unit for integrating computing units, each computing acceleration entity including a computing unit and a first connector; each computing unit including multiple first ports, each first port being connected to the backplane of the processor motherboard via the first connector, the first ports supporting a memory interconnect bus between computing units;

[0008] The base plate includes multiple first interconnect channels, each first interconnect channel interfacing with a first port of each of two compute acceleration entities, and the multiple first interconnect channels cover the interconnection between the multiple compute acceleration entities.

[0009] Optionally, the two computing acceleration entities are connected via a single first interconnect channel or a combination of first interconnect channels;

[0010] The single first interconnect channel is a single first interconnect channel between two computing acceleration entities;

[0011] The combined first interconnect channel includes at least two first interconnect channels between two computing acceleration entities.

[0012] Optionally, the number of the plurality of first ports is greater than the number of the plurality of computing acceleration entities; a first interconnect channel configured in a computing acceleration entity includes:

[0013] A single first interconnect channel and multiple sets of combined first interconnect channels, wherein the number of sets of combined first interconnect channels is less than the number of the plurality of computing acceleration entities.

[0014] Optionally, the plurality of computing acceleration entities are four computing acceleration entities; the first port is a high-speed Serdes port, and the plurality of first ports include: a zeroth high-speed Serdes port, a first high-speed Serdes port, a second high-speed Serdes port, a third high-speed Serdes port, a fourth high-speed Serdes port, a fifth high-speed Serdes port, and a sixth high-speed Serdes port.

[0015] A computing acceleration entity is configured with multiple sets of combined first interconnect channels, including: a first set of combined first interconnect channels and a second set of combined first interconnect channels, wherein the computing acceleration entity connects to two different computing acceleration entities through the first set of combined first interconnect channels and the second set of combined first interconnect channels respectively.

[0016] The first group of first interconnect channels includes three first interconnect channels, which are respectively connected to the zero high-speed Serdes port, the first high-speed Serdes port, the second high-speed Serdes port of the computing acceleration entity, and the fifth high-speed Serdes port, the fourth high-speed Serdes port, and the third high-speed Serdes port of the connected computing acceleration entity.

[0017] The second group of combined first interconnect channels includes three first interconnect channels, which respectively connect to the third high-speed Serdes port, the fourth high-speed Serdes port, and the fifth high-speed Serdes port of the computing acceleration entity, as well as the second high-speed Serdes port, the first high-speed Serdes port, and the zeroth high-speed Serdes port of the connected computing acceleration entity.

[0018] The single first interconnect channel configured in the one computing acceleration entity connects to other computing acceleration entities that are different from the two different computing acceleration entities, and the single first interconnect channel interfaces with the sixth high-speed Serdes port of the different computing acceleration entities.

[0019] Optionally, the number of the plurality of first ports is less than the number of the plurality of computing acceleration entities, and the number of the plurality of first ports is one less than the number of the plurality of computing acceleration entities; the plurality of first interconnect channels are all single first interconnect channels.

[0020] Optionally, the plurality of computing acceleration entities are eight computing acceleration entities; the first port is a high-speed Serdes port, and the plurality of first ports include: a zeroth high-speed Serdes port, a first high-speed Serdes port, a second high-speed Serdes port, a third high-speed Serdes port, a fourth high-speed Serdes port, a fifth high-speed Serdes port, and a sixth high-speed Serdes port.

[0021] One computing acceleration entity is connected one-to-one with the other seven computing acceleration entities through the single first interconnect channel.

[0022] Optionally, the computing unit further includes a second port, which is connected to the backplane of the processor motherboard via the first connector, and the second port supports a wide area function link bus between computing units;

[0023] The base plate also includes multiple second interconnect channels, one of which connects to the second port of each of the two computing acceleration entities.

[0024] Optionally, the plurality of computing acceleration entities are arranged in a row, and the second ports of the computing acceleration entities are connected sequentially through the second interconnection channel, with the second ports of the first and last computing acceleration entities connected through the second interconnection channel.

[0025] Optionally, the computing unit further includes a third port and a fourth port; the third port supports a PCIe bus and a memory interconnect bus between the computing unit; the fourth port supports a PCIe bus.

[0026] The processor motherboard also includes: a PCIe retimer and a second connector;

[0027] The third port is connected to the backplane of the processor motherboard via the first connector, and is connected to the PCIe retimer via the PCIe retimer connection channel of the backplane; the PCIe retimer is connected to other motherboards via the second connector.

[0028] Secondly, embodiments of this application provide a computer device including a processor motherboard as described in the first aspect above.

[0029] This application provides a processor motherboard and a computer device. The processor motherboard includes: a plurality of computing acceleration entities, each computing acceleration entity being a standardized entity unit for integrating computing units, each computing acceleration entity including a computing unit and a first connector; each computing unit including a plurality of first ports, each first port being connected to the backplane of the processor motherboard via the first connector, the first port supporting a memory interconnect bus between computing units; the backplane including a plurality of first interconnect channels, each first interconnect channel connecting to one first port of each of two computing acceleration entities, and the plurality of first interconnect channels covering the interconnection between the plurality of computing acceleration entities.

[0030] As can be seen, in this embodiment, the computing unit is integrated into a standardized computing acceleration entity. The computing acceleration entity is provided with a first connector, so that multiple first ports of the computing unit integrated into the computing acceleration entity can be connected to the backplane of the processor motherboard through the first connector. The first port supports a memory interconnect bus between computing units. Furthermore, the backplane of the processor motherboard is provided with multiple first interconnect channels. Each first interconnect channel connects to one first port of each of the two computing acceleration entities, and the multiple first interconnect channels cover the interconnection between multiple computing acceleration entities. Thus, when the computing unit is integrated into the computing acceleration entity, the interconnection between multiple computing units can be realized, providing a basis for data transmission between multiple computing units. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of an optional structure of a processor motherboard provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of another optional structure of a processor motherboard provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the interconnection structure of computing units in a processor motherboard provided in an embodiment of this application;

[0035] Figure 4This is a schematic diagram of the interconnection structure of computing units in another processor motherboard provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of an optional structure for connecting the computing acceleration entity provided in this application embodiment to other motherboards. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In computer systems, computational acceleration entities, as standardized unit entities, can be used to integrate computational units (such as deep learning units) to provide high-performance computational acceleration. For example, a computational acceleration entity can integrate one or more computational units (such as deep learning units), allowing the integrated computational units (such as deep learning units) to manage the data flow and processing logic of computational tasks such as deep learning and machine learning, thereby optimizing the execution of computational tasks. For ease of understanding, refer to [reference needed]. Figure 1 The schematic diagram shown in this application embodiment illustrates an optional structure of a processor motherboard. As can be seen, the processor motherboard has multiple computing acceleration entities, each of which integrates a computing unit.

[0039] It should be noted that a computing acceleration entity is a standardized entity unit used to integrate computing units; more specifically, it is a standardized hardware unit designed to integrate computing units such as deep learning units. Taking the Open Compute Project (OCP) as an example, a computing acceleration entity can be called an OAM (OCPAccelerator Module), a standard hardware module designed to accelerate computing tasks such as artificial intelligence and machine learning. Correspondingly, an OAM can integrate deep learning units to perform computing tasks such as artificial intelligence and machine learning; an OAM integrating deep learning units can be installed on the processor motherboard and then deployed in servers in a data center to perform intensive computing tasks.

[0040] When computing units (e.g., deep computing units) are integrated into computing acceleration entities, there is an interconnection requirement between the computing units integrated into multiple computing acceleration entities (e.g., between deep computing units). Therefore, it is particularly important to provide a processor motherboard that meets the interconnection requirements between multiple computing units and provides a foundation for data transmission between multiple computing units.

[0041] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] refer to Figure 2 , Figure 2 This is a schematic diagram of another optional structure of a processor motherboard provided in an embodiment of this application. For example... Figure 2 As shown, the processor motherboard provided in this application embodiment may include:

[0043] Multiple computation acceleration entities (such as) Figure 2 As shown in the diagram (computation acceleration entities 0 to n), each computation acceleration entity is a standardized entity unit for integrating computing units. Each computation acceleration entity may include computing units and first connectors. For example, computation acceleration entity 0 integrates computing unit 10 and first connector 20, and computation acceleration entity n integrates computing unit 1n and first connector 2n. Each computing unit may include multiple first ports, which are respectively connected to the backplane 101 of the processor motherboard via the first connectors. The first ports support memory interconnect buses between computing units.

[0044] It should be noted that the computing unit is an IP component designed to perform specific computing tasks; specifically, under OAM, it is an IP component designed by the deep computing unit to perform artificial intelligence and deep learning tasks.

[0045] The backplane of the processor motherboard is a circuit board used by the processor motherboard to provide connections and communication between components, and plays the role of connecting various components of the processor motherboard. In this embodiment of the application, the backplane 101 of the processor motherboard includes a plurality of first interconnect channels, each of which connects to a first port of each of two computing acceleration entities, and the plurality of first interconnect channels cover the interconnection between the plurality of computing acceleration entities.

[0046] Specifically, the connection channel between the first ports of different computing acceleration entities is called the first interconnect channel. That is, the first interconnect channel is a channel designed by the backplane to connect and manage the data flow of the first port. The first interconnect channel is connected to the first port of the computing unit integrated by the computing acceleration entity on the processor motherboard, and each first interconnect channel connects the respective first ports of two computing acceleration entities to allow point-to-point communication between the computing units of the two computing acceleration entities, thereby reducing latency and improving data transmission efficiency, especially in scenarios that require fast data processing and large-scale data exchange.

[0047] In this embodiment, the baseboard supports interconnection configuration between multiple computing acceleration entities through multiple first interconnection channels. That is, the multiple first interconnection channels on the baseboard can support the connection between all computing acceleration entities, ensuring that any two computing acceleration entities can communicate and interact through the first port of the memory interconnect bus supporting the computing units, thereby meeting the interconnection requirements between multiple computing units.

[0048] As can be seen, in this embodiment, the computing unit is integrated into a standardized computing acceleration entity. The computing acceleration entity is provided with a first connector, so that multiple first ports of the computing unit integrated into the computing acceleration entity can be connected to the backplane of the processor motherboard through the first connector. The first port supports a memory interconnect bus between computing units. Furthermore, the backplane of the processor motherboard is provided with multiple first interconnect channels. Each first interconnect channel connects to one first port of each of the two computing acceleration entities, and the multiple first interconnect channels cover the interconnection between multiple computing acceleration entities. Thus, when the computing unit is integrated into the computing acceleration entity, the interconnection between multiple computing units can be realized, providing a basis for data transmission between multiple computing units.

[0049] In an optional implementation, different computing acceleration entities can be interconnected via a first interconnect channel either through a single first interconnect channel or by combining first interconnect channels.

[0050] Here, a single first interconnect channel refers to the only first interconnect channel between different computing acceleration entities; relative to a single first interconnect channel, a combined first interconnect channel includes at least two first interconnect channels, that is, a combination of at least two first interconnect channels; thus, different computing acceleration entities can be connected through a single first interconnect channel (i.e., the only first interconnect channel) or a combination of at least two first interconnect channels (i.e., a combined first interconnect channel).

[0051] In optional implementations, the choice between using a single first interconnect channel or combining first interconnect channels between computing acceleration entities can depend on the specific interconnection requirements between computing acceleration entities, computer system design, number and configuration of computing acceleration entities, etc., and the embodiments of this application do not impose limitations.

[0052] In one optional implementation, embodiments of this application support the simultaneous use of a single first interconnect channel and combined first interconnect channels to achieve interconnection between multiple computing acceleration entities. For example, when the number of multiple first ports in a computing unit is greater than the number of multiple computing acceleration entities, the first interconnect channel configured for a computing acceleration entity may include: a single first interconnect channel and multiple sets of combined first interconnect channels, wherein the number of sets of combined first interconnect channels is less than the number of multiple computing acceleration entities.

[0053] Specifically, a computing acceleration entity can connect to another computing acceleration entity through a single first interconnect channel; simultaneously, the same computing acceleration entity can also be configured with multiple sets of combined first interconnect channels, where each set of combined interconnect channels can connect to a different computing acceleration entity. In this way, a computing acceleration entity can simultaneously establish a connection with one computing acceleration entity through a single first interconnect channel, and establish connections with multiple different computing acceleration entities through multiple sets of combined first interconnect channels.

[0054] In an optional implementation, the number of sets of combined first interconnect channels configured for a computing acceleration entity can be the number of computing acceleration entities minus 2. For example, assuming there are N computing acceleration entities, one computing acceleration entity needs to be interconnected with the remaining N-1 computing acceleration entities via a first interconnect channel. Specifically, this one computing acceleration entity connects to one of the N-1 computing acceleration entities via a single first interconnect channel, and this computing acceleration entity is connected to the remaining N-2 computing acceleration entities respectively via a set of combined first interconnect channels. Therefore, the number of sets of combined first interconnect channels configured for a computing acceleration entity is the number of computing acceleration entities minus 2 (e.g., N minus 2). That is, for any given computing acceleration entity, it is allowed to connect to another computing acceleration entity different from it via a single first interconnect channel, and to connect to other computing acceleration entities via combined first interconnect channels.

[0055] In one specific implementation, taking four computing acceleration entities as an example, and the first port including seven high-speed SerDes ports, refer to... Figure 3 , Figure 3 This is a schematic diagram of the interconnection structure of computing units in a processor motherboard provided in an embodiment of this application. Figure 3 As shown, the multiple computation acceleration entities are computation acceleration entity 0, computation acceleration entity 1, computation acceleration entity 2, and computation acceleration entity 3 (i.e., Figure 3 The computing acceleration entity 0 (OAM 0, OAM 1, OAM 2 and OAM 3) integrates computing unit 10; computing acceleration entity 1 integrates computing unit 11; computing acceleration entity 2 integrates computing unit 12; computing acceleration entity 3 integrates computing unit 13.

[0056] For any computing unit, the computing unit may include multiple first ports. The first ports may be high-speed Serdes (serializer / deserializer) ports. Specifically, the multiple first ports of a computing unit may include zero high-speed Serdes port G0, first high-speed Serdes port G1, second high-speed Serdes port G2, third high-speed Serdes port G3, fourth high-speed Serdes port G4, fifth high-speed Serdes port G5, and sixth high-speed Serdes port G6.

[0057] For example, the computing unit 10 includes multiple first ports: a zero-speed Serdes port G0, a first high-speed Serdes port G1, a second high-speed Serdes port G2, a third high-speed Serdes port G3, a fourth high-speed Serdes port G4, a fifth high-speed Serdes port G5, and a sixth high-speed Serdes port G6. The same applies to computing units 11, 12, and 13, which will not be described in detail here.

[0058] It should be noted that a high-speed SerDes port is a type of port based on high-speed serial communication technology, supporting high-speed time-division multiplexing (TDM) and point-to-point serial communication technologies. Specifically, at the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a transmission medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end.

[0059] As an optional implementation, the sixth high-speed Serdes port G6 of the computing acceleration entity supports high-speed Serdes ports configured as a single first interconnect channel connection. For example, for two computing acceleration entities connected through a single first interconnect channel, the sixth high-speed Serdes ports G6 of the two computing acceleration entities are connected through a single first interconnect channel. As an optional implementation, the zero-high-speed Serdes port G0, the first high-speed Serdes port G1, the second high-speed Serdes port G2, the third high-speed Serdes port G3, the fourth high-speed Serdes port G4, and the fifth high-speed Serdes port G5 of the computing acceleration entity can be configured as high-speed Serdes ports connected by a combined first interconnect channel. At least two first interconnect channels combined by a set of combined first interconnect channels are connected to at least two high-speed Serdes ports from the zero-high-speed Serdes port G0 to the fifth high-speed Serdes port G5 of a computing acceleration entity. For example, for two computing acceleration entities connected by a combined first interconnect channel, at least two high-speed Serdes ports from the zero-high-speed Serdes port G0 to the fifth high-speed Serdes port G5 between the two computing acceleration entities are connected by a first interconnect channel, thereby forming a combined first interconnect channel composed of at least two first interconnect channels between the two computing acceleration entities.

[0060] In an optional implementation, the combined first interconnect channel supports cross-symmetrical connection of high-speed SerDes ports of different computing acceleration entities. In a cross-symmetrical connection, a high-speed SerDes port of one computing acceleration entity is connected to a high-speed SerDes port of another computing acceleration entity at a relative position, forming a mirror or symmetrical layout connection. For example, if the zeroth high-speed SerDes port G0 to the fifth high-speed SerDes port G5 of a computing acceleration entity supports high-speed SerDes ports configured to be connected by the combined first interconnect channel, then the zeroth high-speed SerDes port G0 of one computing acceleration entity can be connected to the fifth high-speed SerDes port G5 of another computing acceleration entity in a cross-symmetrical manner; the first high-speed SerDes port G1 of one computing acceleration entity can be connected to the fourth high-speed SerDes port G4 of another computing acceleration entity in a cross-symmetrical manner; the second high-speed SerDes port G2 of one computing acceleration entity can be connected to the third high-speed SerDes port G3 of another computing acceleration entity in a cross-symmetrical manner, and so on.

[0061] Based on this, in an optional implementation, a computing acceleration entity may be configured with multiple sets of combined first interconnect channels, including a first set of combined first interconnect channels and a second set of combined first interconnect channels. The computing acceleration entity connects to two different computing acceleration entities via the first set of combined first interconnect channels and the second set of combined first interconnect channels, respectively. A single first interconnect channel interfaces with the sixth high-speed SerDes port G6 of the two computing acceleration entities. A single first interconnect channel configured in one computing acceleration entity connects to other computing acceleration entities different from the two different computing acceleration entities.

[0062] The first set of combined first interconnect channels may include three first interconnect channels, which are respectively connected to the zero high-speed Serdes port G0, the first high-speed Serdes port G1, and the second high-speed Serdes port G2 of the computing acceleration entity in a cross-symmetrical manner, as well as the fifth high-speed Serdes port G5, the fourth high-speed Serdes port G4, and the third high-speed Serdes port G3 of the connected computing acceleration entity; the second set of combined first interconnect channels may include three first interconnect channels, which are respectively connected to the third high-speed Serdes port G3, the fourth high-speed Serdes port G4, and the fifth high-speed Serdes port G5 of the computing acceleration entity, as well as the second high-speed Serdes port G2, the first high-speed Serdes port G1, and the zero high-speed Serdes port G0 of the connected computing acceleration entity.

[0063] For example, combining Figure 3 As shown, the first set of combined first interconnect channels configured in the computing acceleration entity 0 includes:

[0064] The first interconnection channel between the zero high-speed Serdes port G0 of computing acceleration entity 0 and the fifth high-speed Serdes port G5 of computing acceleration entity 3.

[0065] The first interconnection channel between the first high-speed Serdes port G1 of computing acceleration entity 0 and the fourth high-speed Serdes port G4 of computing acceleration entity 3.

[0066] And, the first interconnection channel between the second high-speed Serdes port G2 of computing acceleration entity 0 and the third high-speed Serdes port G3 of computing acceleration entity 3.

[0067] The second set of combined first interconnect channels configured in the computing acceleration entity 0 includes:

[0068] The first interconnection channel between the third high-speed Serdes port G3 of computing acceleration entity 0 and the second high-speed Serdes port G2 of computing acceleration entity 1.

[0069] The first interconnection channel between the fourth high-speed Serdes port G4 of computing acceleration entity 0 and the first high-speed Serdes port G1 of computing acceleration entity 1.

[0070] And, the first interconnection channel between the fifth high-speed Serdes port G5 of computing acceleration entity 0 and the zero high-speed Serdes port G0 of computing acceleration entity 1.

[0071] Meanwhile, the single first interconnect channel configured for computing acceleration entity 0 is: the first interconnect channel that connects the sixth high-speed Serdes port G6 of computing acceleration entity 0 to the sixth high-speed Serdes port G6 of computing acceleration entity 2.

[0072] The first set of combined first interconnect channels configured in the computing acceleration entity 1 includes:

[0073] The first interconnection channel between the zero high-speed Serdes port G0 of computing acceleration entity 1 and the fifth high-speed Serdes port G5 of computing acceleration entity 0.

[0074] The first interconnection channel between the first high-speed Serdes port G1 of computing acceleration entity 1 and the fourth high-speed Serdes port G4 of computing acceleration entity 0.

[0075] And, the first interconnection channel between the second high-speed Serdes port G2 of computing acceleration entity 1 and the third high-speed Serdes port G3 of computing acceleration entity 0.

[0076] The second set of combined first interconnect channels configured in the computing acceleration entity 1 includes:

[0077] The first interconnection channel between the third high-speed Serdes port G3 of computing acceleration entity 1 and the second high-speed Serdes port G2 of computing acceleration entity 2.

[0078] The first interconnection channel between the fourth high-speed Serdes port G4 of computing acceleration entity 1 and the first high-speed Serdes port G1 of computing acceleration entity 2.

[0079] And, the first interconnection channel between the fifth high-speed Serdes port G5 of computing acceleration entity 1 and the zero high-speed Serdes port G0 of computing acceleration entity 2.

[0080] Meanwhile, the single first interconnect channel configured for computing acceleration entity 1 is: the first interconnect channel that connects the sixth high-speed Serdes port G6 of computing acceleration entity 1 to the sixth high-speed Serdes port G6 of computing acceleration entity 3.

[0081] The first set of combined first interconnect channels configured in the computing acceleration entity 2 includes:

[0082] The first interconnection channel between the zero high-speed Serdes port G0 of computing acceleration entity 2 and the fifth high-speed Serdes port G5 of computing acceleration entity 1.

[0083] The first interconnection channel between the first high-speed Serdes port G1 of computing acceleration entity 2 and the fourth high-speed Serdes port G4 of computing acceleration entity 1.

[0084] And, the first interconnection channel between the second high-speed Serdes port G2 of the computing acceleration entity 2 and the third high-speed Serdes port G3 of the computing acceleration entity 1.

[0085] The second set of combined first interconnect channels configured in the computing acceleration entity 2 includes: a first interconnect channel that interfaces the third high-speed Serdes port G3 of the computing acceleration entity 2 with the second high-speed Serdes port G2 of the computing acceleration entity 3.

[0086] The first interconnection channel between the fourth high-speed Serdes port G4 of computing acceleration entity 2 and the first high-speed Serdes port G1 of computing acceleration entity 3.

[0087] And, the first interconnection channel between the fifth high-speed Serdes port G5 of the computing acceleration entity 2 and the zero high-speed Serdes port G0 of the computing acceleration entity 3.

[0088] Meanwhile, the single first interconnect channel configured for computing acceleration entity 2 is: the first interconnect channel that connects the sixth high-speed Serdes port G6 of computing acceleration entity 2 with the sixth high-speed Serdes port G6 of computing acceleration entity 0.

[0089] The first set of combined first interconnect channels configured in the computing acceleration entity 3 includes:

[0090] The first interconnection channel between the zero high-speed Serdes port G0 of computing acceleration entity 3 and the fifth high-speed Serdes port G5 of computing acceleration entity 2.

[0091] The first interconnection channel between the first high-speed Serdes port G1 of computing acceleration entity 3 and the fourth high-speed Serdes port G4 of computing acceleration entity 2.

[0092] And, the first interconnection channel between the second high-speed Serdes port G2 of the computing acceleration entity 3 and the third high-speed Serdes port G3 of the computing acceleration entity 2.

[0093] The second set of combined first interconnect channels configured in the computing acceleration entity 3 includes:

[0094] The first interconnection channel between the third high-speed Serdes port G3 of computing acceleration entity 3 and the second high-speed Serdes port G2 of computing acceleration entity 0.

[0095] The first interconnection channel between the fourth high-speed Serdes port G4 of computing acceleration entity 3 and the first high-speed Serdes port G1 of computing acceleration entity 0.

[0096] And, the first interconnection channel between the fifth high-speed Serdes port G5 of the docking computing acceleration entity 3 and the zero high-speed Serdes port G0 of the computing acceleration entity 0.

[0097] Meanwhile, the single first interconnect channel configured for computing acceleration entity 3 is: the first interconnect channel that connects the sixth high-speed Serdes port G6 of computing acceleration entity 3 to the sixth high-speed Serdes port G6 of computing acceleration entity 1.

[0098] In another optional implementation, embodiments of this application support the use of a single first interconnect channel to interconnect multiple computing acceleration entities, that is, all connections between computing acceleration entities are achieved through the first interconnect channel. In an optional implementation, when the number of multiple first ports of a computing unit is less than the number of multiple computing acceleration entities, and the number of multiple first ports of a computing unit is one less than the number of multiple computing acceleration entities, the multiple first interconnect channels configured for a computing acceleration entity are all single first interconnect channels.

[0099] In one specific implementation, taking eight computing acceleration entities as an example, and the first port including seven high-speed SerDes ports, refer to... Figure 4 , Figure 4 This is a schematic diagram of the interconnection structure of computing units in another processor motherboard provided in an embodiment of this application. For example... Figure 4 As shown, the multiple computation acceleration entities are computation acceleration entity 0, computation acceleration entity 1, computation acceleration entity 2, computation acceleration entity 3, computation acceleration entity 4, computation acceleration entity 5, computation acceleration entity 6, and computation acceleration entity 7 (i.e., Figure 4 The computing acceleration entities are OAM 0, OAM 1, OAM 2, OAM 3, OAM 4, OAM 5, OAM 6 and OAM 7, wherein computing unit 10 is integrated on computing acceleration entity 0; computing unit 11 is integrated on computing acceleration entity 1; computing unit 12 is integrated on computing acceleration entity 2; computing unit 13 is integrated on computing acceleration entity 3; computing unit 14 is integrated on computing acceleration entity 4; computing unit 15 is integrated on computing acceleration entity 5; computing unit 16 is integrated on computing acceleration entity 6; and computing unit 17 is integrated on computing acceleration entity 7.

[0100] For any computing unit, the computing unit may include multiple first ports. The first ports may be high-speed Serdes (serializer / deserializer) ports. Specifically, the multiple first ports of a computing unit may include zero high-speed Serdes port G0, first high-speed Serdes port G1, second high-speed Serdes port G2, third high-speed Serdes port G3, fourth high-speed Serdes port G4, fifth high-speed Serdes port G5, and sixth high-speed Serdes port G6.

[0101] For example, the computing unit 10 includes multiple first ports: a zero-speed Serdes port G0, a first high-speed Serdes port G1, a second high-speed Serdes port G2, a third high-speed Serdes port G3, a fourth high-speed Serdes port G4, a fifth high-speed Serdes port G5, and a sixth high-speed Serdes port G6. The same applies to computing units 11, 12, 13, 14, 15, 16, and 17, which will not be described in detail here.

[0102] As an optional implementation, each first port of a computing acceleration entity is connected one-to-one with the first ports of other computing acceleration entities via the single first interconnect channel. In an optional implementation, the zeroth high-speed Serdes port G0 to the sixth high-speed Serdes port G6 of the computing acceleration entity supports high-speed Serdes ports configured to be connected via a single first interconnect channel, and embodiments of this application support connecting the high-speed Serdes ports of different computing acceleration entities in a cross-symmetrical manner, such that there is only one single first interconnect channel between any two computing acceleration entities.

[0103] For example, the zeroth high-speed SerDes port G0 of computing acceleration entity 0 is connected to the sixth high-speed SerDes port G6 of computing acceleration entity 7 through the single first interconnect channel; the first high-speed SerDes port G1 of computing acceleration entity 0 is connected to the fifth high-speed SerDes port G5 of computing acceleration entity 6 through the single first interconnect channel; the second high-speed SerDes port G2 of computing acceleration entity 0 is connected to the fourth high-speed SerDes port G4 of computing acceleration entity 5 through the single first interconnect channel; the third high-speed SerDes port G3 of computing acceleration entity 0 is connected to the computing acceleration... The third high-speed Serdes port G3 of entity 4 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of computing acceleration entity 0 and the second high-speed Serdes port G2 of computing acceleration entity 3 are connected through the single first interconnect channel; the fifth high-speed Serdes port G5 of computing acceleration entity 0 and the first high-speed Serdes port G1 of computing acceleration entity 2 are connected through the single first interconnect channel; the sixth high-speed Serdes port G6 of computing acceleration entity 0 and the zeroth high-speed Serdes port G0 of computing acceleration entity 1 are connected through the single first interconnect channel.

[0104] The zero-speed Serdes port G0 of computing acceleration entity 1 and the sixth-speed Serdes port G6 of computing acceleration entity 0 are connected through the single first interconnect channel; the first-speed Serdes port G1 of computing acceleration entity 1 and the fifth-speed Serdes port G5 of computing acceleration entity 7 are connected through the single first interconnect channel; the second-speed Serdes port G2 of computing acceleration entity 1 and the fourth-speed Serdes port G4 of computing acceleration entity 6 are connected through the single first interconnect channel; the third-speed Serdes port G3 of computing acceleration entity 1 and the sixth-speed Serdes port G6 of computing acceleration entity 7 are connected through the single first interconnect channel; The third high-speed Serdes port G3 of the 5 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 1 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 4 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 1 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 3 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 1 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 2 through the single first interconnect channel.

[0105] The zero-speed Serdes port G0 of computing acceleration entity 2 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 1 through the single first interconnect channel; the first-speed Serdes port G1 of computing acceleration entity 2 is connected to the fifth-speed Serdes port G5 of computing acceleration entity 0 through the single first interconnect channel; the second-speed Serdes port G2 of computing acceleration entity 2 is connected to the fourth-speed Serdes port G4 of computing acceleration entity 7 through the single first interconnect channel; the third-speed Serdes port G3 of computing acceleration entity 2 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 1 through the single first interconnect channel; The third high-speed Serdes port G3 of the 6 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 2 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 5 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 2 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 4 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 2 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 3 through the single first interconnect channel.

[0106] The zero-speed Serdes port G0 of computing acceleration entity 3 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 2 through the single first interconnect channel; the first-speed Serdes port G1 of computing acceleration entity 3 is connected to the fifth-speed Serdes port G5 of computing acceleration entity 1 through the single first interconnect channel; the second-speed Serdes port G2 of computing acceleration entity 3 is connected to the fourth-speed Serdes port G4 of computing acceleration entity 0 through the single first interconnect channel; the third-speed Serdes port G3 of computing acceleration entity 3 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 2 through the single first interconnect channel; The third high-speed Serdes port G3 of the 7 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 3 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 6 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 3 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 5 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 3 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 4 through the single first interconnect channel.

[0107] The zero-speed Serdes port G0 of computing acceleration entity 4 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 3 through the single first interconnect channel; the first-speed Serdes port G1 of computing acceleration entity 4 is connected to the fifth-speed Serdes port G5 of computing acceleration entity 2 through the single first interconnect channel; the second-speed Serdes port G2 of computing acceleration entity 4 is connected to the fourth-speed Serdes port G4 of computing acceleration entity 1 through the single first interconnect channel; the third-speed Serdes port G3 of computing acceleration entity 4 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 3 through the single first interconnect channel; The third high-speed Serdes port G3 of the computing acceleration entity 0 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 4 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 7 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 4 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 6 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 4 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 5 through the single first interconnect channel.

[0108] The zero-speed Serdes port G0 of computing acceleration entity 5 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 4 through the single first interconnect channel; the first-speed Serdes port G1 of computing acceleration entity 5 is connected to the fifth-speed Serdes port G5 of computing acceleration entity 3 through the single first interconnect channel; the second-speed Serdes port G2 of computing acceleration entity 5 is connected to the fourth-speed Serdes port G4 of computing acceleration entity 2 through the single first interconnect channel; the third-speed Serdes port G3 of computing acceleration entity 5 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 4 through the single first interconnect channel; The third high-speed Serdes port G3 of the computing acceleration entity 1 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 5 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 0 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 5 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 7 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 5 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 6 through the single first interconnect channel.

[0109] The zero-speed Serdes port G0 of computing acceleration entity 6 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 5 through the single first interconnect channel; the first-speed Serdes port G1 of computing acceleration entity 6 is connected to the fifth-speed Serdes port G5 of computing acceleration entity 4 through the single first interconnect channel; the second-speed Serdes port G2 of computing acceleration entity 6 is connected to the fourth-speed Serdes port G4 of computing acceleration entity 3 through the single first interconnect channel; the third-speed Serdes port G3 of computing acceleration entity 6 is connected to the sixth-speed Serdes port G6 of computing acceleration entity 5 through the single first interconnect channel; The third high-speed Serdes port G3 of 2 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 6 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 1 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 6 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 0 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 6 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 7 through the single first interconnect channel.

[0110] The zeroth high-speed Serdes port G0 of computing acceleration entity 7 is connected to the sixth high-speed Serdes port G6 of computing acceleration entity 6 through the single first interconnect channel; the first high-speed Serdes port G1 of computing acceleration entity 7 is connected to the fifth high-speed Serdes port G5 of computing acceleration entity 5 through the single first interconnect channel; the second high-speed Serdes port G2 of computing acceleration entity 7 is connected to the fourth high-speed Serdes port G4 of computing acceleration entity 4 through the single first interconnect channel; the third high-speed Serdes port G3 of computing acceleration entity 7 is connected to the sixth high-speed Serdes port G6 of computing acceleration entity 6 through the single first interconnect channel; The third high-speed Serdes port G3 of the 3 is connected through the single first interconnect channel; the fourth high-speed Serdes port G4 of the computing acceleration entity 7 is connected to the second high-speed Serdes port G2 of the computing acceleration entity 2 through the single first interconnect channel; the fifth high-speed Serdes port G5 of the computing acceleration entity 7 is connected to the first high-speed Serdes port G1 of the computing acceleration entity 1 through the single first interconnect channel; the sixth high-speed Serdes port G6 of the computing acceleration entity 7 is connected to the zeroth high-speed Serdes port G0 of the computing acceleration entity 0 through the single first interconnect channel.

[0111] As can be seen, in this embodiment, the computing unit is integrated into a standardized computing acceleration entity. The computing acceleration entity is provided with a first connector, so that multiple first ports of the computing unit integrated into the computing acceleration entity can be connected to the backplane of the processor motherboard through the first connector. The first port supports a memory interconnect bus between computing units. Furthermore, the backplane of the processor motherboard is provided with multiple first interconnect channels. Each first interconnect channel connects to one first port of each of the two computing acceleration entities, and the multiple first interconnect channels cover the interconnection between multiple computing acceleration entities. Thus, when the computing unit is integrated into the computing acceleration entity, the interconnection between multiple computing units can be realized, providing a basis for data transmission between multiple computing units.

[0112] In a further optional implementation, the computing unit may also include a second port, which is connected to the backplane of the processor motherboard via the first connector. The second port supports a wide-area functional link bus between computing units. Correspondingly, the backplane may also include multiple second interconnect channels, with each second interconnect channel interfacing with the second ports of two computing acceleration entities.

[0113] Specifically, the connection channel between the second ports of different computing acceleration entities is called the second interconnect channel. That is, the second interconnect channel is a channel designed by the backplane to connect and manage the data flow of the second ports. The second interconnect channel interfaces with the second ports of the computing units integrated by the computing acceleration entities on the processor motherboard, and each second interconnect channel connects the respective second ports of two computing acceleration entities to allow point-to-point communication between the computing units of the two computing acceleration entities, thereby reducing latency and improving data transmission efficiency, especially in scenarios that require fast data processing and large-scale data exchange.

[0114] It should be noted that the Wide Area Function Link Bus refers to a bus that supports the WAFL (Write Anywhere File Layout) protocol. WAFL, also known as the "Write Anywhere File Layout" protocol, is a file system protocol specifically designed for NAS (Network Attached Storage) systems. The WAFL protocol allows data to be written to any location on the storage device, which improves the flexibility and efficiency of the storage system.

[0115] In an optional implementation, the plurality of computing acceleration entities are arranged in a row, and the second ports of the computing acceleration entities are connected sequentially through a second interconnection channel, with the second ports of the first and last computing acceleration entities connected through the second interconnection channel.

[0116] In a specific implementation, with Figure 3Taking four computing acceleration entities as an example, the second port is a Wide Area Function Link (WAFL); the second interconnect channels on the baseboard are respectively: the second interconnect channel connecting the WAFL of computing acceleration entity 0 and the WAFL of computing acceleration entity 1, the second interconnect channel connecting the WAFL of computing acceleration entity 1 and the WAFL of computing acceleration entity 2, the second interconnect channel connecting the WAFL of computing acceleration entity 2 and the WAFL of computing acceleration entity 3, and the second interconnect channel connecting the WAFL of computing acceleration entity 3 and the WAFL of computing acceleration entity 0.

[0117] In another specific implementation, with Figure 4 Taking eight computing acceleration entities as an example, the second port is a Wide Area Function Link (WAFL). The second interconnect channels on the baseboard are as follows: the second interconnect channel connecting the WAFL of computing acceleration entity 0 to the WAFL of computing acceleration entity 1; the second interconnect channel connecting the WAFL of computing acceleration entity 1 to the WAFL of computing acceleration entity 2; the second interconnect channel connecting the WAFL of computing acceleration entity 2 to the WAFL of computing acceleration entity 3; and the second interconnect channel connecting the WAFL of computing acceleration entity 3. The second interconnection channel of the wide area function link port (WAFL) of computing acceleration entity 4, the second interconnection channel of the wide area function link port (WAFL) of computing acceleration entity 4 and the wide area function link port (WAFL) of computing acceleration entity 5, the second interconnection channel of the wide area function link port (WAFL) of computing acceleration entity 5 and the wide area function link port (WAFL) of computing acceleration entity 6, the second interconnection channel of the wide area function link port (WAFL) of computing acceleration entity 6 and the wide area function link port (WAFL) of computing acceleration entity 7, and the second interconnection channel of the wide area function link port (WAFL) of computing acceleration entity 7 and the wide area function link port (WAFL) of computing acceleration entity 0.

[0118] In an optional implementation, the computing unit may further include a third port P0 and a fourth port P1; the third port P0 supports the PCIe bus and the memory interconnect bus between the computing unit; the fourth port P1 supports the PCIe bus; the processor motherboard may further include: a PCIe retimer and a second connector; wherein, the third port P0 is connected to the backplane of the processor motherboard through the first connector, and is connected to the PCIe retimer through the PCIe retimer connection channel of the backplane; the PCIe retimer is connected to other motherboards through the second connector.

[0119] In the specific implementation, refer to Figure 5 , Figure 5 This is a schematic diagram of an optional structure for connecting the computing acceleration entity provided in this application embodiment to other motherboards. For example... Figure 5 As shown, the acceleration modules (OAM modules) on the baseboard 101 consist of four computing acceleration entities. The third port P0 (not shown in the figure) of each computing acceleration entity is connected to the PCIe retimer (e.g., ...) through the PCIe retimer connection channel of the baseboard. Figure 5 As shown in the figure, the PCIe retimer is connected to other motherboards via a second connector to enable data transfer between different motherboards. In an optional implementation, the second connector can be connected to other motherboards (e.g., the CPU motherboard) via a PCIe converter (i.e., the PCIe switch board in the figure).

[0120] This application also provides a computer device, which includes a processor motherboard as described above.

[0121] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0122] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A processor motherboard, characterized in that, include: Multiple computing acceleration entities, wherein the computing acceleration entity is a standardized entity unit for integrating computing units, and the computing acceleration entity includes computing units and a first connector; The computing unit includes a plurality of first ports, each of which is connected to the backplane of the processor motherboard via a first connector. The first ports support a memory interconnect bus between computing units. The base plate includes multiple first interconnect channels, each first interconnect channel interfacing with a first port of each of two compute acceleration entities, and the multiple first interconnect channels cover the interconnection between the multiple compute acceleration entities.

2. The processor motherboard according to claim 1, characterized in that, The two computing acceleration entities are connected via a single first interconnect channel or a combination of first interconnect channels; The single first interconnect channel is a single first interconnect channel between two computing acceleration entities; The combined first interconnect channel includes at least two first interconnect channels between two computing acceleration entities.

3. The processor motherboard according to claim 2, characterized in that, The number of the plurality of first ports is greater than the number of the plurality of computing acceleration entities; a first interconnect channel configured in a computing acceleration entity includes: A single first interconnect channel and multiple sets of combined first interconnect channels, wherein the number of sets of combined first interconnect channels is less than the number of the plurality of computing acceleration entities.

4. The processor motherboard according to claim 3, characterized in that, The plurality of computing acceleration entities are four computing acceleration entities; the first port is a high-speed Serdes port, and the plurality of first ports include: zero high-speed Serdes port, first high-speed Serdes port, second high-speed Serdes port, third high-speed Serdes port, fourth high-speed Serdes port, fifth high-speed Serdes port and sixth high-speed Serdes port. A computing acceleration entity is configured with multiple sets of combined first interconnect channels, including: a first set of combined first interconnect channels and a second set of combined first interconnect channels, wherein the computing acceleration entity connects to two different computing acceleration entities through the first set of combined first interconnect channels and the second set of combined first interconnect channels respectively. The first group of first interconnect channels includes three first interconnect channels, which are respectively connected to the zero high-speed Serdes port, the first high-speed Serdes port, the second high-speed Serdes port of the computing acceleration entity, and the fifth high-speed Serdes port, the fourth high-speed Serdes port, and the third high-speed Serdes port of the connected computing acceleration entity. The second group of combined first interconnect channels includes three first interconnect channels, which respectively connect to the third high-speed Serdes port, the fourth high-speed Serdes port, and the fifth high-speed Serdes port of the computing acceleration entity, as well as the second high-speed Serdes port, the first high-speed Serdes port, and the zeroth high-speed Serdes port of the connected computing acceleration entity. The single first interconnect channel configured in the one computing acceleration entity connects to other computing acceleration entities that are different from the two different computing acceleration entities, and the single first interconnect channel interfaces with the sixth high-speed Serdes port of the different computing acceleration entities.

5. The processor motherboard according to claim 2, characterized in that, The number of the plurality of first ports is less than the number of the plurality of computing acceleration entities, and the number of the plurality of first ports is one less than the number of the plurality of computing acceleration entities; Each of the plurality of first interconnect channels is a single first interconnect channel.

6. The processor motherboard according to claim 5, characterized in that, The plurality of computing acceleration entities are eight computing acceleration entities; the first port is a high-speed Serdes port, and the plurality of first ports include: zero high-speed Serdes port, first high-speed Serdes port, second high-speed Serdes port, third high-speed Serdes port, fourth high-speed Serdes port, fifth high-speed Serdes port and sixth high-speed Serdes port. One computing acceleration entity is connected one-to-one with the other seven computing acceleration entities through the single first interconnect channel.

7. The processor motherboard according to claim 1, characterized in that, The computing unit further includes a second port, which is connected to the backplane of the processor motherboard via the first connector. The second port supports a wide area function link bus between computing units. The base plate also includes multiple second interconnect channels, one of which connects to the second port of each of the two computing acceleration entities.

8. The processor motherboard according to claim 7, characterized in that, The plurality of computing acceleration entities are arranged in a row, and the second ports of the computing acceleration entities are connected sequentially through the second interconnection channel, with the second ports of the first and last computing acceleration entities connected through the second interconnection channel.

9. The processor motherboard according to claim 1, characterized in that, The computing unit also includes a third port and a fourth port; The third port supports the PCIe bus and the memory interconnect bus between the computing unit; The fourth port supports the PCIe bus; The processor motherboard also includes: a PCIe retimer and a second connector; The third port is connected to the backplane of the processor motherboard via the first connector, and is connected to the PCIe retimer via the PCIe retimer connection channel of the backplane; the PCIe retimer is connected to other motherboards via the second connector.

10. A computer device, characterized in that, Including the processor motherboard as described in any one of claims 1-9.

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