Edge calculation box circuit structure

Abstract

The utility model provides an edge computing box circuit structure, which comprises a double-sided PCB (printed circuit board) substrate, a communication control area is arranged on a front partition, and a power storage area is arranged on a back partition; according to the front layout, an SIM card seat and a 4G communication module are arranged at the upper left corner; the distance between the central processor and the edge of the 4G communication module is 10 + / -2mm; four relays are arranged on the right side in parallel, and a drive circuit of each relay is directly connected with a GPIO pin of the processor; a digital input interface, an analog input interface, an RS485 interface and an output interface are integrated at the upper end of the controller; the power interface is adjacent to the DC-DC conversion chip; an LED indicating lamp, a debugging interface, a serial port, a USB interface and an Ethernet interface are integrated at the lower end; according to the utility model, calculation and processing can be carried out at the edge side of data generation, the cloud pressure is effectively reduced, the real-time performance and reliability of the system are improved, the interface expansion capability is improved, and the signal interference is reduced.

Description

Technical Field

[0001] This utility model relates to the field of edge computing technology for the Internet of Things, and in particular to an edge computing box circuit structure. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), 5G, Artificial Intelligence (AI), and cloud computing, agricultural IoT has also developed rapidly. However, with the increase in IoT sensors, large-scale and refined management operations will generate a large amount of environmental monitoring data. If intelligent control is required through remote servers, it will increase the server pressure, leading to problems such as large data transmission volume and transmission latency, and generating more bandwidth costs, which cannot meet the development goals of precise control and efficient resource utilization in precision agriculture.

[0003] Traditional agricultural IoT systems rely on cloud servers to process sensor data, which suffers from problems such as high data transmission latency, high bandwidth costs, and poor real-time performance. Existing edge computing devices often have shortcomings such as limited interfaces, poor power supply adaptability, and insufficient compatibility with industrial environments. Summary of the Invention

[0004] In view of this, the purpose of this utility model is to provide an edge computing box circuit structure that can perform calculations and processing at the edge where data is generated, effectively reducing cloud pressure, improving the real-time performance and reliability of the system, enhancing interface expansion capabilities, and reducing signal interference.

[0005] This utility model is implemented using the following method: an edge computing box circuit structure.

[0006] The double-sided PCB substrate has a communication control area on the front and a power storage area on the back.

[0007] Front layout: The upper left corner houses the SIM card slot and 4G communication module; the central processing unit is 10±2mm from the edge of the 4G communication module; four relays are arranged in parallel on the right side, with each relay's drive circuit directly connected to the processor's GPIO pins; the upper end integrates digital input interfaces, analog input interfaces, RS485 interfaces, and output interfaces; the power interface is adjacent to the DC-DC converter chip; the AXP221S power management chip outputs three regulated voltages: 1.2V / 3A with a trace length ≤20mm to the processor core, and 1.8V / 2A connected to the memory chip via a π-type filter; eMMC storage chip and DDR3 memory; the lower end integrates LED indicators, a debugging interface, a serial port, a USB interface, an Ethernet interface, and a power interface;

[0008] Reverse layout: The LoRa communication module is located in the upper left corner, corresponding to the 4G communication module, and the onboard battery is located in the lower right corner.

[0009] Furthermore, the processor interconnect architecture: the Allwinner A40i-H's PCIe x1 lane is directly connected to the 4G communication module's MiniPCIe socket; Ethernet circuitry: the processor's RMII interface is connected to the RTL8201F-VB-CG chip via a 22Ω impedance matching resistor, and a 0.1μF decoupling capacitor is connected to the center tap of the network transformer.

[0010] Furthermore, the RS-485 interface is connected to the processor's UART1 port via the SN65HVD75DR chip, with TVS diodes D1-D4 connected in parallel between signal lines A and B; the RS-232 interface is connected to the processor's UART2 port via the MAX3232ESE chip (U17); and the analog input interface is connected to the processor's SPI bus via the ADC0832 analog-to-digital converter.

[0011] Furthermore, the VIN pin of the AXP221S power management chip is connected to the 12V DC input interface, the VBAT pin is connected to the lithium battery interface, and the ENABLE pin is connected to the GPIO1 pin of the Allwinner A40i-H processor; the VIN terminal of the RT8279GSP chip is connected to the 12V input, and the output is divided into two paths: the first path outputs 5V_Relay to the relay array through the L1 inductor, and the second path outputs 3.3V_MCU to the processor; the coil terminals of the four relays are connected to the processor's GPIO group through the ULN2803 driver chip, and the contact terminals are connected to the output interface; the 4G module is connected to the processor's PCIe bus through the Mini-PCIE socket, and the RTL8201F-VB-CG Ethernet PHY chip is connected to the processor through the RMII interface.

[0012] Furthermore, the enable pin EN of the RT8279GSP chip is connected to the processor's GPIO2 pin, and its feedback pin FB sets the output voltage through a resistor divider network R1 / R2.

[0013] Furthermore, the RE / DE pins of the RS-485 interface chip U6 are connected in parallel to the processor's GPIO3 pin to achieve automatic switching between transmit and receive modes.

[0014] The beneficial effects of this utility model are as follows: This utility model solves the problems of chaotic layout, poor interface expandability, and low power efficiency in traditional equipment through a double-sided PCB substrate partitioned layout, multi-interface integrated design, and optimized power management scheme. It has the advantages of optimizing circuit layout, improving interface expandability, enhancing power management efficiency, and reducing signal interference. Data can be collected, analyzed, and processed near the user end without needing to be transmitted back to the server. Edge computing, with its characteristic of processing and analyzing data close to the data source, optimizes the data transmission latency problem in the system and reduces the computing pressure on the cloud server, showing broad application prospects and further promoting the development of precision agriculture. It can perform calculations and processing at the edge where data is generated, effectively reducing cloud pressure and improving the real-time performance and reliability of the system. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of this utility model.

[0016] Figure 2 This is the circuit schematic of the processor (A40i-H chip).

[0017] Figure 3 This is the circuit diagram for the external power supply chip (RT8279GSP chip).

[0018] Figure 4 This is the circuit diagram for the RS232 serial port (MAX3232ESE chip).

[0019] Figure 5 This is the circuit diagram of the AXP221S power management chip.

[0020] In the diagram: Double-sided PCB substrate-1, SIM card slot-2, 4G communication module-3, central processing unit-4, relay-5, power interface-6, eMMC storage chip-7, memory chip-8, AXP221S power management chip-9, LED indicator-10, debugging interface-11, serial port-12, USB interface-13, Ethernet interface-14. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings.

[0022] Please see Figures 1 to 5 As shown, this utility model provides an embodiment: an edge computing box circuit structure.

[0023] The double-sided PCB substrate has a communication control area on the front and a power storage area on the back.

[0024] Front layout: The upper left corner houses the SIM card slot and 4G communication module; the central processing unit is 10±2mm from the edge of the 4G communication module; four relays are arranged in parallel on the right side, with each relay's drive circuit directly connected to the processor's GPIO pins; the upper end integrates digital input interfaces, analog input interfaces, RS485 interfaces, and output interfaces; the power interface is adjacent to the DC-DC converter chip; the AXP221S power management chip outputs three regulated voltages: 1.2V / 3A with a trace length ≤20mm to the processor core, and 1.8V / 2A connected to the memory chip via a π-type filter; eMMC storage chip and DDR3 memory; the lower end integrates LED indicators, a debugging interface, a serial port, a USB interface, an Ethernet interface, and a power interface;

[0025] Reverse layout: The LoRa communication module is located in the upper left corner, corresponding to the 4G communication module, and the onboard battery is located in the lower right corner.

[0026] The double-sided PCB substrate refers to a printed circuit board with functional partitions on both sides, typically made of FR-4 material, with double-sided electrical connections achieved through vias. The communication control area integrates the wireless communication module and processor, and electromagnetic isolation is achieved using a shielding cover. The power storage area contains energy storage components and power conversion circuits, and heat dissipation is enhanced using copper foil ground planes. The processor-communication module spacing control refers to the minimum distance required to maintain signal integrity, achieved through impedance matching design. A multi-channel relay array refers to an independently controllable group of switching devices, implemented using optocoupler-isolated drive circuits. A composite power management system refers to a power supply architecture supporting multiple voltage outputs, implemented through multi-stage DC-DC conversion circuits.

[0027] Specifically, the communication control area on the front of the substrate houses the wireless communication module in a specific region, with the processor located within a preset distance of the module. Optimized wiring paths shorten signal transmission distances. Relay drive circuits are directly connected to the processor's digital output ports, avoiding signal attenuation caused by intermediate conversion stages. Industrial interfaces are linearly arranged along the substrate edge, with grounding isolation strips between each interface. The power management module supplies power to the processor core, memory units, and peripherals through multi-stage voltage regulation circuits, while the filtering circuit employs a specific topology to eliminate high-frequency noise. The low-power communication module on the back complements the main communication module on the front, and the onboard battery provides uninterrupted power to the real-time clock (RTC) through an intelligent switching circuit.

[0028] Compared to existing technologies, the double-sided layout design effectively solves the problem of low space utilization on single-sided panels, and the functional zoning strategy significantly reduces the risk of signal crosstalk. The composite power supply architecture, compared to traditional single-channel power supply solutions, can simultaneously meet the dual requirements of high-precision processor power supply and high-current relay drive. The modular layout of industrial interfaces, compared to random distribution, facilitates field wiring and maintenance. The symmetrical arrangement of communication modules, compared to centralized layout, optimizes antenna radiation patterns and reduces mutual interference.

[0029] Through the above technical solutions, this application achieves localized real-time processing of data from multiple types of sensors, reducing reliance on cloud servers. The optimized circuit layout effectively suppresses electromagnetic interference, improving the operational stability of the equipment in complex environments. The modular interface design supports plug-and-play functionality for various agricultural sensors, enhancing the equipment's adaptability to different scenarios. The composite power supply architecture design simultaneously meets the dual requirements of high-precision processor power supply and high-current relay drive, effectively optimizing power system isolation to reduce cross-interference.

[0030] Processor interconnect architecture: The Allwinner A40i-H's PCIe x1 lane is directly connected to the 4G communication module's Mini PCIe socket; Ethernet circuit: The processor's RMII interface is connected to the RTL8201F-VB-CG chip via a 22Ω impedance matching resistor, and a 0.1μF decoupling capacitor is connected to the center tap of the network transformer.

[0031] The PCIe x1 lane refers to a data transmission channel conforming to the PCI Express standard. It can be implemented using the PCIe controller built into the Allwinner A40i-H processor, establishing a high-speed data path with the 4G communication module through a direct physical layer connection. The 22Ω impedance matching resistor is a component used to adjust the characteristic impedance of the signal transmission line. It can be implemented using a surface-mount resistor to eliminate signal reflections between the RMII interface and the PHY chip. The 0.1μF decoupling capacitor connected to the center tap of the network transformer refers to a capacitor placed between the center tap of the transformer and ground in Ethernet circuit design. It can be implemented using a ceramic capacitor to filter out common-mode noise interference.

[0032] Specifically, the Allwinner A40i-H processor's PCIe x1 lane is physically connected directly to the Mini PCIe socket of the 4G communication module, forming a point-to-point high-speed data transmission path. The processor's RMII interface is connected to the RTL8201F-VB-CG Ethernet PHY chip via a 22Ω impedance matching resistor to ensure impedance continuity for signal transmission. The center tap of the network transformer is grounded via a 0.1μF decoupling capacitor, forming a high-frequency noise filtering loop. This design allows the 4G communication module to directly access processor resources via the PCIe bus while ensuring the signal integrity of the Ethernet interface.

[0033] Compared to existing technologies, traditional edge computing devices often use USB or SPI interfaces to connect wireless communication modules, resulting in bandwidth limitations and protocol conversion delays. Existing Ethernet circuits frequently neglect impedance matching design, leading to decreased signal integrity. This solution improves data transmission efficiency through direct PCIe connection, reduces signal reflection through precise impedance matching, and suppresses common-mode interference through decoupling capacitors, thus enhancing the overall stability and reliability of the communication interface.

[0034] The RS-485 interface is connected to the processor's UART1 port via the SN65HVD75DR chip, with TVS diodes D1-D4 connected in parallel between signal lines A and B; the RS-232 interface is connected to the processor's UART2 port via the MAX3232ESE chip (U17); and the analog input interface is connected to the processor's SPI bus via the ADC0832 analog-to-digital converter.

[0035] The SN65HVD75DR chip is an industry-standard RS-485 transceiver, specifically using a Texas Instruments half-duplex differential bus driver to convert the processor's UART signals into differential signals. Its common-mode voltage range supports -7V to 12V, suppressing electromagnetic interference in industrial environments. TVS diodes D1-D4 are transient voltage suppression diodes connected in parallel between RS-485 signal lines A and B to absorb high-voltage pulses generated by lightning strikes or electrostatic discharge, preventing damage to the interface chip. The MAX3232ESE chip is a 3.0V to 5.5V powered RS-232 level converter, specifically employing a dual-channel design. It generates ±8V voltage through an internal charge pump to convert the processor's TTL level to the RS-232 standard level. The ADC0832 analog-to-digital converter is an 8-bit resolution serial interface ADC that communicates with the processor via the SPI bus. It converts 0-5V analog input signals into digital values, supporting two-channel differential or four-channel single-ended input modes.

[0036] Specifically, the RS-485 interface uses the SN65HVD75DR chip to convert the processor's UART1 signal into a differential signal for transmission. A TVS diode array provides voltage clamping protection between the signal lines, limiting the voltage to a safe range within nanoseconds in the event of an overvoltage surge. The RS-232 interface uses the MAX3232ESE chip for level conversion, enabling the processor to communicate directly with devices using negative logic levels. The analog input interface uses the ADC0832 chip to sample the 0-5V voltage signal output from the sensor. The converted digital signal is transmitted to the processor via the SPI bus, enabling real-time acquisition of analog quantities such as soil moisture and temperature.

[0037] Compared to existing technologies, traditional RS-485 interfaces often use discrete components to build transceiver circuits, resulting in weak anti-interference capabilities and large PCB area requirements. This solution integrates a transceiver chip with a TVS protection diode, significantly improving interface reliability while maintaining communication distance. Existing devices mostly use a single communication interface, incompatible with both RS-485 and RS-232 industrial standards. This solution achieves multi-protocol support through an independent interface design. Traditional analog input circuits using parallel ADCs lead to complex wiring; this solution selects the serial interface ADC0832 chip, reducing the number of signal lines while supporting multi-channel switching sampling.

[0038] Through the above technical solutions, this application achieves stable communication of multiple interfaces in agricultural field environments. The anti-interference capability of the RS-485 interface can adapt to the complex electromagnetic environment of farmland or agricultural greenhouses. The dual standard serial port design meets the access requirements of different agricultural equipment. The analog signal acquisition system can process multiple sensor data in parallel, effectively reducing the data processing latency of edge computing nodes.

[0039] The AXP221S power management chip's VIN pin connects to the 12V DC input interface, the VBAT pin connects to the lithium battery interface, and the ENABLE pin connects to the GPIO1 pin of the Allwinner A40i-H processor. The RT8279GSP chip's VIN pin connects to the 12V input, and its output is divided into two paths: the first path outputs 5V_Relay to the relay array via the L1 inductor, and the second path outputs 3.3V_MCU to the processor. The coil ends of the four relays are connected to the processor's GPIO group via the ULN2803 driver chip, and the contact ends are connected to the output interface. The 4G module is connected to the processor's PCIe bus via the Mini-PCIE socket, and the RTL8201F-VB-CG Ethernet PHY chip is connected to the processor via the RMII interface.

[0040] The AXP221S power management chip is an integrated circuit with multiple regulated outputs, specifically implemented using a power management module supporting three independent voltage outputs, used to provide stable power to the processor core and memory chips. The RT8279GSP chip is a dual-output DC-DC converter, specifically implemented using a synchronous buck converter, using inductor voltage division to separate the 5V relay drive and the 3.3V processor power supply. The ULN2803 driver chip is an eight-channel Darlington transistor array, specifically implemented using a high-current driver chip, used to isolate the processor GPIO signals from the high-current load of the relay coil. The Mini-PCIE socket is a connector conforming to the PCI Express interface standard, specifically implemented using a 52-pin slot, used to support the physical connection and signal transmission of the 4G communication module.

[0041] Specifically, the 12V DC input is connected to the system via the VIN pin of the AXP221S chip, the lithium battery provides backup power via the VBAT pin, and the processor's GPIO1 pin controls the enable state of the power management chip via a level signal. The RT8279GSP chip converts the 12V input into two independent outputs: 5V and 3.3V. The 5V_Relay output, after being filtered by an inductor, powers the relay array, while the 3.3V_MCU output directly powers the processor's core circuitry. The ULN2803 driver chip converts the processor's GPIO control signals into current sufficient to drive the relay coils, with the contact terminals directly controlling the on / off state of the output interface. The 4G communication module establishes a high-speed data transmission channel with the processor's PCIe bus via a Mini-PCIe socket, and the RTL8201F Ethernet PHY chip implements network communication functionality via the RMII interface.

[0042] Compared to existing technologies, traditional edge devices often employ single-path power conversion schemes, leading to unstable power supply. This solution achieves multi-stage power separation through the collaborative operation of the AXP221S and RT8279GSP, ensuring stable operation of the processor core while meeting the high current requirements of the relay array. Existing technologies often use discrete components for relay drive circuits; this solution uses an integrated driver chip to achieve signal isolation and load matching, improving control accuracy and reliability. Compared to the serial communication method between the 4G module and the processor in traditional devices, this solution establishes a high-speed data transmission channel via the PCIe bus.

[0043] Through the above technical solutions, this application effectively solves the problems of unstable power supply and susceptibility to interference in control signals for agricultural IoT devices in complex working environments, and achieves precise driving of multiple relays and high-speed data transmission. The multi-level separation design of the power management system enhances the adaptability of the device to different power supply environments, the integrated drive scheme reduces the risk of signal distortion, and the direct bus connection architecture improves data transmission efficiency, thereby ensuring the reliable operation of edge computing devices in harsh agricultural field conditions.

[0044] The enable pin EN of the RT8279GSP chip is connected to the processor's GPIO2 pin, and its feedback pin FB sets the output voltage through a resistor divider network R1 / R2.

[0045] The enable pin EN refers to the power chip's startup control pin. Specifically, the high and low level signals output by the processor's GPIO pins can be used to remotely control the chip's operating state. This design allows the power module's activation state to be dynamically adjusted according to system load requirements.

[0046] Among them, the resistor voltage divider network R1 / R2 refers to a voltage sampling circuit composed of two series resistors. Specifically, surface mount resistors with an accuracy of 1% can be used to achieve precise adjustment of the output voltage. By adjusting the voltage division ratio, the stability requirements of the supply voltage for different loads can be matched.

[0047] Specifically, when the processor outputs a high level through the GPIO2 pin, the RT8279GSP chip enters the working state, converting the 12V input voltage into two outputs: 5V and 3.3V. A resistor divider network connected to the feedback pin monitors the output voltage in real time. When a voltage deviation is detected, a closed-loop regulation mechanism automatically corrects the duty cycle to ensure the output voltage remains stable at the set value. This design allows for quick adaptation to the power supply accuracy requirements of different application scenarios by modifying the values ​​of the voltage divider resistors.

[0048] Compared to existing technologies, traditional solutions typically use fixed-level or mechanical switches for power chip enable control, which cannot achieve remote intelligent control. Furthermore, feedback loops often use fixed-value resistors, resulting in insufficient flexibility in output voltage regulation. This solution dynamically controls power supply start-up and shutdown through processor GPIO, combined with a configurable voltage divider network, effectively improving the adaptive capability of the power supply system.

[0049] Through the above technical solution, this application realizes intelligent management of the power module. When the load of agricultural IoT equipment suddenly increases or the solar power supply fluctuates, it can dynamically maintain a stable voltage output and avoid relay malfunction or communication module interruption caused by abnormal power supply.

[0050] The RE / DE pins of the RS-485 interface chip U6 are connected in parallel to the GPIO3 pin of the processor to achieve automatic switching between transmit and receive modes.

[0051] The RS-485 interface chip U6 refers to a differential signal transmission device conforming to industrial communication standards. Specifically, it can be implemented using the SN65HVD75DR chip, which has common-mode interference immunity and is suitable for long-distance data transmission in agricultural fields. The parallel connection of the RE / DE pins refers to the electrical connection between the chip's receive enable and transmit enable control terminals. This can be achieved through copper foil traces on the printed circuit board, forming a single control node. The GPIO3 pin is the programmable digital input / output port configured by the processor. It can be configured in push-pull output mode, and the communication direction can be switched by level signals.

[0052] Specifically, when the processor needs to send data, the GPIO3 pin outputs a high level to drive the RE / DE pin, causing the RS-485 interface chip to enter transmit mode. After the data transmission is complete, the GPIO3 pin automatically switches to a low level, causing the interface chip to switch to receive mode. This control method eliminates the timing errors caused by software polling through direct hardware connection, ensuring strict timing matching between temperature and humidity sensor data acquisition and equipment control command transmission in multi-node polling scenarios in agricultural greenhouses.

[0053] Compared to existing technologies, traditional RS-485 communication requires the processor to control the switching of transmit and receive modes via software, which carries the risk of bus collisions due to instruction execution delays. This solution achieves automatic switching of transmit and receive modes through direct hardware pin connection, effectively avoiding signal collisions caused by software response delays when multiple devices communicate concurrently in an agricultural environmental monitoring system.

[0054] Through the above technical solution, this application achieves zero-latency directional control of RS-485 bus communication in agricultural IoT gateway devices, solving the data packet conflict problem when multiple sensors communicate concurrently, and improving the communication reliability of agricultural environmental monitoring systems. In greenhouse applications, this design ensures real-time data interaction between light intensity sensors, soil moisture sensors, and ventilation equipment, avoiding actuator malfunctions that may be caused by traditional polling mechanisms.

[0055] Circuit description of this utility model:

[0056] This circuit architecture implements a device with edge computing capabilities, which can be powered by a 12V external power supply or a battery. The circuit uses the Allwinner A40i-H SOC chip as the processor and includes a power module, a storage module, a data acquisition module, a control module, and a communication module.

[0057] After acquiring data from various sensors, the data acquisition module transmits it to the microprocessor. The program in the microprocessor calculates the input data, generates the result data, and stores it in the storage module. The calculated control information is then transmitted to the control module, which outputs control signals to control external devices. Simultaneously, valid data is transmitted to a designated IoT cloud platform via a 4G network.

[0058] A40i-H Chip: The A40i is an industrial-grade chip based on Allwinner Technology's Cortex-A7 quad-core processor, with a maximum clock speed of 1.2GHz. It features a built-in Mali400 MP2 GPU, supports dual-screen output (LVDS / RGB / MIPI / HDMI multi-interface compatibility), has rich peripheral and interface expansion capabilities, supports multiple communication modules, has a fast boot speed, supports dynamic frequency adjustment and multiple sleep modes, is suitable for battery-powered scenarios, has strong system compatibility, supports operating systems such as Linux and Android, and has high energy efficiency and cost-effectiveness.

[0059] The AXP221S chip is a highly integrated power system management chip with an input voltage range typically between 3.0V and 5.5V, adaptable to various power inputs. This chip provides multiple stable output voltages, including 1.2V, 1.8V, and 3.3V, to meet the needs of different electronic components. It can provide up to 3A of output current, suitable for devices with high current requirements. Its low quiescent power consumption, especially in standby mode, effectively reduces system energy consumption. Built-in over-temperature and over-current protection enhances system safety and stability. The AXP221S boasts a conversion efficiency of up to 95%, exhibiting robust performance under various load conditions. This chip is typically packaged in a QFN package for easy integration and heat dissipation.

[0060] The KLM8G1GETF-B041 chip is an 8GB eMMC memory chip manufactured by Samsung. It uses a BGA153 package and is mainly used in industrial control, consumer electronics, and automotive electronics.

[0061] The H5TQ4G63AFR-RDC chip is a DDR3 memory chip manufactured by Hynix. It supports DDR3 2700MHz (2700MHz) speed, operates at a voltage of 1.5V±0.075V, complies with JEDEC standards, supports dynamic self-refresh function, and can operate stably in a temperature range of -0°C to 95°C.

[0062] RT8279GSP Chip: The RT8279GSP is a DC-to-DC power supply chip from the RICHTEK brand. It supports a wide input voltage range of DC 4.5V to 36V and an output voltage range of 1.2V to 26V, with a maximum output current of 5A.

[0063] The MAX3232ESE chip is a low-power, multi-channel RS-232 transceiver widely used in industrial control and portable devices. This device supports a single supply from 3V to 5.5V, with a maximum data rate of 250kbit / s, and provides ±15kV IEC ESD (electrostatic discharge) protection, conforming to TIA / EIA-232-F standards. It integrates dual drivers and dual receivers, as well as dual charge pump circuitry, generating RS-232 voltage levels without an external power supply.

[0064] The SN65HVD75DR chip is a high-performance RS-485 line driver from Texas Instruments, designed for high-speed data transmission applications in industrial, automotive, and communication systems. As a powerful differential signal transmission solution, it is widely used in applications requiring long-distance, interference-resistant, and reliable operation.

[0065] The RTL8201F-VB-CG chip is a low-power 10 / 100Mbps Ethernet PHY chip from Realtek. It supports auto-negotiation and fiber extension and is widely used in routers, FPGA projects, and IoT devices to provide stable network connectivity for embedded systems. It supports configurable WAN and LAN functions and adapts to different network environments.

[0066] The above description is only a preferred embodiment of the present utility model. All equivalent changes and modifications made within the scope of the patent application of the present utility model shall be covered by the present utility model.

Claims

1. An edge computing box circuit structure, characterized in that: The double-sided PCB substrate has a communication control area on the front and a power storage area on the back. Front layout: The upper left corner houses the SIM card slot and 4G communication module; the central processing unit is 10±2mm from the edge of the 4G communication module; four relays are arranged in parallel on the right side, with each relay's drive circuit directly connected to the processor's GPIO pins; the upper end integrates digital input interfaces, analog input interfaces, RS485 interfaces, and output interfaces; the power interface is adjacent to the DC-DC converter chip; the AXP221S power management chip outputs three regulated voltages: 1.2V / 3A with a trace length ≤20mm to the processor core, and 1.8V / 2A connected to the memory chip via a π-type filter; eMMC storage chip and DDR3 memory; the lower end integrates LED indicators, a debugging interface, a serial port, a USB interface, an Ethernet interface, and a power interface; Reverse layout: The LoRa communication module is located in the upper left corner, corresponding to the 4G communication module, and the onboard battery is located in the lower right corner; Processor interconnect architecture: The Allwinner A40i-H's PCIe x1 channel is directly connected to the 4G communication module Mini. PCIe socket; Ethernet circuit: The processor's RMII interface is connected to the RTL8201F-VB-CG chip via a 22Ω impedance matching resistor, and a 0.1μF decoupling capacitor is connected to the center tap of the network transformer; the RS-485 interface is connected to the processor's UART1 port via the SN65HVD75DR chip, and TVS diodes D1-D4 are connected in parallel between signal lines A and B; the RS-232 interface is connected to the processor's UART2 port via the MAX3232ESE chip (U17); the analog input interface is connected to the processor's SPI bus via the ADC0832 analog-to-digital converter; the VIN pin of the AXP221S power management chip is connected to the 12V DC input interface, the VBAT pin is connected to the lithium battery interface, and the ENABLE pin is connected to the GPIO1 pin of the Allwinner A40i-H processor; RT8279GS The P chip's VIN terminal is connected to a 12V input, and its output is split into two paths: the first path outputs 5V_Relay to the relay array via the L1 inductor, and the second path outputs 3.3V_MCU to the processor; the coil terminals of the four relays are connected to the processor's GPIO group via the ULN2803 driver chip, and the contact terminals are connected to the output interface; the 4G module is connected to the processor's PCIe bus via a Mini-PCIE socket, and the RTL8201F-VB-CG Ethernet PHY chip is connected to the processor via the RMII interface; the EN terminal of the RT8279GSP chip is connected to the processor's GPIO2 pin, and its feedback terminal FB sets the output voltage through a resistor divider network R1 / R2; the RE / DE pins of the RS-485 interface chip U6 are connected in parallel to the processor's GPIO3 pin to achieve automatic switching between transmit and receive modes.

Images