Active equalization PWM interlocking control circuit

Abstract

The utility model discloses an active equalization PWM interlocking control circuit comprising a first time-delay circuit, a first switch circuit and a first isolation circuit which are connected in sequence, and a second time-delay circuit, a second switch circuit and a second isolation circuit which are connected in sequence. The active equalization PWM interlocking control circuit further comprises a drive circuit, the input end of the drive circuit is connected with the PWM signal output end of the MCU main control circuit, and the input end of the drive circuit is further connected with the output end of the first isolation circuit and the output end of the second isolation circuit. By using the active equalization PWM interlocking control circuit provided by the utility model, faults caused by abnormal operation of the MCU can be prevented, the damage of a hardware circuit caused by software failure can be effectively avoided, and the safety guarantee of a BMS management system can be enhanced to a certain extent.

Description

Technical Field

[0001] This utility model relates to the field of battery management system technology, specifically to an active balancing PWM interlock control circuit. Background Technology

[0002] In a battery management system (BMS), the performance and lifespan of a battery pack largely depend on the consistency of its individual battery cells. Active balancing, a key technology for improving battery consistency, effectively prevents overcharging, over-discharging, and other abnormal conditions within the battery pack, thereby extending its overall lifespan. Currently, transformer-based balancing schemes are widely used in battery management design due to their high efficiency and good balancing effect. This scheme typically employs a microcontroller unit (MCU) to implement precise control strategies.

[0003] However, in existing technologies, the MCU, as the control core, inevitably faces the risk of program crashes or unknown bugs. When the MCU malfunctions, if the protection mechanism of the PWM control circuit is inadequate, the equalization function may fail. In this case, voltage leakage may occur between battery cells within the battery pack, which can damage power components and control chips, and in severe cases, may cause short circuits, overheating, or even fires, posing a significant threat to the stability and safety of the battery system. Therefore, ensuring reliable protection measures for the PWM control circuit to prevent equalization failure and voltage leakage when the MCU malfunctions has become a pressing technical challenge in current battery management design. Utility Model Content

[0004] The purpose of this invention is to provide an active equalization PWM interlock control circuit to solve at least one technical problem in the prior art.

[0005] The technical solution provided by this utility model is as follows:

[0006] An active equalization PWM interlock control circuit includes: a first delay circuit, a first switching circuit, and a first isolation circuit connected in sequence; and a second delay circuit, a second switching circuit, and a second isolation circuit connected in sequence.

[0007] The input terminals of the first delay circuit and the second circuit are connected to the PWM signal output terminal of the MCU main control circuit;

[0008] The active equalization PWM interlock control circuit also includes a drive circuit. The input terminal of the drive circuit is connected to the PWM signal output terminal of the MCU main control circuit, and the input terminal of the drive circuit is also connected to the output terminals of the first isolation circuit and the second isolation circuit.

[0009] Preferably, a protection circuit is connected between the input terminal of the driving circuit and the PWM signal output terminal of the MCU main control circuit.

[0010] Preferably, the protection circuit is a voltage regulation protection circuit.

[0011] In one specific implementation, the first delay circuit and the second delay circuit are RC delay circuits.

[0012] Preferably, the RC delay circuit is connected to a fast discharge circuit for rapidly discharging the capacitor.

[0013] In one specific implementation, the fast discharge circuit consists of a resistor and a diode connected in series.

[0014] In one specific implementation, the first isolation circuit and the second isolation circuit are composed of diodes.

[0015] In one specific implementation, the first switching circuit and the second switching circuit include a MOSFET or a transistor.

[0016] Compared with the prior art, the active equalization PWM interlock control circuit provided by this utility model has the following advantages:

[0017] By utilizing the aforementioned active equalization PWM interlock control circuit, faults caused by abnormal MCU operation can be prevented, hardware circuit damage caused by software failure can be effectively avoided, and the security of the BMS management system can be enhanced to a certain extent. Attached Figure Description

[0018] Figure 1 A schematic block diagram of the active equalization PWM interlock control circuit described in this embodiment of the present invention;

[0019] Figure 2 This is a detailed circuit diagram of the active equalization PWM interlock control circuit described in the embodiments of this utility model.

[0020] The reference numerals in the attached diagram are as follows: 10, main control circuit; 20, first delay circuit; 21, first switching circuit; 22, first isolation circuit; 30, second delay circuit; 31, second switching circuit; 32, second isolation circuit; 40, protection circuit; 50, drive circuit. Detailed Implementation

[0021] To better understand the purpose, technical solution, and technical effects of this utility model, the following description, in conjunction with the accompanying drawings and embodiments, will provide further explanation. It should also be stated that the embodiments described below are for illustrative purposes only and are not intended to limit the scope of this utility model. Example

[0022] like Figure 1 As shown, an active equalization PWM interlock control circuit includes: a first delay circuit, a first switching circuit and a first isolation circuit connected in sequence, and a second delay circuit, a second switching circuit and a second isolation circuit connected in sequence.

[0023] The input terminals of the first delay circuit and the second circuit are connected to the PWM signal output terminal of the MCU main control circuit;

[0024] The active equalization PWM interlock control circuit also includes a drive circuit. The input terminal of the drive circuit is connected to the PWM signal output terminal of the MCU main control circuit, and the input terminal of the drive circuit is also connected to the output terminals of the first isolation circuit and the second isolation circuit.

[0025] In a preferred embodiment, a protection circuit is connected between the input terminal of the drive circuit and the PWM signal output terminal of the MCU main control circuit. Specifically, the protection circuit is a voltage regulation protection circuit, which is used to provide voltage regulation protection for the drive circuit. Additionally, a current-limiting resistor can be provided between the input terminal of the drive circuit and the PWM signal output terminal of the MCU main control circuit to provide overcurrent protection for the drive circuit.

[0026] In one specific embodiment, the first delay circuit and the second delay circuit are RC delay circuits. In a preferred embodiment, the RC delay circuit is connected to a fast discharge circuit for rapidly discharging the capacitor. In one specific embodiment, the fast discharge circuit consists of a resistor and a diode connected in series.

[0027] In one specific implementation, the first isolation circuit and the second isolation circuit are composed of diodes.

[0028] In one specific implementation, the first switching circuit and the second switching circuit include a MOSFET or a transistor.

[0029] The active equalization PWM interlock control circuit provided in this embodiment is applied in a transformer-based equalization scheme. It is connected to the PWM signal output terminal of the MCU main control circuit. Specifically, the input terminals of the first delay circuit and the second delay circuit are connected to the PWM signal output terminal of the MCU main control circuit. By forcibly flipping the PWM signal of the MCU main control circuit through the first delay circuit and the second delay circuit, the two PWM signals of the MCU main control circuit are prevented from having the same high and low levels in the same time period. This can prevent faults caused by abnormal MCU operation, effectively avoid damage to hardware circuits caused by software failure, and also enhance the security of the BMS management system to a certain extent.

[0030] During normal operation, this active equalization PWM interlock control circuit will not forcibly toggle the PWM signal of the MCU main control circuit. If the PWM signal of the MCU main control circuit exceeds the delay time of the hardware circuit, the circuit will forcibly toggle the PWM signal to prevent two PWM signals from having the same high and low levels at the same time. It should be noted that the delay times of the first and second delay circuits are longer than the transition time of the control signal of the MCU main control circuit to ensure the normal operation of the circuit.

[0031] In one specific implementation, as shown in the appendix Figure 2 As shown, the first delay circuit 20, the first switch circuit 21, and the first isolation circuit 22 are connected in sequence, as are the second delay circuit 30, the second switch circuit 31, and the second isolation circuit 32. The input terminals of the first delay circuit and the second circuit are connected to the PWM signal output terminal of the MCU main control circuit 10. The input terminal of the drive circuit 50 is connected to the PWM signal output terminal of the MCU main control circuit through the protection circuit 40, and the input terminal of the drive circuit 50 is also connected to the output terminals of the first isolation circuit 22 and the second isolation circuit 32.

[0032] In this specific embodiment, the driver chip of the driving circuit is SGM4800. The first delay circuit 20 consists of resistor BR3 and capacitor BC1, and the second delay circuit 30 consists of resistor BR7 and capacitor BC3. Resistor BR1 and diode D1 are connected in series to form a fast discharge circuit, as are resistor BR5 and diode D2. MOSFET EM1 and resistor BR2 form a first switching circuit, MOSFET EM2 and resistor BR4 form a second switching circuit, diodes BD1 and BD2 form a first isolation circuit, diodes BD3 and BD4 form a second isolation circuit, and Zener diodes BZ1 and BZ2 form a voltage regulation protection circuit. The specific connection relationships of each electronic component are shown in the attached figure. Figure 2 As shown, further details will not be provided here. Among them, in the appendix... Figure 1 and attached Figure 2 In the diagram, nodes PWM_H and PWM_L are the two PWM signal output terminals of the MCU main control circuit.

[0033] The following is a brief description of the working process or working principle of the active equalization PWM interlock control circuit provided in this embodiment:

[0034] As attached Figure 2As shown, in the PWM signal output, when PWM_H is high and PWM_L is low, MOSFET EM1 is off. The high-level PWM_H signal drives MOSFET EM2 to turn on after passing through the RC delay circuit composed of resistor BR7 and capacitor BC3, thus pulling the PWM_H signal low. Similarly, when PWM_H is low and PWM_L is high, MOSFET EM2 is off. The high-level PWM_L signal drives MOSFET EM1 to turn on after passing through the RC delay circuit composed of resistor BR3 and capacitor BC1, thus pulling the PWM_L signal low. Since PWM_H and PWM_L signals are inverse outputs, if one of them does not turn low after a certain time, it will be forcibly pulled low through the current. This ensures that the two PWM signals cannot simultaneously turn on the equalizing MOSFET, thus avoiding the situation where both MOSFETs are conducting at the same time. This prevents malfunctions caused by abnormal MCU operation, effectively avoids hardware circuit damage caused by software failure, and also strengthens the security of the BMS management system to a certain extent. It should be noted that the delay time of the RC delay circuit mentioned above is longer than the control signal transition time of the MCU main control circuit, in order to ensure the normal operation of the circuit.

[0035] The above embodiments only illustrate several implementation methods of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. An active equalization PWM interlock control circuit, characterized in that, It includes a first delay circuit, a first switching circuit, and a first isolation circuit connected in sequence, and a second delay circuit, a second switching circuit, and a second isolation circuit connected in sequence. The input terminals of the first delay circuit and the second circuit are connected to the PWM signal output terminal of the MCU main control circuit; The active equalization PWM interlock control circuit also includes a drive circuit. The input terminal of the drive circuit is connected to the PWM signal output terminal of the MCU main control circuit, and the input terminal of the drive circuit is also connected to the output terminals of the first isolation circuit and the second isolation circuit.

2. The active equalization PWM interlock control circuit according to claim 1, characterized in that, A protection circuit is connected between the input terminal of the drive circuit and the PWM signal output terminal of the MCU main control circuit.

3. The active equalization PWM interlock control circuit according to claim 2, characterized in that, The protection circuit is a voltage regulation protection circuit.

4. The active equalization PWM interlock control circuit according to claim 1, characterized in that, The first delay circuit and the second delay circuit are RC delay circuits.

5. The active equalization PWM interlock control circuit according to claim 4, characterized in that, The RC delay circuit is connected to a fast discharge circuit for rapidly discharging the capacitor.

6. The active equalization PWM interlock control circuit according to claim 4, characterized in that, The fast discharge circuit consists of a resistor and a diode connected in series.

7. The active equalization PWM interlock control circuit according to claim 1, characterized in that, The first isolation circuit and the second isolation circuit are composed of diodes.

8. The active equalization PWM interlock control circuit according to claim 6, characterized in that, The first and second switching circuits include MOSFETs or transistors.

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