Power semiconductor device

Abstract

The utility model relates to the technical field of semiconductor devices, and discloses a power semiconductor device, which comprises a substrate, a chip, a power pin, a first signal pin and a second signal pin, the chip is arranged on the substrate and is electrically connected with the power pin, the first signal pin and the second signal pin; the first signal pin and the power pin are arranged on the same side surface of the substrate; the second signal pin and the power pin are arranged on different side surfaces of the substrate. The first signal pins and the power pins are arranged on the same side surface of the substrate, so that the length of a signal transmission path can be reduced, signal delay and interference are reduced, and the efficiency and reliability of signal transmission are improved. The second signal pin and the power pin are arranged on different side surfaces of the substrate, so that a multi-pin design can be realized, the welding stability of the power semiconductor device is improved, and the through-current capability and the high-power tolerance capability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and for example to a power semiconductor device. Background Technology

[0002] Currently, with the rapid development of the power electronics industry's high-quality and high-reliability requirements, the demands on highly integrated and high-performance semiconductor devices are becoming increasingly stringent. The operating environment of these devices is susceptible to numerous external factors that can lead to device failure. Non-hermetic semiconductor packaged devices mainly consist of a frame, solder, chip, molding compound, and DBC (Direct Bonded Copper) materials. Each material has different characteristics, and devices generate heat during use due to their own properties or external factors. When power devices experience temperature increases or are affected by circuit noise during operation, there is a certain probability of damage, failure, or a reduction in device lifespan.

[0003] In related technologies, the packaging structure of power devices is mostly bottom-mount or through-hole.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] Due to limitations in packaging structure, the current-carrying capacity and high-power tolerance of devices in related technologies are restricted.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a power semiconductor device to improve the device's current carrying capacity and high power tolerance.

[0009] In some embodiments, the power semiconductor device includes: a substrate, a chip, a power pin, a first signal pin, and a second signal pin; the chip is disposed on the substrate and electrically connected to the power pin, the first signal pin, and the second signal pin; the first signal pin and the power pin are disposed on the same side of the substrate; the second signal pin and the power pin are disposed on different sides of the substrate.

[0010] Optionally, the setting distance between the power pin and the first signal pin is greater than the setting distance between two adjacent second signal pins.

[0011] Optionally, the first signal pin and the power pin are disposed on the first side of the substrate; the second signal pin is disposed on one or more of the second side, the third side, and the fourth side of the substrate; wherein the second side is disposed adjacent to the first side, the third side is disposed opposite to the first side, and the fourth side is disposed opposite to the second side.

[0012] Optionally, the second signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin; and the first signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is located on the side away from the power pin.

[0013] Optionally, there may be multiple first signal pins, which are located on both sides of the power pin.

[0014] Optionally, there may be multiple power pins, which are located on both sides of the first signal pin.

[0015] Optionally, the power pin is the drain potential, and the first signal pin and the second signal pin are the gate potential and the source potential, respectively.

[0016] Optionally, the power semiconductor device further includes: an insulating heat sink disposed on a substrate, wherein the heat dissipation surface of the insulating heat sink is disposed facing upward.

[0017] The power semiconductor device provided in this disclosure can achieve the following technical effects:

[0018] In this embodiment, the power semiconductor device includes a substrate, a chip, power pins, a first signal pin, and a second signal pin. All power pins are disposed on the same side of the substrate, and one side of the power pins includes at least one or more first signal pins. The fact that the first signal pins and power pins are disposed on the same side of the substrate reduces the length of the signal transmission path, thereby reducing signal delay and interference, and improving the efficiency and reliability of signal transmission. The second signal pins are disposed on different sides of the substrate than the power pins, enabling a multi-pin design, improving the soldering stability of the power semiconductor device, and enhancing the device's current-carrying capacity and high-power tolerance.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0021] Figure 1 This is a schematic diagram of a power semiconductor device provided in an embodiment of this disclosure;

[0022] Figure 2 This is a schematic diagram of the pin layout of a power semiconductor device provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of the pin layout of another power semiconductor device provided in an embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram of the pin layout of another power semiconductor device provided in an embodiment of this disclosure;

[0025] Figure 5 This is a schematic diagram of the pin layout of another power semiconductor device provided in an embodiment of this disclosure;

[0026] Figure 6 This is a schematic diagram of the pin layout of another power semiconductor device provided in an embodiment of this disclosure;

[0027] Figure 7 This is an internal equivalent circuit diagram of a power semiconductor device provided in an embodiment of this disclosure.

[0028] Reference numerals: 10, substrate; 20, chip; 30, power pin; 41, first signal pin; 42, second signal pin. Detailed Implementation

[0029] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0030] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0031] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0032] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0033] Unless otherwise stated, the term "multiple" means two or more.

[0034] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0035] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0037] Combination Figure 1As shown, this embodiment of the present disclosure provides a power semiconductor device, including a substrate 10, a chip 20, a power pin 30, a first signal pin 41, and a second signal pin 42. The chip 20 is disposed on the substrate 10 and electrically connected to the power pin 30, the first signal pin 41, and the second signal pin 42. The first signal pin 41 and the power pin 30 are disposed on the same side of the substrate 10; the second signal pin 42 and the power pin 30 are disposed on different sides of the substrate 10.

[0038] Combination Figure 1 As shown, in this embodiment, all power pins 30 are disposed on the same side of the substrate 10, and one or more first signal pins 41 are included on one side of the power pins 30. The first signal pins 41 and power pins 30 being disposed on the same side of the substrate 10 reduces the length of the signal transmission path, thereby reducing signal delay and interference, and improving the efficiency and reliability of signal transmission. Second signal pins 42 and power pins 30 are disposed on different sides of the substrate 10, enabling a multi-pin design, improving the soldering stability of the power semiconductor device, and enhancing the device's current carrying capacity and high power tolerance.

[0039] Optionally, the setting distance between the power pin 30 and the first signal pin 41 is greater than the setting distance between two adjacent second signal pins 42.

[0040] Combination Figure 1 As shown, in this embodiment, the distance H between the power pin 30 and the first signal pin 41 is greater than the distance h between two adjacent second signal pins 42, which can reduce electromagnetic interference and signal crosstalk between the power pin 30 and the first signal pin 41, and improve the clarity and integrity of the signal.

[0041] Optionally, the substrate 10 is made of DBC material. A suitable layout can be made on the substrate 10 depending on the number of chips 20 and pins.

[0042] Optionally, the first signal pin 41 and the power pin 30 are disposed on the first side of the substrate 10; the second signal pin 42 is disposed on one or more of the second side, the third side, and the fourth side of the substrate 10; wherein the second side is disposed adjacent to the first side, the third side is disposed opposite to the first side, and the fourth side is disposed opposite to the second side.

[0043] In this embodiment, the package layout of the power semiconductor device includes two-sided, three-sided, and four-sided lead schemes. Suitable for diverse application circuits, the power semiconductor device can flexibly choose a suitable package layout. This disclosure does not limit the number or width of the leads; reasonable settings can be made according to different actual needs. Furthermore, for better soldering conditions, the shape and structural morphology of the leads are not limited, such as designs with wider surface areas, through-holes in the center, or grooves on the sides. Combined with... Figure 1 The diagram shows the four-sided pin package layout of a power semiconductor device. For two-sided and three-sided pin package layouts, it is only necessary to remove the pin layout on one or two sides of the substrate 10.

[0044] Optionally, combined Figure 2 As shown, the design scheme of the two-sided pins includes: the first signal pin 41 and the power pin 30 are disposed on the first side of the substrate 10; the second signal pin 42 is disposed on one of the second side, the third side, and the fourth side of the substrate 10.

[0045] Optionally, combined Figure 3 As shown, the three-sided pin design includes: the first signal pin 41 and the power pin 30 are disposed on the first side of the substrate 10; the second signal pin 42 is disposed on any two of the second, third and fourth sides of the substrate 10.

[0046] Optionally, combined Figure 4 As shown, the four-sided pin design includes: a first signal pin 41 and a power pin 30 disposed on the first side of the substrate 10; and a second signal pin 42 disposed on the second, third, and fourth sides of the substrate 10.

[0047] In this embodiment, by selecting an appropriate package layout according to the needs of different application circuits, the power semiconductor device can adapt to various circuit designs. In a two-sided pin design, pins are provided on two opposite or adjacent sides of the device, suitable for applications requiring double-sided connections. In a three-sided pin design, pins are provided on three sides of the device, providing more connection options for circuit design. In a four-sided pin design, pins are provided on all four sides of the device, suitable for applications with compact space and requiring omnidirectional connections. In this way, the power semiconductor device can be flexibly integrated into various circuits, improving the device's versatility and applicability. By providing different numbers of pin configurations, the most suitable package layout can be selected according to the specific circuit design and space constraints, thereby optimizing the performance and reliability of the entire system.

[0048] Optionally, the second signal pin 42 includes one or more of a G signal pin, an S signal pin, and a K signal pin; and the first signal pin 41 includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is located on the side away from the power pin 30. The G signal pin represents the gate and is used to receive the gate signal. The S signal pin represents the source and is used to receive the source signal. The K signal pin represents the Kelvin pin and is used for a drive circuit or a measurement circuit.

[0049] In this embodiment, depending on different circuit requirements, the first signal pin 41 and the second signal pin 42 can be configured as one or more of the following: G signal pin, S signal pin, and K signal pin. The Kelvin pin is used to monitor and control the power device. To reduce interference from the power pin 30 to the Kelvin pin, the Kelvin pin needs to be placed on a different side from the power pin 30, or as far away from the power pin 30 as possible. Since the power pin 30 generates a strong electromagnetic field when transmitting large currents, this may cause electromagnetic interference to nearby signal pins. By physically isolating the Kelvin pin from the power pin 30, electromagnetic coupling between them can be reduced, thereby reducing interference. Reducing interference can improve the accuracy and stability of the Kelvin pin, thus ensuring the correct operation and performance of the power device. In high-speed or high-frequency applications, signal accuracy is particularly important for the response time and reliability of the device. Furthermore, reducing interference on the signal pin can also reduce the extra time required for the device to process signals, thereby increasing switching speed and improving the overall efficiency of the system. Therefore, arranging the Kelvin pin and the power pin 30 on different sides or away from the power pin 30 can effectively reduce the interference of the power pin 30 on the signal pin, improve the accuracy and stability of the signal, and thus improve the switching speed and overall performance of the device.

[0050] Optionally, depending on the specific application requirements, it may be necessary to configure the K signal pin.

[0051] In this embodiment, the K-signal pin is not essential in power semiconductor devices. In applications requiring precise control of the switching states of power devices, such as complex power electronic converters, a K-signal pin is necessary to receive control signals. However, for simpler applications where additional control or monitoring functions are not required, the K-signal pin can be omitted to simplify design and reduce costs.

[0052] Optionally, combined Figure 5 As shown, there are multiple first signal pins 41, which are located on both sides of the power pin 30.

[0053] In this embodiment, isolating the first signal pin 41 through the power pin 30 reduces direct electromagnetic coupling between the two first signal pins 41, thereby reducing interference between them, improving signal integrity, and ultimately reducing the bit error rate and improving data transmission reliability. Furthermore, Figure 5 The diagram shows a four-sided pin design scheme, which can be adapted to different practical requirements. Figure 2 , Figure 3 , Figure 4 The content can be Figure 5 The design scheme was modified to a suitable two-sided or three-sided pin design scheme.

[0054] Optionally, combined Figure 6 As shown, there are multiple power pins 30, which are located on both sides of the first signal pin 41.

[0055] Placing the first signal pin 41 between the power pins 30 serves as a physical barrier, reducing direct electromagnetic interference between the power pins 30 and minimizing mutual influence. By placing the first signal pin 41 between the two power pins 30, power can be distributed more evenly, preventing any single power pin 30 from experiencing excessive current or voltage loads, thus improving the overall performance and reliability of the device. Furthermore, Figure 6 The diagram shows a four-sided pin design scheme, which can be adapted to different practical requirements. Figure 2 , Figure 3 , Figure 4 The content can be Figure 6 The design scheme was modified to a suitable two-sided or three-sided pin design scheme.

[0056] Optionally, power pin 30 is the drain potential, and first signal pin 41 and second signal pin 42 are the gate potential and source potential, respectively.

[0057] The equivalent circuit diagram inside a power semiconductor device is as follows: Figure 7 As shown, C is the power electrode of the device, corresponding to power pin 30, and serves as the drain potential of the device; G, E, and K are the signal electrodes of the device, corresponding to the first signal pin 41 and the second signal pin 42, and serve as the gate potential and source potential of the device, respectively. G corresponds to the G signal pin, E corresponds to the S signal pin, and K corresponds to the K signal pin.

[0058] Optionally, the power semiconductor device further includes an insulating heat sink disposed on the substrate 10, wherein the heat dissipation surface of the insulating heat sink is disposed facing upward.

[0059] In this embodiment, the insulating heat sink can improve the heat dissipation efficiency of the device, thereby enhancing its performance and reliability. The insulating heat sink provides an effective heat dissipation path, conducting away the heat generated during device operation to reduce its operating temperature. Positioning the insulating heat sink upwards, with the heat dissipation surface facing upwards towards the device, allows for more direct heat transfer to the surrounding air or to the heat dissipation structure above the heat sink, contributing to improved heat transfer efficiency. When designing power semiconductor devices, the shape, size, material, and connection method of the insulating heat sink to the substrate 10 need to be comprehensively considered to achieve optimal thermal management. The heat sink design may include fins, grooves, or other features that enhance heat conduction to improve heat dissipation efficiency.

[0060] Optionally, the power semiconductor devices provided in this disclosure can be applied to different application fields and scenarios, including: automobiles, photovoltaics, charging piles, wind power, energy storage, etc.

[0061] Optionally, the number of chips 20 in the power semiconductor device may include one or more.

[0062] Optionally, the power semiconductor devices provided in this disclosure can be applied to IC (Integrated Circuit) chips, thermistors, IGBTs (Insulated Gate Bipolar Transistors), FRDs (Fast Recovery Diodes), MOS (Metal-Oxide-Semiconductors), BJTs (Bipolar Junction Transistors), SCRs (Silicon Controlled Rectifiers), and other devices. These include single-device products, half-bridge circuits, and full-bridge circuit designs.

[0063] This disclosure also provides a method for fabricating a power semiconductor device, comprising: fixing a chip onto a substrate to form a preliminary electrical connection between the chip and the substrate; configuring the pin layout on the substrate according to the requirements of the application circuit; electrically connecting the power electrode of the power chip to the power pin; and connecting the signal electrode of the power chip to the first signal pin and the second signal pin to form an electrical signal path.

[0064] Optionally, the chip is fixed to the substrate, including fixing the chip to the substrate by means of solder, conductive adhesive, silver paste, solder pads, etc.

[0065] Alternatively, the pin layout on the substrate can be configured according to the pin layout in the power semiconductor device described above.

[0066] Optionally, the pins include a power pin, a first signal pin, and a second signal pin; the pin layout includes: the first signal pin and the power pin are disposed on the same side of the substrate, and the second signal pin and the power pin are disposed on different sides of the substrate.

[0067] Optionally, the setting distance between the power pin and the first signal pin is greater than the setting distance between two adjacent second signal pins.

[0068] Optionally, the first signal pin and the power pin are disposed on the first side of the substrate; the second signal pin is disposed on one or more of the second side, the third side, and the fourth side of the substrate; wherein the second side is disposed adjacent to the first side, the third side is disposed opposite to the first side, and the fourth side is disposed opposite to the second side.

[0069] Optionally, the second signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin; and the first signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is located on the side away from the power pin.

[0070] Optionally, depending on the specific application requirements, it may be necessary to configure the K signal pin.

[0071] Optionally, there may be multiple first signal pins, which are located on both sides of the power pin.

[0072] Optionally, there may be multiple power pins, which are located on both sides of the first signal pin.

[0073] Optionally, the power electrode of the power chip is electrically connected to the power pin, including: the power electrode of the power chip is directly connected to the power pin; or, the power electrode of the power chip is interconnected with the power pin by wire bonding or sintering.

[0074] Optionally, connecting the signal electrode of the power chip to the first signal pin and the second signal pin includes: connecting the signal electrode of the power chip to the first signal pin and the second signal pin by bonding or sintering; or connecting the signal electrode of the power chip to the first signal pin and the second signal pin by copper wire bonding.

[0075] Optionally, the method for fabricating a power semiconductor device further includes: setting an insulating heat sink with its heat dissipation surface facing upward within a substrate.

[0076] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A power semiconductor device, characterized in that, include: Substrate, chip, power pin, first signal pin, second signal pin; The chip is mounted on the substrate and is electrically connected to the power pin, the first signal pin, and the second signal pin. The first signal pin and the power pin are located on the same side of the substrate; The second signal pin and the power pin are located on different sides of the substrate; The setting distance between the power pin and the first signal pin is greater than the setting distance between two adjacent second signal pins; The second signal pin includes one or more of the G signal pin and the S signal pin; and the first signal pin includes one or more of the G signal pin and the S signal pin; the G signal pin represents the gate and is used to receive the gate signal; the S signal pin represents the source and is used to receive the source signal; the power pin is the drain potential.

2. The power semiconductor device according to claim 1, characterized in that, The first signal pin and the power pin are disposed on the first side of the substrate; The second signal pin is disposed on one or more of the second side, third side, and fourth side of the substrate; The second side is adjacent to the first side, the third side is opposite to the first side, and the fourth side is opposite to the second side.

3. The power semiconductor device according to claim 1, characterized in that, The second signal pin also includes a K signal pin; and the first signal pin also includes a K signal pin; wherein the K signal pin is located on the side away from the power pin.

4. The power semiconductor device according to claim 3, characterized in that, There are multiple first signal pins, which are located on both sides of the power pins.

5. The power semiconductor device according to claim 3, characterized in that, There are multiple power pins, which are located on both sides of the first signal pin.

6. The power semiconductor device according to any one of claims 1 to 5, characterized in that, The power pin is the drain potential, and the first signal pin and the second signal pin are the gate potential and the source potential, respectively.

7. The power semiconductor device according to any one of claims 1 to 5, characterized in that, Also includes: An insulating heat sink is disposed on the substrate, with the heat dissipation surface of the insulating heat sink facing upwards.

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