EMMC storage device and electronic equipment

Abstract

The embodiment of the utility model provides an eMMC storage device and electronic equipment, the eMMC storage device comprises a processing unit, a conversion circuit, a switch unit and N eMMC, the N eMMC comprises a first eMMC and a second eMMC, and N is an integer greater than or equal to 2; the first output end of the processing unit is connected with the first end of the conversion circuit, the second end of the conversion circuit is connected with the first end of the switch unit, the second end of the switch unit is connected with the first end of the first eMMC, and the third end of the switch unit is connected with the first end of the second eMMC; and the switch unit is used for realizing communication between the processing unit and one of the N eMMC.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to an eMMC storage device and electronic device. Background Technology

[0002] Traditional embedded multi-media card (eMMC) storage devices are storage devices with eMMC soldered on. This storage device can be connected to the card slot of a TransFlash (TF) card, and the information to be stored can be stored on the eMMC through a TF to eMMC conversion circuit. However, since the eMMC on this storage device is soldered on, if there is more than one eMMC in the eMMC storage device, multiple TF to eMMC conversion circuits are required to store information on multiple eMMCs.

[0003] Therefore, there is an urgent need for a feasible solution that can use a single TF-to-eMMC converter circuit to store information on multiple eMMCs. Utility Model Content

[0004] This application provides an eMMC storage device and an electronic device, enabling the eMMC storage device to store information on multiple eMMCs using a single conversion circuit.

[0005] A first aspect of this application provides an eMMC storage device, comprising:

[0006] The system includes a processing unit, a conversion circuit, a switching unit, and N eMMCs, wherein the N eMMCs include a first eMMC and a second eMMC, and N is an integer greater than or equal to 2.

[0007] The first output terminal of the processing unit is connected to the first terminal of the conversion circuit, the second terminal of the conversion circuit is connected to the first terminal of the switching unit, the second terminal of the switching unit is connected to the first terminal of the first eMMC, and the third terminal of the switching unit is connected to the first terminal of the second eMMC; the switching unit is used to enable the processing unit to connect to one of the N eMMCs.

[0008] Optionally, the eMMC storage device further includes: a switch control unit;

[0009] The second output terminal of the processing unit is connected to the first terminal of the switch control unit, and the second terminal of the switch control unit is connected to the control terminal of the switch unit.

[0010] The switch control unit is used to convert the control command output by the processing unit into a switching command. The switching command is used to control the state of the switch unit so that the processing unit can be connected to one of the N eMMCs.

[0011] Optionally, the eMMC storage device further includes N slots, each corresponding to one of the N eMMCs.

[0012] Optionally, the N slots include a first slot and a second slot, the first slot being provided with a first limiting frame and the second slot being provided with a second limiting frame; the first limiting frame is used to fix the first eMMC and the second limiting frame is used to fix the second eMMC.

[0013] Optionally, the size of the first limiting frame is adapted to the size of the first eMMC, and the size of the second limiting frame is adapted to the size of the second eMMC.

[0014] Optionally, the first limiting frame and the second limiting frame may have different or the same dimensions.

[0015] Optionally, the eMMC storage device further includes M flip structures, wherein when the flip structures are in the flip state, the slots can be used to insert eMMC; M is an integer less than or equal to N.

[0016] Optionally, the eMMC storage device further includes N ejection structures, including a first ejection structure and a second ejection structure; the first slot is disposed within the first ejection structure, and the second slot is disposed within the second ejection structure;

[0017] When the first pop-up structure is in the pop-up state, the first eMMC can be inserted into the first slot;

[0018] When the second pop-up structure is in the pop-up state, the second eMMC can be inserted into the second slot.

[0019] Optionally, the switching instructions may include binary instructions.

[0020] A second aspect of this application provides an electronic device that includes an eMMC storage device as described in the first aspect.

[0021] In this embodiment, the eMMC storage device switches the state of the switching unit so that when the first end of the switching unit is connected to the second end of the switching unit, the processing unit is connected to the first eMMC. The storage signal received by the processing unit is converted into a storage signal of the eMMC protocol by the conversion circuit and then transmitted to the first eMMC. After receiving the storage signal of the eMMC protocol, the first eMMC can store information in the first eMMC or retrieve information stored in the first eMMC.

[0022] When the first terminal of the switching unit is connected to the third terminal of the switching unit, the processing unit is connected to the second eMMC. The storage signal received by the processing unit is converted into a storage signal of the eMMC protocol by the conversion circuit and then transmitted to the second eMMC. After receiving the storage signal of the eMMC protocol, the second eMMC can store information in the second eMMC or retrieve information stored in the second eMMC.

[0023] By following the steps above, information can be stored on multiple eMMCs using a single conversion circuit by switching the state of the switching unit in the eMMC storage device. This avoids the need for multiple conversion circuits, with each conversion circuit connected to one eMMC, thus reducing the cost when information needs to be stored on multiple eMMCs. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of the structure of a conventional eMMC storage device provided in this application embodiment;

[0026] Figure 2 A schematic diagram of the structure of an eMMC storage device provided in an embodiment of this application;

[0027] Figure 3 A schematic diagram of another eMMC storage device provided in this application embodiment;

[0028] Figure 4 This is a schematic diagram illustrating how an upgrade testing device can be used to upgrade a driver or perform read / write speed tests, as provided in an embodiment of this application.

[0029] Figure 5 This is a schematic diagram illustrating a driver upgrade using an upgrade testing device, as provided in an embodiment of this application.

[0030] Figure 6 This is a schematic diagram illustrating another method of upgrading a driver using an upgrade testing device, as provided in an embodiment of this application.

[0031] Figure 7 This is a schematic diagram illustrating a failure to upgrade a driver using an upgrade testing device, as provided in an embodiment of this application.

[0032] Figure 8 A schematic diagram illustrating a read / write speed test using an upgraded testing device, provided as an embodiment of this application;

[0033] Figure 9 This is a schematic diagram illustrating a sequential read test using an upgraded testing device, as provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0036] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0037] It should be understood that eMMC is an embedded memory chip. In order to use the eMMC chip as a portable external storage device, the eMMC needs to be soldered into the eMMC storage device so that the eMMC can be connected to the conversion circuit. The conversion circuit converts the received storage signal into the storage signal of the eMMC protocol, so that the eMMC can realize storage based on the storage signal of the eMMC protocol.

[0038] Please see Figure 1 , Figure 1 This is a schematic diagram of a conventional eMMC storage device provided in an embodiment of this application. The eMMC storage device includes a processing unit, a conversion circuit, and an eMMC. A first terminal of the processing unit is connected to a first terminal of the conversion circuit, and a second terminal of the conversion circuit is connected to the eMMC.

[0039] The processing unit is used to receive the stored signal and send the stored signal to the conversion circuit.

[0040] The conversion circuit converts the received storage signal into the eMMC protocol storage signal and sends the eMMC protocol storage signal to the eMMC.

[0041] Optionally, the conversion circuit is a conversion circuit that converts the SD protocol to the eMMC protocol. By inserting the eMMC storage device into the card slot of the TF card or microSD card, the processing unit receives the storage signal of the SD protocol output from the output terminal of the card slot of the TF card or microSD card, and the conversion circuit converts the storage signal of the SD protocol into the storage signal of the eMMC protocol.

[0042] When an eMMC receives a storage signal from the eMMC protocol, it can store information in the eMMC or retrieve information stored in the eMMC.

[0043] When the storage space of a single eMMC is insufficient and information needs to be stored on multiple eMMCs, the processing unit needs to be connected to multiple conversion circuits. Each conversion circuit is connected to an eMMC, so that the storage signal received by the processing unit can be transmitted to any eMMC. However, the multiple conversion circuits required by this implementation method result in a higher cost for the eMMC storage device.

[0044] Please see Figure 2 , Figure 2 This is a schematic diagram of an eMMC storage device provided in an embodiment of this application. The device includes a processing unit 10, a conversion circuit 20, a switching unit 30, a first eMMC 40, and a second eMMC 50. The processing unit 10 includes a first output terminal 11 and an input terminal 12. The conversion circuit 20 includes a first terminal 21 and a second terminal 22. The switching unit 30 includes a first terminal 31, a second terminal 32, and a third terminal 33. The first eMMC 40 includes a first terminal 41, and the second eMMC 50 includes a first terminal 51.

[0045] The first output terminal 11 of the processing unit 10 is connected to the first terminal 21 of the conversion circuit 20, the second terminal 22 of the conversion circuit 20 is connected to the first terminal 31 of the switching unit 30, the second terminal 32 of the switching unit 30 is connected to the first terminal 41 of the first eMMC 40, and the third terminal 33 of the switching unit 30 is connected to the first terminal 51 of the second eMMC 50.

[0046] The processing unit 10 receives the stored signal through the input terminal 12 and outputs the stored signal to the conversion circuit 20 through the first output terminal 11 of the processing unit 10.

[0047] The conversion circuit 20 is used to convert the received storage signal into an eMMC protocol storage signal and send the eMMC protocol storage signal to the first eMMC or the second eMMC.

[0048] Optionally, if the conversion circuit 20 includes a conversion circuit that converts the storage signal of the SD protocol into the storage signal of the eMMC protocol, the processing unit 10 receives the storage signal of the SD protocol through the input terminal 12 and transmits the storage signal of the SD protocol to the conversion circuit 20.

[0049] Alternatively, the input terminal of the processing unit 10 may be made of beryllium copper plated with gold to improve the conductivity and durability of the input terminal of the processing unit 10.

[0050] The switching unit 30 is used to enable the processing unit 10 to connect with the first eMMC 40 or the second eMMC 50.

[0051] When the first end 31 of the switching unit 30 is connected to the second end 32 of the switching unit 30, the processing unit 10 is connected to the first eMMC 40. The storage signal received by the processing unit 10 is converted into a storage signal of the eMMC protocol by the conversion circuit 20 and then transmitted to the first eMMC 40, thereby realizing the storage of information in the first eMMC 40.

[0052] When the first terminal 31 of the switching unit 30 is connected to the third terminal 33 of the switching unit 30, the processing unit 10 is connected to the second eMMC 50. The storage signal received by the processing unit is converted into a storage signal of the eMMC protocol by the conversion circuit 20 and then transmitted to the second eMMC 50, thereby realizing the storage of information in the second eMMC 50.

[0053] In one possible implementation, in addition to the first eMMC and the second eMMC, there are N-2 eMMCs in the eMMC storage device. The switching unit 30 also includes N-2 ports, any port of which is connected to an eMMC. Connecting the first end of the switching unit 30 to any end of the switching unit 30 other than the first end can enable the processing unit 10 to communicate with an eMMC.

[0054] In this embodiment, the eMMC storage device switches the state of the switching unit 30 so that when the first end 31 of the switching unit 30 is connected to the second end 32 of the switching unit 30, the processing unit 10 is connected to the first eMMC 40. The storage signal received by the processing unit 10 is converted into an eMMC protocol storage signal by the conversion circuit 20 and then transmitted to the first eMMC 40. After receiving the eMMC protocol storage signal, the first eMMC 40 can store information in the first eMMC 40 or retrieve information stored in the first eMMC 40.

[0055] When the first terminal 31 of the switching unit 30 is connected to the third terminal 33 of the switching unit 30, the processing unit 10 is connected to the second eMMC 50. The storage signal received by the processing unit 10 is converted into an eMMC protocol storage signal by the conversion circuit 20 and then transmitted to the second eMMC 50. After receiving the eMMC protocol storage signal, the second eMMC 50 can store information in the second eMMC 50 or retrieve information stored in the second eMMC 50.

[0056] By using the above steps, information can be stored on multiple eMMCs using a single conversion circuit 20 by switching the state of the switching unit 30 in the eMMC storage device. This avoids the need for multiple conversion circuits, with each conversion circuit connected to one eMMC, thus reducing the cost when information needs to be stored on multiple eMMCs.

[0057] Please see Figure 3 , Figure 3 This is a schematic diagram of another eMMC storage device provided in an embodiment of this application. The device includes a processing unit 10, a conversion circuit 20, a switching unit 30, a first eMMC 40, a second eMMC 50, and a switching control unit 60. The processing unit 10 includes a first output terminal 11, an input terminal 12, and a second output terminal 13. The conversion circuit 20 includes a first terminal 21 and a second terminal 22. The switching unit 30 includes a first terminal 31, a second terminal 32, a third terminal 33, and a control terminal 34. The first eMMC 40 includes a first terminal 41, the second eMMC 50 includes a first terminal 51, and the switching control unit 60 includes a first terminal 61 and a second terminal 62.

[0058] The first output terminal 11 of the processing unit 10 is connected to the first terminal 21 of the conversion circuit 20, the second terminal 22 of the conversion circuit 20 is connected to the first terminal 31 of the switching unit 30, the second terminal 32 of the switching unit 30 is connected to the first terminal 41 of the first eMMC 40, the third terminal of the switching unit 30 is connected to the first terminal 51 of the second eMMC 50, the second output terminal 13 of the processing unit 10 is connected to the first terminal 61 of the switch control unit 60, and the second terminal 62 of the switch control unit 60 is connected to the control terminal 34 of the switching unit 30.

[0059] The switch control unit 60 is used to convert the control commands of the processing unit 10 into switching commands, thereby controlling the switching state of the switch unit. Specifically, the second output terminal 13 of the processing unit 10 outputs a control command to switch the state of the switch unit to the first terminal 61 of the switch control unit 60. The switch control unit 60 converts the control command into a switching command and outputs it to the control terminal 34 of the switch unit 30 through the second terminal of the switch control unit 60. When the switch unit 30 receives the switching command output by the switch control unit 60, it switches the state of the switch unit 30 according to the switching command. Optionally, the control command output by the processing unit 10 is an analog signal. The switch control unit 60 converts the analog control command into a digital switching command and outputs the digital switching command to the switch unit 30.

[0060] In one possible implementation, the second terminal 62 of the switch control unit 60 is used to output binary instructions. When the second terminal 62 of the switch control unit 60 includes one output terminal, it can output either 0 or 1, two different binary instructions. These two different binary instructions can switch the switch unit 30 to two different states, enabling the processing unit 10 to connect to two different eMMCs. When the second terminal 62 of the switch control unit 60 includes two output terminals, it can output four different binary instructions: 00, 01, 10, and 11. These four different binary instructions can switch the switch unit 30 to four different states, enabling the processing unit 10 to connect to four different eMMCs.

[0061] Optionally, the eMMC storage device also includes N slots. These slots are used to insert eMMCs. Specifically, the N slots include a first slot and a second slot; the first slot is used to insert a first eMMC 40, and the second slot is used to insert a second eMMC 50.

[0062] Optionally, the slot supports eMMC sizes including 169-FBGA or 153-FBGA.

[0063] Optionally, the slots correspond to the limiting frames, with the first slot corresponding to the first limiting frame and the second slot corresponding to the second limiting frame. The first limiting frame has a clearance fit with the first eMMC, and the second limiting frame has a clearance fit with the second eMMC. By changing the size of the first limiting frame, first eMMCs of different sizes can be inserted into the first limiting frame. For example, if the size of the first limiting frame is 16*16, the insertable first eMMC 40 should also be 16*16. If the size of the first limiting frame is changed to 20*20, the insertable first eMMC 40 should also be 16*16.

[0064] In one possible implementation, the eMMC storage device further includes M flip structures, wherein when any flip structure is in the flipped state, the eMMC can be inserted into a slot covered by that flip structure. For example, the eMMC storage device includes a first flip structure and a second flip structure, the first flip structure covering a first slot and the second flip structure covering a second slot. When the first flip structure is in the flipped state, a first eMMC 40 can be inserted into the first slot. When the second flip structure is in the flipped state, a second eMMC 50 can be inserted into the second slot. As another example, the eMMC storage device includes a third flip structure, the third flip structure covering both the first and second slots. When the third flip structure is in the flipped state, either the first eMMC 40 or the second eMMC 50 can be inserted into the first slot.

[0065] In another possible implementation, the eMMC storage device further includes N ejector structures. When any ejector structure is in the ejected state, the eMMC can be inserted into a slot located within that ejector structure. For example, the eMMC storage device includes a first ejector structure and a second ejector structure, with a first slot located in the first ejector structure and a second slot located in the second ejector structure. When the first ejector structure is in the ejected state, a first eMMC 40 can be inserted into the first slot. When the second ejector structure is in the ejected state, a second eMMC 50 can be inserted into the second slot.

[0066] In one possible embodiment, when the processing unit 10 is connected to any eMMC, the upgrade testing device can be used to upgrade the driver or perform read / write speed tests on the eMMC. (See [link to relevant documentation]). Figure 4 , Figure 4 This is a schematic diagram illustrating the use of an upgrade testing device to upgrade a driver or perform a read / write speed test, as provided in an embodiment of this application. Specifically, the driver can be upgraded by clicking "Driver Upgrade," or a read / write speed test can be performed by clicking "Speed ​​Test," or the driver upgrade or read / write speed test can be exited by clicking "Exit."

[0067] If you click "Driver Update" to update the driver, please refer to... Figure 5 , Figure 5This illustration shows a driver upgrade using an upgrade testing device, as provided in this application embodiment. The upgrade testing device allows selection of multiple driver file versions; any version can be selected to begin the upgrade. Specifically, driver file 1 with version number 03 is selected for the upgrade; this driver file is 512KB in size. After selecting the driver file for upgrade, users can click "Start Upgrade" to begin the upgrade, click "Cancel Upgrade" to reselect the driver file, or click "Back" to return to the previous screen. Figure 5 The interface described above.

[0068] If you click "Start Upgrade" to upgrade the driver, please refer to... Figure 6 , Figure 6 This is a schematic diagram illustrating another method of upgrading a driver using an upgrade testing device, as provided in an embodiment of this application. Specifically, during the driver upgrade process, the status information can be used to determine whether the driver upgrade is complete. If the status information is "Upgrading," it indicates that the driver is being upgraded for the eMMC. The progress of the driver upgrade can be monitored using a progress bar, and the driver upgrade can be forcibly terminated by clicking "Force Exit."

[0069] If you click "Start Upgrade" to upgrade the driver, please refer to... Figure 7 , Figure 7 This illustration shows a driver upgrade failure using an upgrade testing device, as provided in an embodiment of this application. Specifically, in the event of a driver upgrade failure, the failure can be confirmed by the upgrade failure status information, and the stage of the upgrade failure can be determined by the progress bar in the upgrade progress. Optionally, the reason for the driver upgrade failure is that the driver is invalid. The driver upgrade can be forcibly terminated by clicking "Force Exit".

[0070] In the case of clicking speed test to perform read / write speed test, please refer to Figure 8 , Figure 8 This diagram illustrates a read / write speed test using an upgraded testing device, as provided in an embodiment of this application. Specifically, the read / write speed test includes sequential read testing, sequential write testing, random read testing, and random write testing. Clicking "Sequential Read" performs a sequential read test on the eMMC, clicking "Sequential Write" performs a sequential write test on the eMMC, clicking "Random Read" performs a random read test on the eMMC, clicking "Random Write" performs a random write test on the eMMC, or clicking "Back" returns to the previous state. Figure 5 The interface described above.

[0071] If you click Sequential Read to perform a sequential read test on the eMMC, please refer to [link / reference]. Figure 9 , Figure 9 This diagram illustrates a sequential read test using an upgrade testing device, as provided in an embodiment of this application. Specifically, a sequential read test is performed on the eMMC to determine its sequential read rate. Optionally, the eMMC sequential read rate is 210.32 MB / s. During the sequential read test of the eMMC, the user can click "back" to return to the previous screen. Figure 8 The interface allows users to select specific read / write speed tests.

[0072] In one possible design, the electronic device can correspond to, for example... Figure 2 or Figure 3 The eMMC storage device shown can be either an eMMC storage device or a chip within an eMMC storage device. This electronic device may include components for performing the operations performed by the eMMC storage device in the above embodiments, and each component in the electronic device respectively implements the operations performed by the eMMC storage device in the above method embodiments.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. Parts not described in detail in a particular embodiment can be found in the relevant descriptions of other embodiments. It should be understood that the disclosed apparatus can be implemented in other ways based on the embodiments provided in this application. For example, the apparatus embodiments described above are merely illustrative.

[0074] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An eMMC storage device, characterized in that, The eMMC storage device includes: The system includes a processing unit, a conversion circuit, a switching unit, and N eMMCs, wherein the N eMMCs include a first eMMC and a second eMMC, and N is an integer greater than or equal to 2. The first output terminal of the processing unit is connected to the first terminal of the conversion circuit, the second terminal of the conversion circuit is connected to the first terminal of the switching unit, the second terminal of the switching unit is connected to the first terminal of the first eMMC, and the third terminal of the switching unit is connected to the first terminal of the second eMMC; the switching unit is used to enable the processing unit to connect to one of the N eMMCs.

2. The eMMC storage device according to claim 1, characterized in that, The eMMC storage device further includes: a switch control unit; The second output terminal of the processing unit is connected to the first terminal of the switch control unit, and the second terminal of the switch control unit is connected to the control terminal of the switch unit. The switch control unit is used to convert the control command output by the processing unit into a switching command. The switching command is used to control the state of the switch unit so that the processing unit can be connected to one of the N eMMCs.

3. The eMMC storage device according to claim 1, characterized in that, The eMMC storage device further includes N slots, each corresponding to one of the N eMMCs.

4. The eMMC storage device according to claim 3, characterized in that, The N slots include a first slot and a second slot. The first slot is provided with a first limiting frame, and the second slot is provided with a second limiting frame. The first limiting frame is used to fix the first eMMC, and the second limiting frame is used to fix the second eMMC.

5. The eMMC storage device according to claim 4, characterized in that, The size of the first limiting frame is adapted to the size of the first eMMC, and the size of the second limiting frame is adapted to the size of the second eMMC.

6. The eMMC storage device according to claim 4, characterized in that, The first limiting frame and the second limiting frame may have different or the same dimensions.

7. The eMMC storage device according to claim 4, characterized in that, The eMMC storage device also includes M flip structures, wherein when the flip structures are in the flip state, the slots can be used to insert eMMC; M is an integer less than or equal to N.

8. The eMMC storage device according to claim 4, characterized in that, The eMMC storage device further includes N ejector structures, including a first ejector structure and a second ejector structure; the first slot is disposed within the first ejector structure, and the second slot is disposed within the second ejector structure; When the first pop-up structure is in the pop-up state, the first eMMC can be inserted into the first slot; When the second pop-up structure is in the pop-up state, the second eMMC can be inserted into the second slot.

9. The eMMC storage device according to claim 2, characterized in that, The switching instructions include binary instructions.

10. An electronic device, characterized in that, Includes the eMMC storage device as described in any one of claims 1 to 9.

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