Power supply control chip with variable sampling blanking time

Abstract

The utility model relates to the technical field of power electronics, and discloses a power supply control chip with variable sampling blanking time, which comprises a high-voltage power supply unit, a reference unit, comparators CMP1 to CMP4, switches SW1 to SW6, a controlled current source G1, a controlled current source G2, capacitors C1 to C4, a pulse generation unit, a rising edge delay unit, a D trigger DFF1, an SR latch SR1, a buffer BUFFER and an AND gate AND1. When the circuit is used, the longer the conduction time of the external MOS tube is, the higher the voltage of the capacitor C1 is, and the smaller the output current of the controlled current source G2 is when the external MOS tube is turned off, so that the longer the charging time of the capacitor C2 is, and the output overturning time of the comparator CMP2 is prolonged. The finally generated effect is that the higher the primary side current of the transformer is, the longer the blanking time of voltage VAUX sampling is, the variable sampling blanking time is achieved, it can be guaranteed that the sampling voltage input to the switch SW3 can truly reflect the output voltage, and errors of system output are avoided.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically to a power control chip with variable sampling blanking time. Background Technology

[0002] Traditional AC-DC power conversion circuits in isolated solutions require isolation optocouplers and operational amplifiers such as the 431 to provide secondary voltage feedback to the primary control circuit. This poses a significant challenge for cost- or size-sensitive applications. Therefore, power conversion circuits based on primary-side feedback have emerged. Commonly used circuits include... Figure 1 As shown, Figure 1 The working and detection principles of the circuit shown are as follows:

[0003] The input voltage VIN is shaped by the rectifier bridge and filtered by the output capacitor of the rectifier bridge to become a slightly rippled DC voltage VBUS. When the MOSFET Q1 is turned on, the DC voltage VBUS charges the primary winding of the transformer. At this time, the transformer can be equivalent to an inductor. According to the charging current law of an inductor, we can obtain:

[0004] VBUS - VCS = L * (diL / dt), where VCS is the voltage across the resistor RCS, iL is the primary inductance current of the transformer, and diL / dt is the rate of change of this current. Since the resistor RCS is a small resistance, by reasonably designing the resistance range of the resistor RCS, VCS will not exceed 1V, while VBUS is 130-390 times VCS. Therefore, the engineering calculation can be simplified to VBUS = L * (diL / dt).

[0005] When MOSFET Q1 is turned off, the primary inductance of the transformer discharges to the secondary winding through a turns-ratio equivalent, with a discharge voltage of VOUT*NPS, where VOUT is the output voltage and NPS is the ratio of the number of turns on the primary winding to the number of turns on the secondary winding. Clearly, based on the principle of transformer turns ratio, the voltage of the auxiliary winding is denoted as VAUX, and its amplitude in the horizontal state during the turn-off time is... Where VAUX_H is the voltage during the discharge of the auxiliary winding inductor, and VOUT and VD are the output voltage and diode forward voltage drop, respectively. N is the number of turns in the auxiliary winding. S This represents the number of turns in the secondary winding.

[0006] When the inductor discharges, the auxiliary winding is in a horizontal state. After the inductor has finished discharging, the capacitance between the inductor and the drain-sink of the MOSFET Q1 will resonate, causing VDRAIN to decrease until it reaches VBUS, at which point the voltage of the auxiliary winding is 0. Additionally, the chip detects VAUX_H (the voltage at the chip's sampling pin) through voltage divider resistors RU and RD. Obviously N SIf VD, RD, and RU are constants for a given system, then VAUX_H can directly reflect the size of VOUT.

[0007] In practical applications, since no transformer is perfectly coupled and there is leakage inductance between the coils, when MOSFET Q1 is turned off, VDRAIN will oscillate due to the leakage inductance and the leakage inductance absorption capacitor. Similarly, the waveform of VAUX will also experience a small oscillation. The duration and amplitude of the oscillation are proportional to the energy stored in the primary inductor of the transformer. Obviously, the chip must avoid this oscillation during sampling. The current traditional approach is that after the chip sends the signal to turn off MOSFET Q1, it will delay for a period of time before sampling the output. This period is called the sampling blanking time, denoted as TSAMPLE_LEB, and is generally set at around 2.5us-3us. The chip can only sample the VAUX_H voltage divider after the blanking time has elapsed, and sampling also requires a period of time, denoted as TSAMPLE, which is generally around 1us.

[0008] The above process has two problems, as follows:

[0009] 1. When the system is under heavy load, due to the longer conduction time of MOSFET Q1 and the greater energy stored in the transformer, the oscillation time and horizontal state time of VDRAIN and VAUX are both longer after MOSFET Q1 is turned off. That is, the state of VAUX_H is maintained for a longer period (the specific time depends on the system load). After the blanking time, it can still maintain a hold time for chip sampling. The relevant signal waveforms are as follows: Figure 2 As shown. However, under light load conditions, the MOSFET Q1 has a short turn-on time and the energy stored in the transformer is low. After the chip turns off MOSFET Q1, VAUX cannot maintain a horizontal position within the time interval TSAMPLE_LEB+TSAMPLE, and is in the resonant region at the end of the blanking and hold period. At this time, the chip's sampling cannot reflect the true output voltage; the relevant waveform is shown below. Figure 3 As shown, the measured voltage is lower than the horizontal range, so the chip mistakenly thinks the output voltage is low and raises it. Therefore, the output voltage under light load will be higher than the set output voltage.

[0010] Second: Under heavy load, when the transformer discharges past TSAMPLE_LEB, the inductor current is still relatively high, and the diode voltage drop required for the inductor to discharge to the output is large. Under light load, however, the inductor current is smaller after TSAMPLE_LEB, and the diode voltage drop required for the inductor to discharge to the output is smaller. The voltage drop (VD) of a diode cannot be considered constant under different load conditions and will fluctuate slightly. When the output voltage (VOUT) and VD are close in magnitude, this fluctuation will cause a large error. Generally, the voltage drop of a diode is about 0.8V-1V under heavy load, averaging 0.9V, while it is about 0.5V under light load, a difference of 0.4V. For a 24V output voltage system, this error is 0.4 / 24 = 3.33%, and for a 5V output voltage system, the error is approximately 0.4 / 5 = 8%. Utility Model Content

[0011] In view of the shortcomings of the prior art, the present invention provides a power control chip with variable sampling blanking time. The technical problem to be solved is that the sampling blanking time of the existing power control chip is not variable when in use, which makes it impossible to collect the actual output voltage and increases the system output error.

[0012] To solve the above technical problems, this utility model provides the following technical solution: a power control chip with variable sampling blanking time, including a comparator CMP1, a D flip-flop DFF1, an SR latch SR1 and a buffer BUFFER;

[0013] The positive input terminal of comparator CMP1 is used to input the reference voltage VZCD. The negative input terminal of comparator CMP1 is electrically connected to the output terminal of switch SW3 and the input terminal of switch SW4 respectively. The input terminal of switch SW3 is used to connect the output feedback voltage. The control terminal of switch SW3 is electrically connected to the output terminal of comparator CMP2 and the input terminal of the pulse generation unit respectively. The output terminal of the pulse generation unit is electrically connected to the control terminal of switch SW4. The positive input terminal of comparator CMP2 is electrically connected to one end of capacitor C2, the input terminal of switch SW5 and the output terminal of controlled current source G2 respectively. The negative input terminal of comparator CMP2 is used to input the reference voltage VDELAY. The output terminal of switch SW5 and the other end of capacitor C2 are both grounded. The input terminal of controlled current source G2 is used to connect the reference voltage V5V. The positive connection terminal of controlled current source G2 is used to connect the reference voltage VREF2.

[0014] The output terminal of switch SW4 is electrically connected to the negative terminal of controlled current source G1 and grounded through capacitor C3. The positive terminal of controlled current source G1 is used to input the reference voltage VREF. The input terminal of controlled current source G1 is used to connect the reference voltage V5V. The output terminal of controlled current source G1 is electrically connected to the negative input terminal of comparator CMP4 and is used to input current IS1. The positive input terminal of comparator CMP4 is electrically connected to one end of capacitor C4 and the input terminal of switch SW6. The other end of capacitor C4 and the output terminal of switch SW6 are both grounded. The output terminal of comparator CMP4 is electrically connected to one input terminal of AND gate AND1. The output terminal of AND gate AND1 is connected to SR latch S. The R input terminal of R1 is electrically connected, and the other input terminal of AND gate AND1 is electrically connected to the input terminal of comparator CMP3. The negative input terminal of comparator CMP3 is used to input the reference voltage VCS_MIN. The positive input terminal of comparator CMP3 is electrically connected to the output terminals of switch SW2 and switch SW1 respectively. The input terminal of switch SW2 is grounded through capacitor C1 and electrically connected to the negative connection terminal of controlled current source G2. The control terminals of switch SW1 and switch SW2 are electrically connected to the output terminal of rising edge delay unit respectively. The input terminal of rising edge delay unit is electrically connected to the QP output terminal of SR latch SR1. The input terminal of switch SW1 is used to input the primary side feedback voltage.

[0015] The output of comparator CMP1 is electrically connected to the clock input of D flip-flop DFF1. The Q output of D flip-flop DFF1 is electrically connected to the S input of SR latch SR1. The QP output of SR latch SR1 is electrically connected to the input of buffer BUFFER, the reset terminal of D flip-flop DFF1, and the control terminal of switch SW5. The QN output of SR latch SR1 is electrically connected to the control terminal of switch SW6.

[0016] In one embodiment, the present invention further includes a high-voltage power supply unit and a reference unit. The high-voltage power supply unit generates a VCC voltage based on an external input voltage, and the reference unit generates reference voltages V5V, VZCD, VREF, VREF2, VCS_MIN, and VDELAY based on the VCC voltage.

[0017] In one embodiment, the present invention further includes a chip body 100, wherein the high-voltage power supply unit, reference unit, comparators CMP1 to CMP4, switches SW1 to SW6, controlled current source G1, controlled current source G2, capacitors C1 to C4, pulse generation unit, rising edge delay unit, D flip-flop DFF1, SR latch SR1, buffer BUFFER and AND gate AND1 are all disposed on the chip body.

[0018] In one embodiment, the chip body is further provided with HV pin, VCC pin, FB pin, COMP pin, GND pin, GATE pin and CS pin;

[0019] The HV pin is electrically connected to the input terminal of the high-voltage power supply unit, and the VCC pin is electrically connected to the output terminal of the high-voltage power supply unit; the FB pin is electrically connected to the input terminal of switch SW3, the COMP pin is electrically connected to the output terminal of the controlled current source G1, the GND pin is the ground terminal of the chip, the CS pin is electrically connected to the input terminal of switch SW1, and the GATE pin is electrically connected to the output terminal of the buffer BUFFER.

[0020] In one embodiment, the pulse generation unit outputs a pulse signal after receiving a signal from a low level to a high level.

[0021] In one implementation, the high-level duration of the pulse signal is 1µs.

[0022] In one implementation, after receiving a low-level to high-level signal, the input of the rising edge delay unit drives switches SW1 and SW2 to turn on after a delay of x.

[0023] In one embodiment, the control terminals of switches SW1 and SW2 are turned on when a high-level signal is input and turned off when a low-level signal is input.

[0024] In one embodiment, the control terminals of switches SW3 and SW4 are turned on when a high-level signal is input and turned off when a low-level signal is input.

[0025] In one embodiment, the control terminals of switches SW5 and SW6 are turned on when a high-level signal is input and turned off when a low-level signal is input.

[0026] The beneficial effects of this invention compared to the prior art are as follows: In actual use, the longer the external MOSFET is on, the higher the voltage on capacitor C1. Then, when the external MOSFET is off, the output current of the controlled current source G2 is smaller, resulting in a longer charging time for capacitor C2. This, in turn, lengthens the switching time of the comparator CMP2. The final effect is that the higher the primary current of the transformer, the longer the blanking time of the voltage VAUX sampling, thus achieving a variable sampling blanking time. In addition, because the sampling blanking time is variable, it can be ensured that the sampling voltage input to switch SW3 can truly reflect the output voltage, thus avoiding errors in the system output. Attached Figure Description

[0027] Figure 1This is a circuit diagram of an existing power conversion circuit based on primary-side feedback;

[0028] Figure 2 for Figure 1 Waveforms of relevant signals when the circuit is under heavy load;

[0029] Figure 3 for Figure 1 Waveforms of relevant signals in the circuit under light load;

[0030] Figure 4 This is a schematic diagram of the structure of the present invention in the embodiment;

[0031] Figure 5 for Figure 4 Waveforms of relevant signals in the circuit under heavy load;

[0032] Figure 6 for Figure 4 Waveforms of relevant signals in the circuit under light load. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0034] like Figure 4 As shown, this embodiment provides a power control chip with variable sampling blanking time, including a comparator CMP1, a D flip-flop DFF1, an SR latch SR1, and a buffer BUFFER.

[0035] The positive input terminal of comparator CMP1 is used to input the reference voltage VZCD. The negative input terminal of comparator CMP1 is electrically connected to the output terminal of switch SW3 and the input terminal of switch SW4 respectively. The input terminal of switch SW3 is used to connect the output feedback voltage. The control terminal of switch SW3 is electrically connected to the output terminal of comparator CMP2 and the input terminal of pulse generation unit 1 respectively. The output terminal of pulse generation unit 1 is electrically connected to the control terminal of switch SW4. The positive input terminal of comparator CMP2 is electrically connected to one end of capacitor C2, the input terminal of switch SW5 and the output terminal of controlled current source G2 respectively. The negative input terminal of comparator CMP2 is used to input the reference voltage VDELAY. The output terminal of switch SW5 and the other end of capacitor C2 are both grounded. The input terminal of controlled current source G2 is used to connect the reference voltage V5V. The positive connection terminal of controlled current source G2 is used to connect the reference voltage VREF2.

[0036] The output of switch SW4 is electrically connected to the negative terminal of controlled current source G1 and grounded through capacitor C3. The positive terminal of controlled current source G1 is used to input the reference voltage VREF. The input terminal of controlled current source G1 is used to connect the reference voltage V5V. The output of controlled current source G1 is electrically connected to the negative input terminal of comparator CMP4 and is used to input current IS1. The positive input terminal of comparator CMP4 is electrically connected to one end of capacitor C4 and the input terminal of switch SW6. The other end of capacitor C4 and the output terminal of switch SW6 are both grounded. The output terminal of comparator CMP4 is electrically connected to one input terminal of AND gate AND1. The output terminal of AND gate AND1 is connected to the SR latch SR1. The R input terminal is electrically connected, and the other input terminal of AND gate AND1 is electrically connected to the input terminal of comparator CMP3. The negative input terminal of comparator CMP3 is used to input the reference voltage VCS_MIN. The positive input terminal of comparator CMP3 is electrically connected to the output terminals of switch SW2 and switch SW1 respectively. The input terminal of switch SW2 is grounded through capacitor C1 and electrically connected to the negative connection terminal of controlled current source G2. The control terminals of switch SW1 and switch SW2 are electrically connected to the output terminal of rising edge delay unit 2 respectively. The input terminal of rising edge delay unit 2 is electrically connected to the QP output terminal of SR latch SR1. The input terminal of switch SW1 is used to input the primary side feedback voltage.

[0037] The output of comparator CMP1 is electrically connected to the clock input of D flip-flop DFF1. The Q output of D flip-flop DFF1 is electrically connected to the S input of SR latch SR1. The QP output of SR latch SR1 is electrically connected to the input of buffer BUFFER, the reset terminal of D flip-flop DFF1, and the control terminal of switch SW5. The QN output of SR latch SR1 is electrically connected to the control terminal of switch SW6.

[0038] In practical use, the longer the external MOSFET is on, the higher the voltage on capacitor C1. Then, when the external MOSFET is off, the output current of the controlled current source G2 is smaller, resulting in a longer charging time for capacitor C2. This, in turn, lengthens the switching time of the comparator CMP2. The final effect is that the higher the primary current of the transformer, the longer the blanking time of the voltage VAUX sampling, thus achieving a variable sampling blanking time. In addition, because the sampling blanking time is variable, it can be ensured that the sampling voltage input to switch SW3 can truly reflect the output voltage, avoiding errors in the system output.

[0039] In addition, in this embodiment, as Figure 4As shown, this utility model also includes a high-voltage power supply unit 3 and a reference unit 4. The high-voltage power supply unit 3 generates a VCC voltage based on an external input voltage, and the reference unit 4 generates reference voltages V5V, VZCD, VREF, VREF2, VCS_MIN, and VDELAY based on the VCC voltage. In this embodiment, the reference voltage V5V is 5V, the reference voltage VZCD can be 0.1V, the reference voltage VREF can be 2.5V, the reference voltage VREF2 can be 1.2V, the reference voltage VCS_MIN can be 0.24V, and the reference voltage VDELAY can be 1V.

[0040] In addition, in this embodiment, as Figure 4 As shown, this utility model also includes a chip body 100, a high-voltage power supply unit 3, a reference unit 4, comparators CMP1 to CMP4, switches SW1 to SW6, a controlled current source G1, a controlled current source G2, capacitors C1 to C4, a pulse generation unit 1, a rising edge delay unit 2, a D flip-flop DFF1, an SR latch SR1, a buffer BUFFER, and an AND gate AND1, all of which are disposed on the chip body 100.

[0041] exist Figure 4 In the chip body 100, there are also HV pin, VCC pin, FB pin, COMP pin, GND pin, GATE pin and CS pin;

[0042] The HV pin is electrically connected to the input terminal of high-voltage power supply unit 3, and the VCC pin is electrically connected to the output terminal of high-voltage power supply unit 3. In actual use, the VCC pin can be grounded through a capacitor. The FB pin is electrically connected to the input terminal of switch SW3, the COMP pin is electrically connected to the output terminal of controlled current source G1, the GND pin is the ground terminal of the chip, and the CS pin is electrically connected to the input terminal of switch SW1 for inputting the primary-side feedback voltage. For details, please refer to... Figure 1 The CS pin and GATE pin are electrically connected to the output of the buffer.

[0043] Specifically, in this embodiment, the pulse generation unit 1 outputs a pulse signal after receiving a signal that transitions from a low level to a high level; the high-level duration of the pulse signal is 1µs. In some embodiments, the high-level duration of the pulse signal can be set according to actual needs.

[0044] Specifically, in this embodiment, after receiving a low-level to high-level signal, the input terminal of the rising edge delay unit 2 delays for 300ns before driving switches SW1 and SW2 to turn on. Additionally, after receiving a low-level signal (i.e., after the signal output from the QP output terminal of the SR latch SR1 is low), the input terminal of the rising edge delay unit 2 immediately turns off switches SW1 and SW2.

[0045] In addition, in this embodiment, the control terminals of switches SW1 and SW2 are turned on when a high-level signal is input and turned off when a low-level signal is input; similarly, the control terminals of switches SW3 and SW4 are turned on when a high-level signal is input and turned off when a low-level signal is input; similarly, the control terminals of switches SW5 and SW6 are turned on when a high-level signal is input and turned off when a low-level signal is input.

[0046] The waveforms of relevant signals under heavy or light load conditions in actual use of this utility model are as follows: Figure 5 and Figure 6 As shown, from Figure 5 and Figure 6 It can be seen that under heavy load (i.e., when the IMOS voltage is high), the TSAMPLE_LEB of the FB voltage is long to avoid VAUX voltage oscillations and to sample as low as possible when the VD voltage is low. Conversely, under light load (i.e., when the IMOS peak voltage is low), the TSAMPLE_LEB of the FB voltage is short. The shortened TSAMPLE_LEB+TSAMPLE time avoids sampling at the VAUX resonance curve, ensuring that the FB voltage sampling truly reflects the output voltage. Furthermore, the rectifier diode voltage drop tends to be consistent when sampling the output under heavy and light load conditions, reducing detection errors caused by diode voltage drops.

[0047] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A power control chip with variable sampling blanking time, characterized in that, This includes comparator CMP1, D flip-flop DFF1, SR latch SR1, and buffer BUFFER; The positive input terminal of comparator CMP1 is used to input the reference voltage VZCD. The negative input terminal of comparator CMP1 is electrically connected to the output terminal of switch SW3 and the input terminal of switch SW4 respectively. The input terminal of switch SW3 is used to connect the output feedback voltage. The control terminal of switch SW3 is electrically connected to the output terminal of comparator CMP2 and the input terminal of the pulse generation unit respectively. The output terminal of the pulse generation unit is electrically connected to the control terminal of switch SW4. The positive input terminal of comparator CMP2 is electrically connected to one end of capacitor C2, the input terminal of switch SW5 and the output terminal of controlled current source G2 respectively. The negative input terminal of comparator CMP2 is used to input the reference voltage VDELAY. The output terminal of switch SW5 and the other end of capacitor C2 are both grounded. The input terminal of controlled current source G2 is used to connect the reference voltage V5V. The positive connection terminal of controlled current source G2 is used to connect the reference voltage VREF2. The output terminal of switch SW4 is electrically connected to the negative terminal of controlled current source G1 and grounded through capacitor C3. The positive terminal of controlled current source G1 is used to input the reference voltage VREF. The input terminal of controlled current source G1 is used to connect the reference voltage V5V. The output terminal of controlled current source G1 is electrically connected to the negative input terminal of comparator CMP4 and is used to input current IS1. The positive input terminal of comparator CMP4 is electrically connected to one end of capacitor C4 and the input terminal of switch SW6. The other end of capacitor C4 and the output terminal of switch SW6 are both grounded. The output terminal of comparator CMP4 is electrically connected to one input terminal of AND gate AND1. The output terminal of AND gate AND1 is connected to SR latch S. The R input terminal of R1 is electrically connected, and the other input terminal of AND gate AND1 is electrically connected to the input terminal of comparator CMP3. The negative input terminal of comparator CMP3 is used to input the reference voltage VCS_MIN. The positive input terminal of comparator CMP3 is electrically connected to the output terminals of switch SW2 and switch SW1 respectively. The input terminal of switch SW2 is grounded through capacitor C1 and electrically connected to the negative connection terminal of controlled current source G2. The control terminals of switch SW1 and switch SW2 are electrically connected to the output terminal of rising edge delay unit respectively. The input terminal of rising edge delay unit is electrically connected to the QP output terminal of SR latch SR1. The input terminal of switch SW1 is used to input the primary side feedback voltage. The output of comparator CMP1 is electrically connected to the clock input of D flip-flop DFF1. The Q output of D flip-flop DFF1 is electrically connected to the S input of SR latch SR1. The QP output of SR latch SR1 is electrically connected to the input of buffer BUFFER, the reset terminal of D flip-flop DFF1, and the control terminal of switch SW5. The QN output of SR latch SR1 is electrically connected to the control terminal of switch SW6.

2. The power control chip with variable sampling blanking time according to claim 1, characterized in that, It also includes a high-voltage power supply unit and a reference unit. The high-voltage power supply unit generates a VCC voltage based on an external input voltage. The reference unit generates reference voltages V5V, VZCD, VREF, VREF2, VCS_MIN, and VDELAY based on the VCC voltage.

3. A power control chip with variable sampling blanking time according to claim 2, characterized in that, It also includes a chip body 100, wherein the high voltage power supply unit, reference unit, comparators CMP1 to CMP4, switches SW1 to SW6, controlled current source G1, controlled current source G2, capacitors C1 to C4, pulse generation unit, rising edge delay unit, D flip-flop DFF1, SR latch SR1, buffer BUFFER and AND gate AND1 are all disposed on the chip body.

4. A power control chip with variable sampling blanking time according to claim 3, characterized in that, The chip body is also provided with HV pin, VCC pin, FB pin, COMP pin, GND pin, GATE pin and CS pin; The HV pin is electrically connected to the input terminal of the high-voltage power supply unit, and the VCC pin is electrically connected to the output terminal of the high-voltage power supply unit; the FB pin is electrically connected to the input terminal of switch SW3, the COMP pin is electrically connected to the output terminal of the controlled current source G1, the GND pin is the ground terminal of the chip, the CS pin is electrically connected to the input terminal of switch SW1, and the GATE pin is electrically connected to the output terminal of the buffer BUFFER.

5. A power control chip with variable sampling blanking time according to claim 1, characterized in that, The pulse generation unit outputs a pulse signal after receiving a signal ranging from a low level to a high level.

6. A power control chip with variable sampling blanking time according to claim 5, characterized in that, The high-level duration of the pulse signal is 1µs.

7. A power control chip with variable sampling blanking time according to claim 1, characterized in that, After receiving a low-level to high-level signal, the input terminal of the rising edge delay unit drives switches SW1 and SW2 to turn on after a delay of x.

8. A power control chip with variable sampling blanking time according to claim 1, characterized in that, The control terminals of switches SW1 and SW2 are turned on when a high-level signal is input and turned off when a low-level signal is input.

9. A power control chip with variable sampling blanking time according to claim 1, characterized in that, The control terminals of switches SW3 and SW4 are turned on when a high-level signal is input and turned off when a low-level signal is input.

10. A power control chip with variable sampling blanking time according to claim 1, characterized in that, The control terminals of switches SW5 and SW6 are turned on when a high-level signal is input and turned off when a low-level signal is input.

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