Maximum pulse width limiting circuit based on DQ trigger and logic gate

Abstract

The utility model relates to the technical field of energy storage, in particular to a maximum pulse width limiting circuit based on a DQ trigger and a logic gate, which comprises the DQ trigger, a logic AND gate circuit and an RC circuit, the clock end of the DQ trigger is connected with the PWM generator, and the data end D and the setting end Sn of the DQ trigger are connected with a fixed high level; and a negative output pin Qn and a reset pin Rn of the DQ trigger are connected to the RC circuit. The maximum pulse width limitation is directly realized through hardware logic, and the problems of high response delay and dependence on software reliability in the prior art are solved by utilizing the rising edge detection characteristic of the DQ trigger, the charging and discharging characteristic of the RC network and the real-time comparison function of the logic gate without software intervention.

Description

Technical Field

[0001] This application belongs to the field of energy storage technology, and in particular relates to a maximum pulse width limiting circuit based on DQ flip-flops and logic gates. Background Technology

[0002] In switching power supply topologies, such as Boost, Buck, and Flyback circuits, limiting the maximum duty cycle is one of the key factors ensuring the safe and stable operation of the circuit. Duty cycle refers to the ratio of the on-time of the switching transistor to the entire circuit cycle, directly affecting the power conversion efficiency and circuit stability. If the duty cycle exceeds the design threshold, it may lead to a series of adverse consequences, including overvoltage and overheating of power devices, saturation of magnetic components, and ultimately, damage.

[0003] Currently, many switching power supply systems employ software algorithms and processor-based control methods to adjust and limit the maximum duty cycle. These systems typically rely on multiple steps, including signal sampling, algorithm calculation, and instruction execution, to dynamically adjust the duty cycle to adapt to load changes. However, this approach has certain drawbacks. When the load changes rapidly, the system needs to undergo multiple processes such as signal sampling, calculation, and instruction execution, resulting in high response delays. This delay may cause the duty cycle to exceed the design threshold within a short period, leading to unsafe operating conditions.

[0004] Furthermore, software-based control methods also present challenges in program development and maintenance. If the software algorithm is flawed or the digital chip malfunctions, the duty cycle limiting function may fail, compromising the circuit's safe operation. In such cases, the circuit may face serious problems such as overvoltage and overheating, and could even damage power devices.

[0005] Therefore, existing technologies face the challenge of quickly and accurately controlling the maximum duty cycle under dynamic load changes to ensure the stability and safety of switching power supply systems. To this end, a more efficient, reliable, and low-latency duty cycle control method is urgently needed to avoid the shortcomings of existing software control schemes. Utility Model Content

[0006] This application proposes a maximum pulse width limiting circuit based on DQ flip-flops and logic gates. The maximum pulse width limiting is directly implemented through hardware logic. It utilizes the rising edge detection characteristics of DQ flip-flops, the charging and discharging characteristics of RC networks, and the real-time comparison function of logic gates, without the need for software intervention, thus solving the problems of high response delay and reliance on software reliability in the prior art.

[0007] Specifically, the maximum pulse width limiting circuit based on DQ flip-flops and logic gates described in this application includes: a DQ flip-flop, an AND gate circuit, and an RC circuit.

[0008] The main functions of each module are as follows:

[0009] DQ flip-flop: detects the rising edge of the input PWM signal and generates a status signal.

[0010] AND gate: Compares the input PWM signal with the reference maximum pulse width signal (PWM MAX), and outputs the adjusted PWM signal.

[0011] RC network: In conjunction with the reset pin Rn of the DQ flip-flop, it generates the reference maximum pulse width signal.

[0012] Preferably, the clock terminal of the DQ flip-flop is connected to a PWM generator.

[0013] Preferably, the data terminal D and the set terminal Sn of the DQ flip-flop are connected to a fixed high level to ensure that the flip-flop is triggered only on the rising edge of the clock.

[0014] Preferably, the negative output pin Qn and the reset pin Rn of the DQ flip-flop are connected to an RC circuit.

[0015] Preferably, the output port Q of the DQ flip-flop is connected to an AND gate circuit, and the other end of the AND gate circuit is connected to a PWM generator.

[0016] Preferably, the negative output pin Qn of the DQ flip-flop is connected to the resistor R1 of the RC circuit.

[0017] Preferably, the reset pin Rn of the DQ flip-flop is connected to the capacitor C1 of the RC circuit;

[0018] Furthermore, the reset pin Rn is also connected to the other end of the resistor R1.

[0019] Preferably, when the DQ flip-flop receives the input PWM signal and rises to the trigger value, the data terminal D, the set terminal Sn, and the output port Q output a high level, and the negative output pin Qn outputs a low level. The low level of the negative output pin Qn causes the RC circuit to start discharging the capacitor C1.

[0020] Preferably, the discharge time of capacitor C1 is the maximum pulse width time, which can be set by adjusting the resistance value of R1 and the capacitance value of C1.

[0021] Preferably, the discharge time of capacitor C1 is the maximum pulse width time, which can be set by adjusting the resistance value of R1 and the capacitance value of C1.

[0022] Preferably, the AND gate circuit compares the input PWM signal with the reference maximum pulse width signal and outputs a adjusted PWM signal. This application uses an AND gate to implement pulse width comparison and limiting, avoiding delay and reliability issues in digital systems and improving anti-interference capabilities. Specifically:

[0023] When the PWM_IN pulse width of the input PWM signal is less than or equal to the PWM_MAX pulse width of the reference maximum pulse width signal, the output signal of the logic AND gate is the input PWM signal.

[0024] When the PWM_IN pulse width of the input PWM signal is greater than the PWM_MAX pulse width of the reference maximum pulse width signal, the AND gate circuit forces a low level output in the part exceeding the threshold, limiting the pulse width to the reference maximum pulse width signal.

[0025] Compared with the prior art, this application has the following beneficial effects:

[0026] This application consists of hardware circuits (flip-flops, logic gates, and RC networks). Signal processing relies entirely on physical logic and analog circuit characteristics, requiring no software intervention, thus avoiding firmware vulnerabilities and timing conflicts inherent in digital systems. For example, the truth table logic of the DQ flip-flop (when Sn=1 and D=1, the state flips only on the rising edge of the clock) ensures the stability of signal detection. The analog charging and discharging process of the RC network naturally filters high-frequency noise, reducing the risk of circuit damage due to software anomalies or chip failures.

[0027] Furthermore, this application only requires DQ flip-flops (such as general-purpose chips like the 74HC74, costing less than $1), logic AND gates (such as the 74HC08), and RC resistor-capacitor components (costing less than $0.1), with the total hardware cost being less than 1 / 5 of existing solutions. The circuit structure requires no programming; the maximum pulse width can be flexibly set by adjusting RC parameters (such as resistor and capacitor values), simplifying the debugging process to hardware parameter adjustment without requiring software code development.

[0028] Therefore, the maximum pulse width limiting circuit based on DQ flip-flops and logic gates described in this application significantly reduces system complexity and cost, making it particularly suitable for cost-sensitive consumer electronics and low-end power modules. It also shortens the development cycle and facilitates large-scale production and maintenance. Without replacing the core chip or modifying the software, it can operate stably within a frequency range of 50kHz to 5MHz and an input voltage range of 5V to 100V simply by adjusting the external resistors and capacitors, demonstrating significantly better compatibility than digital solutions. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the maximum pulse width limiting circuit based on DQ flip-flops and logic gates in this embodiment.

[0030] Figure 2 This is the waveform diagram of the maximum pulse width generation of PWM in this embodiment.

[0031] Figure 3 This is the waveform diagram of PWM_in being less than the maximum PWM_max in this embodiment.

[0032] Figure 4 This is the waveform diagram of PWM_in being greater than the maximum PWM_max in this embodiment. Detailed Implementation

[0033] The following description is intended to disclose this application so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0034] like Figure 1 As shown, this application proposes a maximum pulse width limiting circuit based on DQ flip-flops and logic gates. The circuit in this embodiment mainly consists of three parts: DQ flip-flops, logic AND gate circuits, and RC circuits.

[0035] Specifically, the DQ flip-flop is used to detect the rising edge of the input PWM signal and generate a status signal. The clock input of the DQ flip-flop is connected to the output of the PWM generator, and the data input D and the set input Sn are connected to a fixed high level to ensure that the flip-flop is triggered and the state toggles only on the rising edge of the clock.

[0036] The AND gate is used to compare the input PWM signal with the reference maximum pulse width signal (PWM_MAX). When the pulse width of the input PWM signal exceeds the maximum pulse width, the AND gate forces the input PWM signal to be trimmed, and outputs the trimmed PWM signal. Its input is connected to the PWM generator, and its output is connected to the output Q of the flip-flop.

[0037] The RC circuit mainly works with the reset pin Rn of the DQ flip-flop to generate the reference maximum pulse width signal. The resistor R1 and capacitor C1 of the RC circuit form a discharge network used to set the duration of the maximum pulse width.

[0038] To further clarify the connection methods of each module, the details are as follows:

[0039] The clock input of the DQ flip-flop is connected to a PWM generator.

[0040] In this embodiment, the data terminal D and the set terminal Sn of the DQ flip-flop are connected to a fixed high level to ensure that the flip-flop only triggers the state to flip on the rising edge of the clock, thus avoiding unnecessary interference.

[0041] The negative output pin Qn and reset pin Rn of the DQ flip-flop are connected to an RC circuit. Specifically, the negative output pin Qn of the DQ flip-flop is connected to resistor R1 of the RC circuit. The reset pin Rn of the DQ flip-flop is connected to capacitor C1 of the RC circuit, thereby achieving precise maximum pulse width control. For example, when the pulse width of the input PWM signal is greater than the set maximum pulse width, the AND gate circuit will force the output of the adjusted PWM signal to ensure the safety and stability of the circuit.

[0042] The output port Q of the DQ flip-flop is connected to a logic AND gate circuit, the other end of which is connected to a PWM generator. The reset pin Rn is also connected to the other end of resistor R1.

[0043] The maximum pulse width limiting circuit based on DQ flip-flops and logic gates described in this application, during application, when the rising edge of the input PWM signal arrives, the clock terminal of the DQ flip-flop receives the clock signal, the flip-flop's output terminal Q outputs a high level, and the negative output terminal Qn outputs a low level. At this time, the low-level signal at the negative output terminal Qn causes the RC circuit to start discharging capacitor C1, thereby generating the reference maximum pulse width signal.

[0044] In the RC circuit, the values ​​of resistor R1 and capacitor C1 determine the discharge time of capacitor C1, i.e., the maximum pulse width time. By adjusting the values ​​of R1 and C1, the maximum pulse width time can be flexibly set to ensure that the duty cycle does not exceed the set maximum pulse width.

[0045] An AND gate is used to compare the pulse width of the input PWM signal with the reference maximum pulse width signal. When the pulse width of the input PWM signal (PWM_IN) is less than or equal to the reference maximum pulse width signal (PWM_MAX), the AND gate directly outputs the input PWM signal. When the pulse width of the input PWM signal (PWM_IN) is greater than the reference maximum pulse width signal (PWM_MAX), the AND gate forces the excess portion of the PWM signal to a low level, thereby limiting the pulse width of the input PWM signal to not exceed the maximum pulse width. Through this method, this embodiment effectively limits the maximum pulse width in the switching power supply, avoiding problems such as overvoltage and overheating of power devices caused by excessively large pulse widths, thus improving the stability and safety of the circuit.

[0046] like Figure 2 As shown, when the rising edge of the input PWM signal triggers (point 1), the DQ flip-flop outputs a high level for Q and a low level for Qn because Sn=1 and D=1.

[0047] When Qn is low, the RC network starts discharging capacitor C1. When the voltage of C1 drops to the reset threshold (point 2), the level of Rn triggers the flip-flop to reset, Q becomes low, and Qn becomes high. The discharge time (point 1 to point 2) is the maximum pulse width time. The threshold can be set by adjusting the RC time constant (resistance value of R1, capacitance value of C1).

[0048] like Figure 3-4 As shown: PWM comparison and limitation; where, Figure 3 : PWM_in is less than the maximum PWM_ma; Figure 4: PWM_in is greater than the maximum PWM_max. The input PWM signal (PWM_IN) and the reference maximum pulse width signal (PWM_MAX) are input to the AND gate. When the PWM_IN pulse width is less than or equal to the PWM_MAX pulse width: the AND gate outputs the original PWM_IN signal ( Figure 3 When the PWM_IN pulse width > PWM_MAX pulse width: the AND gate forces a low output level for the portion exceeding the threshold, limiting the pulse width to PWM_MAX. Figure 4 ).

[0049] The maximum pulse width limiting circuit based on DQ flip-flops and logic gates provided in this application utilizes a hardware combination of DQ flip-flops and RC networks to generate a reference maximum pulse width signal in real time without software intervention. Pulse width comparison and limiting are achieved through logic AND gates, avoiding delay and reliability issues in digital systems, improving anti-interference capabilities, flexibly setting the pulse width threshold by adjusting the parameters of RC components, and reducing system cost and complexity by using general-purpose low-cost components.

[0050] The foregoing has shown and described the basic principles, main features, and advantages of this application. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from the spirit and scope thereof, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

[0051] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A maximum pulse width limiting circuit based on DQ flip-flops and logic gates, characterized in that, The circuit includes: a DQ flip-flop, an AND gate circuit, and an RC circuit; The clock terminal of the DQ flip-flop is connected to the PWM generator; The data terminal D and the set terminal Sn of the DQ flip-flop are connected to a fixed high level. The negative output pin Qn and reset pin Rn of the DQ flip-flop are connected to the RC circuit.

2. The maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 1, characterized in that, The output port Q of the DQ flip-flop is connected to an AND gate circuit, and the other end of the AND gate circuit is connected to a PWM generator.

3. The maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 2, characterized in that, The negative output pin Qn of the DQ flip-flop is connected to the resistor R1 of the RC circuit.

4. The maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 3, characterized in that, The reset pin Rn of the DQ flip-flop is connected to capacitor C1 in the RC circuit; The reset pin Rn is also connected to the other end of the resistor R1.

5. A maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to any one of claims 1-4, characterized in that, When the DQ flip-flop receives the input PWM signal and rises to the trigger value, the data terminal D, the set terminal Sn, and the output port Q output a high level, and the negative output pin Qn outputs a low level. The low level of the negative output pin Qn causes the RC circuit to start discharging the capacitor C1.

6. The maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 5, characterized in that, The discharge time of capacitor C1 is the maximum pulse width time, which can be set by adjusting the resistance value of R1 and the capacitance value of C1.

7. The maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 6, characterized in that, The logic AND gate circuit compares the input PWM signal with the reference maximum pulse width signal and outputs the adjusted PWM signal.

8. The maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 7, characterized in that, When the PWM_IN pulse width of the input PWM signal is less than or equal to the PWM_MAX pulse width of the reference maximum pulse width signal, the output signal of the logic AND gate is the input PWM signal.

9. A maximum pulse width limiting circuit based on DQ flip-flops and logic gates according to claim 7, characterized in that, When the PWM_IN pulse width of the input PWM signal is greater than the PWM_MAX pulse width of the reference maximum pulse width signal, the AND gate circuit forces a low level output in the part exceeding the threshold, limiting the pulse width to the reference maximum pulse width signal.

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