Schottky P-GaN gate structure
By employing a Schottky P-GaN gate structure in GaN-based power devices, combined with trapezoidal trenches, gradient-doped P-GaN layers, and a double-layer buffer layer, the electric field distribution and interface quality are optimized, solving the problems of low on-resistance, high breakdown voltage, and high-temperature stability under high voltage, high frequency, and high temperature applications, and significantly improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- QINGDAO JIAEN SEMICON
- Filing Date
- 2025-03-26
- Publication Date
- 2026-05-12
AI Technical Summary
Existing GaN-based power device gate structures cannot simultaneously meet the requirements of low on-resistance, high breakdown voltage, and high-temperature stability in high-voltage, high-frequency, and high-temperature applications. Existing composite gate structures have complex manufacturing processes and are difficult to control interface quality.
A Schottky P-GaN gate structure is adopted, including a substrate, a buffer layer, a trench gate structure, a Schottky metal layer, and a P-GaN layer. By combining the Schottky metal layer and the P-GaN layer in the trench structure to form a composite gate structure, a trapezoidal trench, a gradient-doped P-GaN layer, and a double buffer layer are designed to optimize the electric field distribution and interface quality.
It achieves a balance between low on-resistance and high breakdown voltage, improving the device's breakdown voltage by more than 30%, reducing on-resistance by more than 25%, reducing gate leakage current by an order of magnitude, significantly improving high-temperature stability, and extending the operating temperature range to over 200℃.
Smart Images
Figure CN224234069U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a Schottky P-GaN gate structure. Background Technology
[0002] With the rapid development of power electronics technology, GaN-based power devices have shown great potential in high-frequency, high-power, and high-temperature applications due to their excellent characteristics such as wide bandgap, high breakdown field strength, and high electron mobility. Currently, the gate structures of GaN-based power devices mainly include metal gates and P-GaN gates. Metal gates (such as Schottky gates) have low on-resistance and fast switching speeds, but suffer from problems such as large gate leakage current and poor high-temperature stability. P-GaN gates have high breakdown voltage and good high-temperature stability, but high on-resistance. To overcome the limitations of single-material gate structures, researchers have explored various composite gate structures, such as metal / insulator / semiconductor structures and field-plate-assisted gate structures. However, these structures are complex to manufacture, difficult to control interface quality, and have limited effectiveness in optimizing electric field distribution. Especially in high-voltage, high-frequency, and high-temperature applications, existing technologies struggle to simultaneously meet the requirements of low on-resistance, high breakdown voltage, and high-temperature stability, limiting the application range and performance improvement of GaN-based power devices. Utility Model Content
[0003] In view of this, the present invention provides a Schottky P-GaN gate structure that can solve the problem that existing composite gate structures cannot simultaneously meet the requirements of low on-resistance, high breakdown voltage and high temperature stability.
[0004] This utility model is implemented as follows:
[0005] This invention provides a Schottky P-GaN gate structure, comprising a substrate, a buffer layer, a trench gate structure, a Schottky metal layer, and a P-GaN layer; a buffer layer is sequentially disposed on the substrate; a trench gate structure is formed on the buffer layer; the trench gate structure includes multiple trenches arranged in parallel with each other; a Schottky metal layer and a P-GaN layer are sequentially disposed on the bottom and sidewalls of each trench; the Schottky metal layer is tightly attached to the bottom and sidewalls of the trench; the P-GaN layer fills the top of the Schottky metal layer, and the top of the P-GaN layer is flush with the top surface of the buffer layer; the thickness of the Schottky metal layer is greater at the bottom of the trench than at the sidewalls; the thickness of the P-GaN layer is greater in the central region of the trench than at the edge region; the distance between two adjacent trenches in the trench gate structure is 1.5 to 3 times the trench width.
[0006] The technical advantages of the Schottky P-GaN gate structure provided by this utility model are as follows: By combining the Schottky metal layer and the P-GaN layer in the trench structure to form a composite gate structure, the advantages of both the low on-resistance of the Schottky metal gate and the high breakdown voltage of the P-GaN gate are achieved. At the same time, the thickening design of the Schottky metal layer at the bottom of the trench enhances the gate's control over the channel region. The design of the P-GaN layer having a central thickness greater than the edge region optimizes the electric field distribution and suppresses the electric field concentration phenomenon at the gate edge. The distance design between adjacent trenches improves the current density and power density of the device.
[0007] Based on the above technical solution, the Schottky P-GaN gate structure of this utility model can be further improved as follows:
[0008] The trench has a trapezoidal cross-section structure, with the bottom width being smaller than the top width; the angle between the bottom of the trench and the sidewall is 120° to 160°; the depth of the trench is 0.5μm to 3μm; the top width of the trench is 1μm to 5μm; and the bottom width of the trench is 0.3μm to 3μm.
[0009] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the design of the trapezoidal cross-section trench structure optimizes the electric field distribution of the gate, reduces the crowding effect of the electric field at the gate edge, and improves the breakdown voltage of the device; the angle design reduces the formation of voids during the gate metal filling process and improves the process reliability; the trench depth and width design ensures the gate control capability while optimizing the switching speed and on-resistance of the device, thus improving the overall performance of the device.
[0010] The Schottky metal layer is composed of one or more metals selected from tungsten, molybdenum, titanium, nickel, and platinum; the thickness of the Schottky metal layer at the bottom of the trench is 50 nm to 150 nm; the thickness of the Schottky metal layer at the sidewall of the trench is 20 nm to 80 nm; and a nanoscale roughening structure is provided at the contact interface between the Schottky metal layer and the trench to enhance the contact area between the Schottky metal layer and the trench.
[0011] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: by using a metal material with a high work function to fabricate the Schottky metal layer, the leakage current of the gate is reduced; by designing the thickness of the Schottky metal layer at different positions in the trench, the electric field control capability of the gate is enhanced; setting the bottom thickness to be greater than the sidewall thickness is used to improve the gate's control effect on the channel region; by setting a nanoscale roughening structure, the contact area between the metal and the semiconductor is significantly increased, the contact resistance is reduced, and the current conduction capability of the device is improved.
[0012] Furthermore, the P-GaN layer adopts a gradient doping structure, with a high doping concentration on the side closer to the Schottky metal layer and a low doping concentration on the side farther from the Schottky metal layer; the doping concentration of the P-GaN layer decreases exponentially from the side closer to the Schottky metal layer to the side farther from the Schottky metal layer; the total thickness of the P-GaN layer is 100 nanometers to 500 nanometers.
[0013] The beneficial effects of the above-mentioned improvement scheme are as follows: the gradient doping structure of the P-GaN layer forms a built-in electric field, which enhances the gate's depletion capability in the channel region; the highly doped region near the Schottky metal layer reduces the contact resistance between the metal and the P-GaN; the use of an exponentially decreasing doping concentration creates a smooth electric field distribution, reducing carrier scattering and improving carrier mobility; and the design of the P-GaN layer thickness ensures gate control capability while avoiding the high resistance problem caused by excessive thickness.
[0014] Furthermore, the substrate is a silicon carbide substrate or a sapphire substrate; the thickness of the substrate is 200μm to 500μm; the surface of the substrate is polished and the surface roughness is less than 0.1nm; the diameter of the substrate is 2in to 6in.
[0015] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: by using high-quality substrate materials such as silicon carbide or sapphire, good lattice matching and thermal conductivity are provided, and the dislocation density of the epitaxial layer is reduced; the design of the substrate thickness takes into account both mechanical strength and thermal resistance; the high-precision surface polishing process reduces interface scattering and defects, and improves the quality of the epitaxial layer; and the design of the substrate size improves production efficiency and cost-performance ratio.
[0016] Furthermore, the buffer layer includes a bottom buffer sublayer and a top buffer sublayer; the bottom buffer sublayer is directly disposed on the surface of the substrate; the top buffer sublayer is disposed on the upper surface of the bottom buffer sublayer; the thickness of the bottom buffer sublayer is 10nm to 50nm; the thickness of the top buffer sublayer is 1μm to 3μm; the bottom buffer sublayer and the top buffer sublayer are integrally formed by in-situ epitaxy.
[0017] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: by adopting a double-layer buffer layer structure, the lattice mismatch and thermal expansion coefficient difference between the substrate and the functional layer are effectively alleviated, and the dislocation density of the epitaxial layer is reduced; by designing a bottom buffer sublayer to provide an initial nucleation layer, the crystal quality of the epitaxial layer is improved; by providing a smooth transition through the top buffer sublayer, interface traps are reduced; and by adopting an in-situ epitaxial integral molding process, interface contamination is avoided, and interface quality and device performance are improved.
[0018] Furthermore, the sidewalls of the trench are inclined, with an upward inclination angle of 5° to 15° from the bottom of the trench; the four corners at the bottom of the trench adopt a rounded transition structure with a radius of 50nm to 100nm.
[0019] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the electric field distribution is optimized by the tilt design of the trench sidewall, the electric field concentration effect at the gate edge is reduced, and the breakdown voltage of the device is improved; the tilt angle design facilitates the subsequent filling of metal and P-GaN materials, improving the process reliability; the rounded transition structure at the bottom of the trench eliminates the sharp corner effect, reduces local electric field concentration, and improves the reliability and lifespan of the device.
[0020] Furthermore, the Schottky metal layer forms a raised structure in the central region at the bottom of the trench, with a raised height of 10nm to 30nm; the raised structure is semi-ellipsoidal, with its major axis parallel to the length direction of the trench.
[0021] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: by designing a bump structure to enhance the gate's control capability over the channel region, the switching speed of the device is improved; the use of a semi-ellipsoidal bump structure forms a smooth electric field distribution, reducing local electric field concentration; the design of the bump structure's long axis being parallel to the trench optimizes the current distribution, improving the device's current density and power density.
[0022] Furthermore, an arc-shaped protrusion is formed on the top surface of the P-GaN layer, with an arc height of 10nm to 50nm; the cross-section of the arc-shaped protrusion has a smooth transition bell-shaped curve shape.
[0023] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the electric field distribution between the gate and the source is optimized by designing an arc-shaped protrusion structure, which improves the breakdown voltage of the device; the bell-shaped curve shape with smooth transition reduces the sharp corner effect and local electric field concentration; the arc structure increases the effective surface area and improves the heat dissipation capability.
[0024] Furthermore, the number of grooves is 3 to 10, and the multiple grooves are evenly distributed at intervals on the top surface of the buffer layer; the distance between adjacent grooves is 2 μm to 8 μm.
[0025] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the effective gate area is increased by the multi-trench design, which improves the current density and power density of the device; the current distribution is optimized by the uniformly distributed trench structure, which improves the current uniformity of the device; and the distance between adjacent trenches is designed to reduce interference between trenches, which improves the operating stability of the device.
[0026] Compared with existing technologies, the Schottky P-GaN gate structure provided by this invention offers the following advantages: By combining a Schottky metal layer and a P-GaN layer in a trench structure to form a composite gate structure, it achieves both the low on-resistance of a Schottky metal gate and the high breakdown voltage of a P-GaN gate. The trapezoidal trench design optimizes the electric field distribution and reduces the electric field concentration effect at the gate edge; the thickened Schottky metal layer at the bottom of the trench enhances the gate's control over the channel region; the gradient doping structure of the P-GaN layer creates a built-in electric field, enhancing the gate's depletion capability over the channel region; the dual-layer buffer layer structure effectively alleviates the lattice mismatch and thermal expansion coefficient difference between the substrate and the functional layer; the tilted design of the trench sidewalls and the rounded transition structure at the bottom eliminate sharp corner effects and reduce local electric field concentration; the raised structure of the Schottky metal layer at the bottom of the trench and the arc-shaped raised structure at the top of the P-GaN layer further optimize the electric field distribution; the multi-trench structure increases the effective gate area, improving the device's current density and power density. The overall effect is as follows: the breakdown voltage of the device is increased by more than 30%, the on-resistance is reduced by more than 25%, the gate leakage current is reduced by an order of magnitude, the high-temperature stability is significantly improved, the operating temperature range is extended to more than 200℃, while maintaining good process feasibility and cost-effectiveness. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of a Schottky P-GaN gate structure;
[0029] Figure 2 This is a schematic diagram of the top of a single trench in a Schottky P-GaN gate structure;
[0030] Figure 3 This is a side cross-sectional view of a single trench in a Schottky P-GaN gate structure;
[0031] Figure 4 This is a partial schematic diagram of the P-GaN layer in a Schottky P-GaN gate structure.
[0032] The attached diagram lists the components represented by each number as follows:
[0033] 10. Substrate; 11. Buffer layer; 111. Bottom buffer sublayer; 112. Top buffer sublayer; 12. Trench gate structure; 13. Schottky metal layer; 14. P-GaN layer; 15. Bump structure; 16. Arc bump. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.
[0035] like Figure 1-4 The diagram illustrates an embodiment of a Schottky P-GaN gate structure provided by this invention. This embodiment includes a substrate 10, a buffer layer 11, a trench gate structure 12, a Schottky metal layer 13, and a P-GaN layer 14. The buffer layer 11 is sequentially disposed on the substrate 10. A trench gate structure 12 is formed on the buffer layer 11. The trench gate structure 12 includes multiple trenches arranged parallel to each other. A Schottky metal layer 13 and a P-GaN layer 14 are sequentially disposed on the bottom and sidewalls of each trench. The Schottky metal layer 13 is tightly bonded to the bottom and sidewalls of the trench. The P-GaN layer 14 fills the area above the Schottky metal layer 13, and the top of the P-GaN layer 14 is flush with the top surface of the buffer layer 11. The thickness of the Schottky metal layer 13 is greater at the bottom of the trench than at the sidewalls. The thickness of the P-GaN layer 14 is greater in the central region of the trench than at the edge region. The distance between two adjacent trenches in the trench gate structure 12 is 1.5 to 3 times the trench width.
[0036] In the above technical solution, the trench has a trapezoidal cross-sectional structure, with the bottom width being smaller than the top width; the angle between the bottom of the trench and the sidewall is 120° to 160°; the depth of the trench is 0.5μm to 3μm; the top width of the trench is 1μm to 5μm; and the bottom width of the trench is 0.3μm to 3μm.
[0037] In the above technical solution, the Schottky metal layer 13 is composed of one or more metals selected from tungsten, molybdenum, titanium, nickel, and platinum; the thickness of the Schottky metal layer 13 at the bottom of the trench is 50 nm to 150 nm; the thickness of the Schottky metal layer 13 at the sidewall of the trench is 20 nm to 80 nm; and a nanoscale roughening structure is provided at the contact interface between the Schottky metal layer 13 and the trench to enhance the contact area between the Schottky metal layer 13 and the trench.
[0038] Furthermore, in the above technical solution, the P-GaN layer 14 adopts a gradient doping structure, with a high doping concentration on the side closer to the Schottky metal layer 13 and a low doping concentration on the side farther from the Schottky metal layer 13; the doping concentration of the P-GaN layer 14 decreases exponentially from the side closer to the Schottky metal layer 13 to the side farther from the Schottky metal layer 13; the total thickness of the P-GaN layer 14 is 100 nanometers to 500 nanometers.
[0039] Furthermore, in the above technical solution, the substrate 10 is a silicon carbide substrate or a sapphire substrate; the thickness of the substrate 10 is 200μm to 500μm; the surface of the substrate 10 is polished and the surface roughness is less than 0.1nm; the diameter of the substrate 10 is 2in to 6in.
[0040] Furthermore, in the above technical solution, the buffer layer 11 includes a bottom buffer sublayer 111 and a top buffer sublayer 112; the bottom buffer sublayer 111 is directly disposed on the surface of the substrate 10; the top buffer sublayer 112 is disposed on the upper surface of the bottom buffer sublayer 111; the thickness of the bottom buffer sublayer 111 is 10nm to 50nm; the thickness of the top buffer sublayer 112 is 1μm to 3μm; the bottom buffer sublayer 111 and the top buffer sublayer 112 are integrally formed by in-situ epitaxy.
[0041] Furthermore, in the above technical solution, the sidewalls of the trench are inclined, with an upward inclination angle of 5° to 15° from the bottom of the trench; the four corners at the bottom of the trench adopt a rounded transition structure with a radius of 50nm to 100nm.
[0042] Furthermore, in the above technical solution, the Schottky metal layer 13 forms a protrusion structure 15 in the central region at the bottom of the trench, with a protrusion height of 10nm to 30nm; the protrusion structure 15 is semi-ellipsoidal, with its major axis parallel to the trench length direction.
[0043] Furthermore, in the above technical solution, an arc-shaped protrusion 16 is formed on the top surface of the P-GaN layer 14, with an arc height of 10nm to 50nm; the cross-section of the arc-shaped protrusion 16 has a smooth transition bell-shaped curve shape.
[0044] Furthermore, in the above technical solution, the number of grooves is 3 to 10, and the multiple grooves are evenly distributed on the top surface of the buffer layer 11; the distance between adjacent grooves is 2μm to 8μm.
[0045] Specifically, the principle of this invention is as follows: by combining a Schottky metal layer and a P-GaN layer in a trench structure to form a composite gate structure, complementary advantages are achieved. First, the trapezoidal cross-section of the trench structure alters the electric field distribution, mitigating the electric field concentration effect at the gate edge and improving the device's breakdown voltage. Second, the Schottky junction formed by the Schottky metal layer and the semiconductor provides low on-resistance characteristics, while the barrier formed by the P-GaN layer increases the gate's breakdown voltage. By increasing the thickness of the Schottky metal layer at the bottom of the trench, the gate's control over the channel region is strengthened. The gradient doping structure of the P-GaN layer creates a built-in electric field, enhancing the gate's depletion capability over the channel region while reducing contact resistance. The double-layer buffer layer structure alleviates the lattice mismatch and thermal expansion coefficient difference between the substrate and the functional layer, improving the epitaxial layer quality. The tilted design of the trench sidewalls and the rounded transition structure at the bottom eliminate sharp corner effects and reduce local electric field concentration. The protruding structure of the metal layer and the arc design of the P-GaN layer further optimize the electric field distribution. The multi-trench structure increases the effective gate area, thereby improving the current density and power density of the device.
Claims
1. A Schottky P-GaN gate structure, characterized in that, The structure includes a substrate, a buffer layer, a trench gate structure, a Schottky metal layer, and a P-GaN layer. A buffer layer is sequentially disposed on the substrate. A trench gate structure is formed on the buffer layer. The trench gate structure includes multiple parallel trenches. A Schottky metal layer and a P-GaN layer are sequentially disposed on the bottom and sidewalls of each trench. The Schottky metal layer is tightly adhered to the bottom and sidewalls of the trench. The P-GaN layer fills the space above the Schottky metal layer, and the top of the P-GaN layer is flush with the top surface of the buffer layer. The thickness of the Schottky metal layer is greater at the bottom of the trench than at the sidewalls. The thickness of the P-GaN layer is greater in the central region of the trench than at the edge region. The distance between two adjacent trenches in the trench gate structure is 1.5 to 3 times the trench width.
2. The Schottky P-GaN gate structure according to claim 1, characterized in that, The trench has a trapezoidal cross-section structure, with the bottom width being smaller than the top width; the angle between the bottom of the trench and the sidewall is 120°~160°; the depth of the trench is 0.5μm~3μm; the top width of the trench is 1μm~5μm; and the bottom width of the trench is 0.3μm~3μm.
3. The Schottky P-GaN gate structure according to claim 1, characterized in that, The thickness of the Schottky metal layer is 50nm~150nm at the bottom of the trench; the thickness of the Schottky metal layer at the sidewall of the trench is 20nm~80nm; the contact interface between the Schottky metal layer and the trench is provided with a nanoscale roughening structure to enhance the contact area between the Schottky metal layer and the trench.
4. A Schottky P-GaN gate structure according to claim 3, characterized in that, The substrate is a silicon carbide substrate or a sapphire substrate; the thickness of the substrate is 200μm~500μm; the surface of the substrate is polished and the surface roughness is less than 0.1nm; the diameter of the substrate is 2in~6in.
5. A Schottky P-GaN gate structure according to claim 4, characterized in that, The buffer layer includes a bottom buffer sublayer and a top buffer sublayer; the bottom buffer sublayer is directly disposed on the surface of the substrate; the top buffer sublayer is disposed on the upper surface of the bottom buffer sublayer; the thickness of the bottom buffer sublayer is 10nm~50nm; the thickness of the top buffer sublayer is 1μm~3μm; the bottom buffer sublayer and the top buffer sublayer are integrally formed by in-situ epitaxy.
6. A Schottky P-GaN gate structure according to claim 5, characterized in that, The sidewalls of the trench are inclined, with an upward inclination angle of 5° to 15° from the bottom of the trench; the four corners of the bottom of the trench adopt a rounded transition structure with a radius of 50nm to 100nm.
7. A Schottky P-GaN gate structure according to claim 6, characterized in that, The Schottky metal layer forms a raised structure in the central region at the bottom of the trench, with a raised height of 10nm~30nm; the raised structure is semi-ellipsoidal, with its major axis parallel to the length of the trench.
8. A Schottky P-GaN gate structure according to claim 7, characterized in that, The top surface of the P-GaN layer forms an arc-shaped protrusion with a height of 10nm~50nm.
9. A Schottky P-GaN gate structure according to claim 8, characterized in that, The number of grooves is 3 to 10, and the multiple grooves are evenly distributed at intervals on the top surface of the buffer layer; the distance between adjacent grooves is 2μm to 8μm.