Temporary carrier plate for transferring semiconductor device and packaging structure of semiconductor device
By using a simple temporary carrier board and packaging structure for transfer semiconductor devices, the problems of low efficiency and high cost of traditional packaging technologies are solved, and efficient and reliable Mini/Micro-LED packaging is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JIANGXI DING WAA SAM TAI TECH CO LTD
- Filing Date
- 2025-05-21
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional semiconductor packaging technology is inefficient when processing large numbers of tiny chips, suffers from connection reliability issues, and is costly, making it difficult to meet the mass transfer requirements of Mini/Micro-LED.
A temporary carrier board for transferring semiconductor devices with a simple structure and good versatility is adopted, including a carrier board and a peelable adhesive layer. The transfer unit has electrodes, and the working electrodes are formed by electroplating metal and connected to the unit circuit. In the packaging structure, the wiring layer is on the peelable surface of the package.
It achieves efficient and reliable semiconductor device packaging, applicable to different types of semiconductor devices, reducing costs and improving transfer accuracy and connection reliability.
Smart Images
Figure CN224234102U_ABST
Abstract
Description
[TECHNICAL FIELD]
[0001] The utility model relates to miniaturized semiconductor device package especially relates to a temporary carrier plate of transferring semiconductor device and the packaging structure of semiconductor device. [BACKGROUND]
[0002] With the continuous development of semiconductor technology and the increasing demand of downstream applications (such as display, lighting) for integration, miniaturization and high resolution, especially the rise of Mini / Micro-LED technology, the traditional semiconductor packaging technology is facing great challenges.
[0003] Traditional chip packaging methods, such as lead frame packaging (Leadframe Packaging), ball grid array packaging (BGA), chip flip-chip soldering to printed circuit board (PCB) or ceramic substrate (COB / COG), etc., usually rely on connecting chips to hard substrates through wire bonding or solder paste welding. These methods are inefficient when handling a large number of small chips, and have many problems:
[0004] 1) Substrate limitations: traditional substrates such as PCB have problems such as low dimensional accuracy, mismatched thermal expansion coefficient (CTE) with chips, easy warping, easy moisture absorption and expansion, etc. In high-precision, large-area display applications, these problems will cause pixel distortion, reduced connection reliability, and reduced yield.
[0005] 2) Connection efficiency and reliability: traditional wire bonding and solder paste welding processes are slow and have limited precision, and are prone to problems such as false welding, tin connection, missed welding, short circuit, broken wire, etc. Especially for a large number of Mini / Micro-LED chips, welding / wire bonding is the main yield bottleneck. Gold wire bonding is expensive, limiting the use of lower-cost aluminum electrode chips. The alignment accuracy of solder paste printing cannot meet the needs of Micro-LED.
[0006] 3) Poor adaptability to mass transfer: traditional substrate design (pad size, spacing, layout) and subsequent connection processes (soldering, wire bonding) are difficult to perfectly match the mass transfer technology required by Micro-LED, limiting the improvement of production efficiency.
[0007] 4) Cost problem: traditional process flow is long, material cost (such as gold wire, high-level substrate) is high, and manufacturing cost is high.
[0008] In recent years, fan-out packaging technology as an advanced packaging method has been developed, and some forms (such as Fan-Out Panel Level Packaging, FOPLP) use temporary carriers, plastic packaging, and form a redistribution layer (RDL) on the surface of the plastic package to build a packaging structure, overcoming the size limitations of round crystals and improving integration. Mass transfer technology has also emerged to greatly improve the transfer efficiency of small chips. However, the existing FOPLP or mass transfer and packaging combined technical solutions still need to be optimized in terms of precise alignment of extremely high-density, extremely small-size devices and ensuring the reliability of subsequent electrical connections. For example, how to provide a high-precision, easy-to-align reference for mass transfer, and how to ensure that the small chip pads embedded in the plastic package form extremely reliable connections with the RDL layer on the surface of the plastic package, especially without using traditional soldering or wire bonding, is still a technical challenge.
[0009] The application with the application number 202311152821.2 discloses a packaging method of MIP chip, which sequentially includes a manufacturing process of packaging carrier, a mass transfer process of three-color Micro LED chip, a packaging process and a segmentation process; the packaging carrier includes a carrier circuit and a glass carrier plate, and the glass carrier plate is fixed on the bottom surface of the carrier circuit in a peelable manner; the carrier circuit includes a substrate and a plurality of unit circuits arranged in an array, and each unit circuit includes at least one group of three-color chip pads, at least four bottom electrodes and a circuit connecting the three-color chip pads and the bottom electrodes. The application has the following disadvantages: 1) the carrier circuit structure is complex and has poor universality; 2) the pre-prepared carrier circuit may be deformed due to thermal stress when the packaging glue is cured, resulting in misalignment of the pads and the chip electrodes, and poor alignment of the transferred semiconductor devices; 3) in the packaging structure, the electrode connection is mainly realized through the unit circuit of the carrier circuit, and the unit circuit includes three-color chip pads and bottom electrodes, and the connection mode is relatively fixed and mainly used for specific Micro LED chip packaging. [SUMMARY]
[0010] The technical problem to be solved by the utility model is to provide a temporary carrier for transferring semiconductor devices, which has simple structure and good universality.
[0011] Another technical problem to be solved by the utility model is to provide a packaging structure for semiconductor devices, which has good universality and is suitable for different types of semiconductor devices.
[0012] In order to solve the above technical problems, the utility model adopts the technical scheme, a kind of temporary carrier plate of transfer semiconductor device, including bearing plate and the peelable adhesive layer covered in the top surface of bearing plate, the top surface of peelable adhesive layer includes multiple transfer unit arranged in array, and transfer unit includes the transfer area of semiconductor device;Transfer unit includes multiple electrode pasted in the top surface of peelable adhesive layer.
[0013] The temporary carrier plate described above, the electrode is a switching electrode shaped as a working electrode 16.
[0014] The temporary carrier plate described above includes an electrode plate, the electrode plate includes a substrate, the substrate includes substrate units corresponding to the transfer units, the substrate units include a plurality of the electrodes, and the electrodes are embedded in holes of the substrate; the bottom surface of the substrate is pasted to the top surface of the peelable adhesive layer.
[0015] The temporary carrier plate described above, the electrode is a working electrode, the working electrode includes a top electrode and a bottom electrode, the top surface of the top electrode is substantially flush with the top surface of the substrate, and the bottom surface of the bottom electrode is substantially flush with the bottom surface of the substrate; the substrate unit includes a chip transfer hole, and the chip transfer hole of the substrate unit surrounds the outer periphery of the transfer area on the top surface of the peelable adhesive layer.
[0016] A packaging structure of a semiconductor device includes a package body, an insulating layer, and a plurality of working electrodes, the package body includes a packaging adhesive and the semiconductor device, the bottom surface of the package body is a peel-off surface, and all electrodes of the semiconductor device are exposed on the peel-off surface; the packaging structure includes a wiring layer, the wiring layer is made on the peel-off surface of the package body, the wiring layer includes unit circuits, the unit circuits are connected to the electrodes of the semiconductor device; the insulating layer covers the peel-off surface of the package body, the unit circuits, and the electrodes of the semiconductor device.
[0017] The packaging structure further includes:
[0018] When the unit circuits are connected to a plurality of switching electrodes, the insulating layer includes working electrode windows corresponding to the switching electrodes, the working electrodes are formed in the working electrode windows by electroplating metal, and are connected to the corresponding switching electrodes;
[0019] When the packaging structure includes an electrode plate, the working electrodes are embedded in the electrode plate, the working electrodes are connected to the unit circuits, the top surface of the working electrodes is exposed to the top surface of the electrode plate, and the insulating layer covers the bottom surface of the electrode plate.
[0020] The packaging structure described above, the insulating layer is a solder resist ink layer.
[0021] The packaging structure described above, the electrode base plate or the switching electrode in the working electrode window forms the working electrode by copper plating and solderable metal plating.
[0022] The packaging structure described above, the electrode plate includes a substrate and a plurality of working electrodes embedded in the holes of the substrate, the working electrode includes a top electrode and a bottom electrode, the top surface of the top electrode is exposed to the top surface of the substrate, and the insulating layer covers the bottom surface of the substrate and the bottom electrode of the working electrode; the substrate includes a chip transfer hole, the semiconductor device is arranged in the chip transfer hole of the substrate, and the packaging glue fills the chip transfer hole and covers the semiconductor device.
[0023] The packaging structure described above, the semiconductor device includes an LED chip or a diode, or a combination of an LED chip and an LED driving chip, and the LED chip includes a Mini-LED chip or a Micro-LED chip.
[0024] The temporary carrier plate has simple structure and good universality, and the packaging structure of the semiconductor device has good universality and is suitable for different types of semiconductor devices. [DETAILED DESCRIPTION]
[0025] The utility model will be further explained in detail in combination with the drawings and specific embodiments.
[0026] Figure 1 It is a schematic diagram of step 101 of the packaging method of the embodiment 1 of the utility model.
[0027] Figure 2 It is a schematic diagram of step 102 of the packaging method of the embodiment 1 of the utility model.
[0028] Figure 3 It is a schematic diagram of step 103 of the packaging method of the embodiment 1 of the utility model.
[0029] Figure 4 It is Figure 3 the top view.
[0030] Figure 5 It is a schematic diagram of step 2 of the packaging method of the embodiment 1 of the utility model.
[0031] Figure 6 It is Figure 5 the top view.
[0032] Figure 7 It is a schematic diagram of step 3 of the packaging method of the embodiment 1 of the utility model.
[0033] Figure 8 It is a schematic diagram of step 4 of the packaging method of the embodiment 1 of the utility model.
[0034] Figure 9 It is a schematic diagram of step 501 of the packaging method of the embodiment 1 of the utility model.
[0035] Figure 10 is a schematic diagram of step 502 of the packaging method of the embodiment 1 of the utility model.
[0036] Figure 11 is a schematic diagram of step 503 of the packaging method of the embodiment 1 of the utility model.
[0037] Figure 12 is a schematic diagram of step 504 of the packaging method of the embodiment 1 of the utility model.
[0038] Figure 13 is a top view of Figure 12 .
[0039] Figure 14 is a schematic diagram of step 6 of the packaging method of the embodiment 1 of the utility model.
[0040] Figure 15 is a schematic diagram of step 7 of the packaging method of the embodiment 1 of the utility model.
[0041] Figure 16 is a schematic diagram of step 8 of the packaging method of the embodiment 1 of the utility model.
[0042] Figure 17 is a schematic diagram of the packaging structure of the embodiment 1 of the utility model.
[0043] Figure 18 is a schematic diagram of step 2 of the packaging method of the embodiment 2 of the utility model.
[0044] Figure 19 is a top view of Figure 18 .
[0045] Figure 20 is a schematic diagram of the packaging structure of the embodiment 2 of the utility model.
[0046] Figure 21 is a schematic diagram of step 1 of the packaging method of the embodiment 3 of the utility model.
[0047] Figure 22 is a schematic diagram of step 2 of the packaging method of the embodiment 3 of the utility model.
[0048] Figure 23 is a top view of Figure 22 .
[0049] Figure 24 is a schematic diagram of step 3 of the packaging method of the embodiment 3 of the utility model.
[0050] Figure 25 is a schematic diagram of step 4 of the packaging method of the embodiment 3 of the utility model.
[0051] Figure 26 is a schematic diagram of step 5 of the packaging method of the embodiment 3 of the utility model.
[0052] Figure 27 is the schematic diagram of step 6 of the packaging method of the embodiment 3 of the utility model.
[0053] Figure 28 is the schematic diagram of step 7 of the packaging method of the embodiment 3 of the utility model.
[0054] Figure 29 is the schematic diagram of step 8 of the packaging method of the embodiment 3 of the utility model.
[0055] Figure 30 is the schematic diagram of the packaging structure of the embodiment 3 of the utility model.
[0056] Figure 31 is the schematic diagram of step 2 of the packaging method of the embodiment 4 of the utility model.
[0057] Figure 32 is the top view of Figure 31 .
[0058] Figure 33 is the schematic diagram of the packaging structure of the embodiment 4 of the utility model.
[0059] Figure 34 is the schematic diagram of the packaging method of the embodiment 5 of the utility model.
[0060] Figure 35 is the schematic diagram of step 1 of the packaging method of the embodiment 6 of the utility model.
[0061] Figure 36 is the top view of Figure 35 .
[0062] Figure 37 is the schematic diagram of step 2 of the packaging method of the embodiment 6 of the utility model.
[0063] Figure 38 is one of the schematic diagrams of step 3 of the packaging method of the embodiment 6 of the utility model.
[0064] Figure 39 is the second schematic diagram of step 3 of the packaging method of the embodiment 6 of the utility model.
[0065] Figure 40 is the third schematic diagram of step 3 of the packaging method of the embodiment 6 of the utility model.
[0066] Figure 41 is the schematic diagram of step 4 of the packaging method of the embodiment 6 of the utility model.
[0067] Figure 42 is the schematic diagram of step 5 of the packaging method of the embodiment 6 of the utility model.
[0068] Figure 43 is a top view of Figure 42 .
[0069] Figure 44 is a schematic view of step 6 of the packaging method of the embodiment 6 of the utility model.
[0070] Figure 45 is a schematic view of step 7 of the packaging method of the embodiment 6 of the utility model.
[0071] Figure 46 is a schematic view of the packaging structure of the embodiment 6 of the utility model. [DETAILED DESCRIPTION]
[0072] The packaging method of the miniaturized semiconductor device of the embodiment 1 of the utility model is as shown in Figures 1 to 17 , comprising the following steps:
[0073] 1) a temporary carrier plate for transferring semiconductor devices is made, the temporary carrier plate comprises a bearing plate 3 and a peelable adhesive layer 4 covering the top surface of the bearing plate 3, the top surface of the peelable adhesive layer 4 comprises a plurality of transfer regions 21 of semiconductor devices corresponding to transfer units arranged in an array; the transfer unit 20 comprises N transfer electrodes 2 pasted on the top surface of the peelable adhesive layer 4, and in this embodiment, N = 4:
[0074] 101) as shown in Figure 1 , according to the layout of the transfer unit 20 on the top surface of the bearing plate 3, the four transfer electrodes 2 of all the transfer units 20 are electroplated on the top surface of the stainless steel carrier plate 1;
[0075] 102) as shown in Figure 2 , the peelable adhesive layer 4 is covered on the top surface of the bearing plate 3, and the top surface of the peelable adhesive layer 4 is bonded with all the transfer electrodes 2 on the top surface of the stainless steel carrier plate 1, and in this embodiment, the bearing plate 3 is a glass plate;
[0076] 103) as shown in Figure 3 and Figure 4 , the stainless steel carrier plate 1 is peeled off from all the transfer electrodes 2, and all the transfer electrodes 2 are transferred to the peelable adhesive layer 4 of the temporary carrier plate, and the making of the temporary carrier plate for transferring semiconductor devices is completed;
[0077] 2) as shown in Figure 5 and Figure 6 , a large number of semiconductor devices 5 are transferred to the temporary carrier plate, including transferring semiconductor devices 5 to each transfer region 21, and a plurality of electrodes of the semiconductor device 5 are pasted downward on the peelable adhesive layer 4; the semiconductor device in this embodiment is an RGB LED chip combination, and the LED chip can be a Mini-LED chip or a Micro-LED chip;
[0078] 3) as shown in Figure 7As shown, encapsulating adhesive 7 is applied to all semiconductor devices 5, transfer electrodes 2 and peelable adhesive layer 4 of transfer unit 20 to form an encapsulation body;
[0079] 4) such as Figure 8 As shown, the package is peeled off from the temporary carrier, exposing the working surfaces of all electrodes on the semiconductor device 5 and all transition electrodes 2 on the peeled surface of the package.
[0080] 5) Fabricate a wiring layer. On the release surface of the package, fabricate a unit circuit corresponding to each transfer unit 20. The electrodes of the semiconductor device 5 of each transfer unit 20 are connected to the corresponding unit circuit, and the transfer electrode 2 of each transfer unit 20 is connected to the corresponding unit circuit.
[0081] 501) such as Figure 9 As shown, a photosensitive film 8 is applied to the release surface of the package, all the transfer electrodes 2, and the electrodes on the semiconductor device 5;
[0082] 502) such as Figure 10 As shown, exposure and development are performed to create a cutout pattern 81 on the photosensitive film 8 that corresponds to all unit circuits;
[0083] 503) such as Figure 11 As shown, titanium and copper are vacuum sputtered to form all the unit circuits 9 in the hollowed-out pattern 81;
[0084] 504) Remove the photosensitive film 8 and thicken the copper plating on the unit circuit, such as Figure 12 and Figure 13 As shown;
[0085] 6) such as Figure 14 As shown, a solder resist ink layer 10 is covered on the release surface of the package, and the solder resist ink layer 10 covers the release surface of the package, the unit circuit 9, and the electrodes of the semiconductor device; corresponding to each transfer unit 20 as follows... Figure 15 As shown, there are 4 working electrode windows 15 corresponding to the adapter electrode 2, and the adapter electrode 2 is exposed in the corresponding working electrode window 15.
[0086] 7) such as Figure 15 As shown, copper is plated in all working electrode windows 15 to form working electrodes 16 connected to the transfer electrode 2; the transfer electrode serves as the basis for the formation of working electrodes 16, and forms an electrical connection between working electrodes 16 and unit circuit 9.
[0087] 8) such as Figure 16 As shown, the working electrode 16 is surface treated by plating a solderable metal layer 17 such as tin, silver or gold.
[0088] 9) such as Figure 17As shown, the package and the solder resist ink layer 10 are cut to obtain a packaging unit of the semiconductor device.
[0089] As shown, Figure 17 The packaging structure of the small-sized semiconductor device according to the embodiment 1 includes a package, an insulating layer and four working electrodes 16. The package includes a package adhesive 7 and a semiconductor device 5. The bottom surface of the package is a peeling surface, and all the electrodes of the semiconductor device 5 are exposed on the peeling surface. The packaging structure includes a wiring layer 9, which is formed on the peeling surface of the package. The wiring layer includes a unit circuit 9, which is connected to the electrodes of the semiconductor device. A solder resist ink layer (insulating layer) 10 covers the peeling surface of the package, the unit circuit 9 and the electrodes of the semiconductor device 5. The solder resist ink layer 10 includes four working electrode windows. There is a switching electrode 2 in each working electrode window, which is connected to the unit circuit 9. The bottom surface of the switching electrode 2 is flush with the peeling surface of the package. The working electrodes 16 are formed in the working electrode windows by electroplating copper and are connected to the corresponding switching electrodes 2. The outer surface of the working electrodes 16 is plated with a solderable metal 17 such as tin, gold or silver to form a solder pad. The packaging structure of the small-sized semiconductor device according to the embodiment 1 can be used for packaging of an LED chip or a diode, or a combination of an LED chip and an LED driving chip. However, the number of working electrodes 16 may be different for different semiconductor devices.
[0090] The packaging method of the small-sized semiconductor device according to the embodiment 2 is shown in Figures 18 to 20 The main difference between the embodiment 2 and the embodiment 1 is that the semiconductor device is a combination of an RGB LED chip and an LED driving chip. The packaging method of the small-sized semiconductor device according to the embodiment 2 includes the following steps:
[0091] 1) Step 1 is the same as step 1 of the embodiment 1;
[0092] 2) As shown in Figure 18 and Figure 19 , the semiconductor devices are transferred to the temporary carrier in large quantities. The difference between step 2 and step 2 of the embodiment 1 is that the semiconductor devices include an RGB LED chip combination 5A and an LED driving chip 5B. The RGB LED chip combination 5A is first transferred to each transfer area 21, and then the LED driving chip 5B is transferred to each transfer area 21. The multiple electrodes of the semiconductor devices 5A and 5B are pasted on the peelable adhesive layer 4. The LED chip can be a Mini-LED chip or a Micro-LED chip.
[0093] 3) Steps 3-9 are basically the same as steps 3-9 of the embodiment 1. The obtained packaging unit is shown in Figure 20 .
[0094] The packaging structure of the small-sized semiconductor device according to the embodiment 2 is shown in Figure 20As shown, the difference between the embodiment 1 small-sized semiconductor device packaging structure is that the semiconductor device is a combination of RGB LED chip 5A and LED driving chip 5B.
[0095] The packaging method of the small-sized semiconductor device in the embodiment 3 of the utility model is as shown in Figures 21 to 30 , which comprises the following steps:
[0096] 1) As shown in Figure 21 , a temporary carrier for transferring semiconductor devices is made, and the temporary carrier comprises a bearing plate 3 and a peelable adhesive layer 4 covering the top surface of the bearing plate 3; in this embodiment, no electrode is pasted on the peelable adhesive layer 4, and the number N of electrodes pasted on the top surface of the peelable adhesive layer 4 on the transfer unit 20 is 0:
[0097] 2) As shown in Figure 22 and Figure 23 , a large number of semiconductor devices are transferred to the temporary carrier, including transferring semiconductor devices 5 to each transfer area 21, and the multiple electrodes of the semiconductor devices 5 are pasted downward on the peelable adhesive layer 4; in this embodiment, the semiconductor devices 5 are a combination of RGB LED chips, and the LED chips can be Mini-LED chips or Micro-LED chips;
[0098] 3) As shown in Figure 24 , the packaging adhesive 7 is covered on the semiconductor devices 5 and the peelable adhesive layer 4 of all the transfer units 20 to form a packaging body;
[0099] 4) As shown in Figure 25 , the packaging body is peeled off from the temporary carrier, and the electrodes on all the semiconductor devices 5 are exposed on the peeling surface of the packaging body;
[0100] 5) As shown in Figure 26 , a wiring layer is made, and a unit circuit 9 is made on the peeling surface of the packaging body corresponding to each transfer unit 20, the electrodes of the semiconductor devices 5 of each transfer unit 20 are respectively connected with the corresponding unit circuit 9, and the unit circuit 9 of each transfer unit 20 comprises four electrode pads 91; the manufacturing process of the wiring layer is the same as steps 501-504 of embodiment 1;
[0101] 6) As shown in Figure 27 , a solder resist ink layer 10 is covered on the peeling surface of the packaging body, the unit circuit 9 and the electrodes of the semiconductor devices 5; corresponding to each transfer unit 20, as shown in Figure 27 , there are four working electrode windows 15 corresponding to the electrode pads 91, and the electrode pads 91 are exposed in the corresponding working electrode windows 15,
[0102] 7) As shown in Figure 28As shown, copper plating is performed in all working electrode windows 15 to form working electrodes 16 connected with electrode base disks 91; the electrode base disks 9 serve as the basis for forming the working electrodes 16, and the working electrodes 16 are electrically connected with the unit circuit 9;
[0103] 8) As shown in Figure 29 The working electrodes 16 are subjected to surface treatment to form a solderable metal layer 17 such as tin, silver or gold;
[0104] 9) As shown in Figure 30 The package and the solder resist ink layer 10 are cut to obtain a packaged unit of the semiconductor device.
[0105] The packaged structure of the miniaturized semiconductor device according to the embodiment 3 is as shown in Figure 30 The difference from the packaged structure of the embodiment 1 is that the relay electrode 2 is not included, and the unit circuit 9 includes electrode base disks 91, the electrode base disks 91 are located in the corresponding working electrode windows, and the working electrodes 16 are formed in the working electrode windows by copper plating and are connected with the corresponding electrode base disks 91.
[0106] The packaged method of the miniaturized semiconductor device according to the embodiment 4 is as shown in Figures 31 to 33 The main difference between the embodiment 4 and the embodiment 3 is that the semiconductor device is a combination of RGB LED chips and LED driving chips. The packaged method of the miniaturized semiconductor device according to the embodiment 4 includes the following steps:
[0107] 1) Step 1 is the same as step 1 of the embodiment 3;
[0108] 2) As shown in Figure 31 and Figure 32 The semiconductor devices are transferred to the temporary carrier in large quantities, and the difference between step 2 and step 2 of the embodiment 3 is that the combination of RGB LED chips 5A and the LED driving chips 5B are included; the RGB LED chip combination 5A is first transferred to each transfer area 21, and then the LED driving chip 5B is transferred to each transfer area 21, and the multiple electrodes of the semiconductor devices 5A and 5B are pasted downward on the peelable adhesive layer 4; the LED chip can be a Mini-LED chip or a Micro-LED chip;
[0109] 3) Steps 3-9 are basically the same as steps 3-9 of the embodiment 3, and the obtained packaged unit is as shown in Figure 33 .
[0110] The packaged structure of the miniaturized semiconductor device according to the embodiment 4 is as shown in Figure 33As shown, the difference between the packaging structure of the embodiment 3 is that the transfer electrode 2 is not included, and the unit circuit 9 includes the electrode base disc 91, the electrode base disc 91 is located in the corresponding working electrode window, the working electrode 16 is formed in the working electrode window by electroplating copper, and is connected with the corresponding electrode base disc 91.
[0111] The packaging method of the miniaturized semiconductor device of the embodiment 5 is as shown in the figure, Figure 34 The main difference between the embodiment 5 and the embodiment 1 is that, when the temporary carrier plate for transferring the semiconductor device is manufactured in step 1, the transfer unit 20 includes the main circuit 92 of the unit circuit. As shown in the figure, Figure 34 As shown in the figure, in step 101, the main circuit 92 is electroplated on the top surface of the stainless steel carrier plate at the same time as the transfer electrode 2, the main circuit 92 is connected with the transfer electrode, and extends to the transfer area of the semiconductor device; in step 102, the top surface of the carrier plate is covered with a peelable adhesive layer, including bonding the top surface of the peelable adhesive layer with all the main circuits 92 on the top surface of the stainless steel carrier plate; in step 103, including peeling off the stainless steel carrier plate and all the main circuits 92, and transferring all the main circuits 92 to the peelable adhesive layer of the temporary carrier plate.
[0112] The packaging method of the miniaturized semiconductor device of the embodiment 6 is as shown in the figure, Figures 35 to 46 The main difference between the embodiment 6 and the embodiment 1 is that the semiconductor device 5 is a semiconductor chip, and the temporary carrier plate includes an electrode plate 30, the electrode plate 30 includes a base plate 31, the base plate 31 includes a base plate unit 30A corresponding to the transfer area 21 of the semiconductor device, and there are four working electrodes 16 in the base plate unit 30A, the working electrodes 16 are embedded in the holes of the base plate 31, including a top electrode 161 and a bottom electrode 162, the top surface of the top electrode 161 is basically flush with the top surface of the base plate 31, and the bottom surface of the bottom electrode 162 is basically flush with the bottom surface of the base plate 31; the base plate unit 30A includes a chip transfer hole 33, and the chip transfer hole 33 of the base plate unit 30A surrounds the outer periphery of the transfer area 21 on the top surface of the peelable adhesive layer.
[0113] The packaging method of the miniaturized semiconductor device of the embodiment 6 includes the following steps:
[0114] 1) As shown in the figure, Figure 35 And Figure 36 The temporary carrier plate for transferring the semiconductor device is manufactured, and the electrode plate 30 is pasted on the top surface of the carrier plate 3 through the peelable adhesive layer 4:
[0115] 2) As shown in the figure, Figure 37 The semiconductor device 5 is massively transferred to the temporary carrier plate, including transferring the semiconductor device 5 to the transfer area 21 in each base plate unit 30A chip transfer hole 33, the semiconductor device 5 is a semiconductor chip, and multiple electrodes of the semiconductor device 5 are pasted on the peelable adhesive layer 4 downward;
[0116] 3) such as Figure 38 As shown, encapsulating adhesive 7 is filled into the chip transfer holes 33 of each substrate unit 30A, covering the semiconductor devices 5 and the peelable adhesive layer 4 in all transfer units 20 to form an encapsulation; as shown Figure 39 As shown, the top surface of the encapsulating adhesive 7 and the top surface of the electrode plate 30 are ground flat, as follows. Figure 40 As shown, a protective film 18 is then applied to the top surface of the encapsulating adhesive 7 and the top surface of the electrode plate 30.
[0117] 4) such as Figure 41 As shown, the package is peeled off from the temporary carrier, exposing all the electrodes on the semiconductor device 5 and the bottom electrode 162 of all the working electrodes 16 on the electrode plate 30 on the peeled surface of the package.
[0118] 5) Create the wiring layer, such as Figure 42 and Figure 43 As shown, a unit circuit 9 is fabricated on the peeling surface of the package corresponding to each transfer unit 20. The electrodes of the semiconductor device 5 of each transfer unit 20 are connected to the corresponding unit circuit 9. The bottom electrode 162 of each substrate unit working electrode 16 is connected to the corresponding unit circuit 9. The fabrication process of the wiring layer is the same as steps 501-504 of Embodiment 1.
[0119] 6) such as Figure 44 As shown, a solder resist ink layer 10 is covered on the release surface of the package, and the solder resist ink layer 10 covers the release surface of the package, the unit circuit 9, the electrodes of the semiconductor device 5 and the bottom electrode 162 of the working electrode 16.
[0120] 7) such as Figure 45 As shown, the protective film 18 is removed to expose the top electrode 161 of all working electrodes 16. The top electrode 161 of the working electrodes 16 is then surface-treated by plating a solderable metal layer 17 such as tin, silver or gold.
[0121] 8) such as Figure 46 As shown, the package body and solder resist ink layer 10 are cut to obtain the package unit of the semiconductor device.
[0122] The packaging structure of the miniaturized semiconductor device in Embodiment 6 of this utility model is as follows: Figure 46As shown, the difference between the package structure of the miniaturized semiconductor device of Example 1 is that the semiconductor device 5 is a semiconductor chip, and in addition, the package structure of Example 6 comprises an electrode plate 30, the electrode plate 30 comprises a substrate 31, the substrate 31 is embedded with working electrodes 16, the working electrodes comprise top electrodes 161 and bottom electrodes 162, the bottom electrodes 162 are connected with the unit circuit 9, the top electrodes 161 are exposed on the top surface of the substrate 31, and the outer surface of the top electrodes 161 is plated with a solderable metal 17 such as tin, gold or silver to form a solder pad. The substrate comprises a chip transfer hole, the semiconductor device 5 is arranged in the chip transfer hole of the substrate 31, the encapsulating adhesive 7 fills the chip transfer hole and covers the semiconductor device 5, and the solder resist ink layer 10 covers the unit circuit 9, the bottom surface of the encapsulating adhesive 7, the electrodes of the semiconductor device 5 and the bottom surface of the electrode plate 30.
[0123] Those skilled in the art can understand that the package method and package structure of the miniaturized semiconductor device of the utility model embodiment 6 are only described by taking a semiconductor chip as an example, but are also applicable to the package of other miniaturized semiconductor devices such as an LED chip or a diode, or a combination of an LED chip and an LED driving chip.
[0124] The main difference between the package method of the miniaturized semiconductor device of the utility model embodiment 7 and that of Example 1 is that the semiconductor device is a diode, and the transfer unit 20 comprises N transfer electrodes which are attached to the top surface of the peelable adhesive layer 4, and in this embodiment 7, N = 2.
[0125] The main difference between the package method of the miniaturized semiconductor device of the utility model embodiment 8 and that of Example 3 is that the semiconductor device is a diode, and in step 5 of Example 3, the unit circuit 9 of each transfer unit 20 comprises two electrode pads 91, in step 6 of Example 3, the unit circuit forms two working electrode windows 15 corresponding to the electrode pads 91, and in step 7 of Example 3, two working electrodes 16 connected with the electrode pads 91 are formed.
[0126] The utility model embodiments have the following beneficial effects:
[0127] 1) The carrier board has a simple structure and good versatility; no pre-made circuit is needed, and no thermal stress deformation will occur;
[0128] 2) The carrier board can be reused, and the cost is relatively low;
[0129] 3) The transfer electrodes pre-arranged on the temporary carrier board serve as high-precision alignment references, reducing the positional deviation of the electrodes during mass transfer; the electrode plate embedded with working electrodes can provide mechanical support, improving the rigidity of the temporary carrier board;
[0130] 4) In the package structure, the wiring layer is made on the peeling surface of the package body and connected with the electrodes of the semiconductor device, and the unit circuit can meet the requirements of different semiconductor devices, and has good versatility.
Claims
1. A temporary carrier for transferring semiconductor devices, comprising a carrier plate and a peelable adhesive layer covering the top surface of the carrier plate, characterized in that, The top surface of the peelable adhesive layer includes a plurality of transfer units arranged in an array, each transfer unit including a transfer region of a semiconductor device; the transfer unit includes a plurality of electrodes attached to the top surface of the peelable adhesive layer.
2. The temporary carrier plate according to claim 1, characterized in that, The electrode in question is a transfer electrode that forms the basis for the working electrode.
3. The temporary carrier plate according to claim 1, characterized in that, It includes an electrode plate, which includes a substrate. The substrate includes a substrate unit corresponding to the transfer unit. The substrate unit includes a plurality of electrodes, which are embedded in holes in the substrate. The bottom surface of the substrate is attached to the top surface of the peelable adhesive layer.
4. The temporary carrier plate according to claim 1, characterized in that, The electrode is a working electrode, which includes a top electrode and a bottom electrode. The top surface of the top electrode is substantially flush with the top surface of the substrate, and the bottom surface of the bottom electrode is substantially flush with the bottom surface of the substrate. The substrate unit includes a chip transfer hole, which surrounds the transfer area on the top surface of the peelable adhesive layer.
5. A packaging structure for a semiconductor device, comprising a package body, an insulating layer, and a plurality of working electrodes, wherein the package body comprises encapsulating adhesive and the semiconductor device, characterized in that, The bottom surface of the package is a release surface, exposing the electrodes of all semiconductor devices. The package structure includes a wiring layer fabricated on the release surface of the package. The wiring layer includes unit circuits, which are connected to the electrodes of the semiconductor devices. The insulating layer covers the release surface of the package, the unit circuit, and the electrodes of the semiconductor device; The packaging structure further includes: 1) When the unit circuit is connected to a plurality of transfer electrodes, the insulating layer includes a working electrode window corresponding to the transfer electrode, wherein the working electrode is formed in the working electrode window by electroplating metal and is connected to the corresponding transfer electrode; 2) When the packaging structure includes an electrode plate, the working electrode is embedded in the electrode plate, the working electrode is connected to the unit circuit, the top surface of the working electrode is exposed on the top surface of the electrode plate, and the insulating layer covers the bottom surface of the electrode plate.
6. The packaging structure according to claim 5, characterized in that, The insulating layer is a solder resist ink layer.
7. The packaging structure according to claim 6, characterized in that, The electrode base plate or adapter electrode in the working electrode window is formed into a working electrode by copper plating and solderable metal plating.
8. The packaging structure according to claim 5, characterized in that, The packaging structure includes the electrode plate, which includes a substrate and a plurality of working electrodes embedded in holes in the substrate. The working electrodes include a top electrode and a bottom electrode. The top surface of the top electrode is exposed on the top surface of the substrate. The insulating layer covers the bottom surface of the substrate and the bottom electrode of the working electrode. The substrate includes chip transfer holes, and the semiconductor device is disposed in the chip transfer holes of the substrate. The encapsulating adhesive fills the chip transfer holes and covers the semiconductor device.
9. The packaging structure according to claim 5, characterized in that, The semiconductor device includes an LED chip or a diode, or a combination of an LED chip and an LED driver chip, wherein the LED chip includes a Mini-LED chip or a Micro-LED chip.