Impedance acquisition and active equalization circuit and energy storage equipment
By sharing the same impedance acquisition and active balancing circuit structure, active balancing and electrochemical impedance detection of the battery cells are achieved, solving the problems of complex battery structure and high cost in existing technologies, simplifying circuit design and improving battery safety and efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SVOLT ENERGY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-16
- Publication Date
- 2026-05-15
AI Technical Summary
Existing battery equalization circuits and electrochemical impedance detection are usually separate circuit structures, which leads to complex battery structures and increased design costs.
An impedance acquisition and active balancing circuit is provided, including a driving module, a rectification and impedance acquisition module, and an active balancing module. It achieves active balancing and impedance acquisition of the battery cell through a bus-isolated unidirectional fixed-point method, and uses the same circuit structure.
The circuit structure was simplified, the design cost was reduced, and the safety detection and active balancing of the cells were achieved, thus improving the safety and efficiency of the battery.
Smart Images
Figure CN224249384U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of battery management technology, specifically to an impedance acquisition and active balancing circuit and an energy storage device. Background Technology
[0002] Battery safety testing (such as cell electrochemical impedance spectroscopy) and battery balancing are both important factors affecting battery safety. However, existing battery balancing circuits and electrochemical impedance spectroscopy detection are usually separate circuit structures, making the overall battery structure very complex and increasing design costs. Utility Model Content
[0003] Embodiments of this application provide an impedance acquisition and active balancing circuit and an energy storage device to achieve impedance acquisition and active balancing of battery cells, simplifying the circuit structure and reducing costs.
[0004] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:
[0005] In a first aspect, an impedance acquisition and active balancing circuit is provided for use in an energy storage device, the energy storage device including a battery management system and multiple battery cells; the circuit includes: a drive module, multiple rectification and impedance acquisition modules and multiple active balancing modules;
[0006] The drive module is electrically connected to the battery management system and each of the rectification and impedance acquisition modules; each rectification and impedance acquisition module is electrically connected to an active balancing module, and each active balancing module is electrically connected to a battery cell.
[0007] In conjunction with the first aspect, the rectification and impedance acquisition module includes a first insulation and impedance acquisition unit, a second insulation and impedance acquisition unit, a third insulation and impedance acquisition unit, a fourth insulation and impedance acquisition unit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, and a transformer;
[0008] The first insulation and impedance acquisition unit is electrically connected to the drive module and the first switch unit, the first switch unit is electrically connected to the second insulation and impedance acquisition unit, and the second insulation and impedance acquisition unit is electrically connected to the drive module and the second switch unit, respectively; the second switch unit is electrically connected to the transformer.
[0009] The transformer is electrically connected to the third switching unit, the third switching unit is electrically connected to the third insulation and impedance acquisition unit, the third insulation and impedance acquisition unit is electrically connected to the drive module and the third switching unit respectively, the fourth switching unit is electrically connected to the fourth insulation and impedance acquisition unit, and the fourth insulation and impedance acquisition unit is electrically connected to the drive module.
[0010] The first insulation and impedance acquisition unit, the second insulation and impedance acquisition unit, the third insulation and impedance acquisition unit, the fourth insulation and impedance acquisition unit, the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit constitute a rectifier bridge.
[0011] In conjunction with the first aspect, the first insulation and impedance acquisition unit, the second insulation and impedance acquisition unit, the third insulation and impedance acquisition unit, and the fourth insulation and impedance acquisition unit are impedance acquisition switches ISO7741F-Q1.
[0012] In conjunction with the first aspect, the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit all include a first switch and a second switch connected in parallel; wherein the first switch and the second switch are respectively connected to the battery management system.
[0013] In conjunction with the first aspect, the first switch and the second switch are MOS switching transistors.
[0014] In conjunction with the first aspect, the first switch and the second switch are NPN type MOS switching transistors.
[0015] In conjunction with the first aspect, the active balancing module includes a third switch, a fourth switch, a fifth switch, a sixth switch, a first resistor, a second resistor, a third resistor, and an analog front-end acquisition unit; wherein, the third switch is integrated inside the analog front-end acquisition unit;
[0016] Wherein, the first end of the third switch is electrically connected to the battery management system, the second end of the third switch is electrically connected to the second end of the fifth switch and the positive electrode of the corresponding battery cell, and the third end of the third switch is electrically connected to the first end of the fourth switch, the second end of the sixth switch and the negative electrode of the corresponding battery cell.
[0017] The second terminal of the fourth switch is electrically connected to the first terminal of the first resistor and the first terminal of the fifth switch, respectively; the third terminal of the fourth switch is electrically connected to the first terminal of the second resistor and the second terminal of the sixth switch, respectively.
[0018] The third terminal of the fifth switch is electrically connected to the second terminal of the first resistor and the corresponding rectification and impedance acquisition module, respectively; the first terminal of the sixth switch is electrically connected to the second terminal of the second resistor and the first terminal of the third resistor, respectively; and the third terminal of the sixth switch is electrically connected to the second terminal of the third resistor and the corresponding rectification and impedance acquisition module, respectively.
[0019] In conjunction with the first aspect, the analog front-end acquisition unit is an AFE chip.
[0020] In conjunction with the first aspect, the driving module is an F280039C chip.
[0021] Secondly, an energy storage device is provided, including the impedance acquisition and active balancing circuit described above.
[0022] One of the above technical solutions has the following advantages or beneficial effects:
[0023] Compared with existing technologies, this application provides an impedance acquisition and active balancing circuit, comprising: a driving module, multiple rectification and impedance acquisition modules, and multiple active balancing modules; wherein the driving module is electrically connected to the battery management system and each rectification and impedance acquisition module; each rectification and impedance acquisition module is electrically connected to an active balancing module, and each active balancing module is electrically connected to a battery cell. The circuit provided by this application can achieve the acquisition and active balancing of the electrochemical impedance of the battery cell, thereby facilitating the safety detection and active balancing of the battery cell. Furthermore, by setting up a driving module, multiple rectification and impedance acquisition modules, and multiple active balancing modules, the same circuit can be used to simultaneously achieve active balancing and electrochemical impedance acquisition of each battery cell, thereby simplifying the circuit structure and reducing complexity and design costs. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the impedance acquisition and active equalization circuit provided in the embodiments of this application.
[0026] Figure 2 This is a schematic diagram of another impedance acquisition and active equalization circuit provided in the embodiments of this application.
[0027] Figure 3This is a schematic diagram of the principle structure of an impedance acquisition switch ISO7741F-Q1 provided in the embodiments of this application;
[0028] Figure 4 This is a pin diagram of an impedance acquisition switch ISO7741F-Q1 provided in an embodiment of this application;
[0029] Figure 5 This is a schematic diagram of an impedance acquisition and active equalization circuit provided in an embodiment of this application;
[0030] Figure 6 This is a schematic diagram of the working process of an impedance acquisition and active equalization circuit provided in the embodiments of this application;
[0031] Figure 7 This is a schematic diagram of the circuit structure of an energy storage device provided in the embodiments of this application. Detailed Implementation
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0033] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified.
[0034] Figure 1 This is a block diagram illustrating the principle structure of an impedance acquisition and active equalization circuit provided in an embodiment of this application. Please refer to... Figure 1The impedance acquisition and active balancing circuit is applied to an energy storage device, which includes a battery management system and multiple battery cells. The impedance acquisition and active balancing circuit includes a drive module 100, multiple rectification and impedance acquisition modules, and multiple active balancing modules. The drive module 100 is electrically connected to the battery management system and each rectification and impedance acquisition module. Each rectification and impedance acquisition module is electrically connected to an active balancing module, and each active balancing module is electrically connected to a battery cell.
[0035] The impedance acquisition and active balancing circuit uses a bus-isolated unidirectional fixed-point active balancing method, and is equipped with a drive module 100, multiple rectification and impedance acquisition modules and multiple active balancing modules to achieve active balancing of each cell.
[0036] The energy storage device includes a battery management system (BMS) and multiple battery cells. These cells are connected in series. For example, see [link to example]. Figure 1 The energy storage device includes a first cell 10, a second cell 20, ..., an Nth cell 30. The first cell 10, the second cell 20, ..., the Nth cell 30 are connected in series.
[0037] The impedance acquisition and active equalization circuit includes multiple rectification and impedance acquisition modules and multiple active equalization modules. For example, see [link to example]. Figure 1 The impedance acquisition and active equalization circuit includes a first rectification and impedance acquisition module 210, a second rectification and impedance acquisition module 220, ..., an Nth rectification and impedance acquisition module 230, and a first active equalization module 310, a second active equalization module 320, ..., an Nth active equalization module 330. The BMS is electrically connected to the drive module 100, and the drive module 100 is electrically connected to the first rectification and impedance acquisition module 210, the second rectification and impedance acquisition module 220, ..., the Nth rectification and impedance acquisition module 230. The first rectification and impedance acquisition module 210 is electrically connected to the first active equalization module 310, the second rectification and impedance acquisition module 220 is electrically connected to the second active equalization module 320, ..., the Nth rectification and impedance acquisition module 230 is electrically connected to the Nth active equalization module 330. The first active balancing module 310 is electrically connected to the first battery cell 10, the second active balancing module 320 is electrically connected to the second battery cell 20, ..., the Nth active balancing module 330 is electrically connected to the Nth battery cell 30.
[0038] The energy required for the impedance acquisition and active balancing circuit is provided by the high voltage of the PACK composed of individual cells connected in series.
[0039] In some embodiments, the driver module is an F280039C chip.
[0040] Each rectification and impedance acquisition module rectifies the voltage required for active charging of its corresponding battery cell, providing the active charging voltage for that cell. Simultaneously, it detects the electrochemical impedance of the corresponding battery cell for subsequent safety testing. The drive module 100 drives each rectification and impedance acquisition module to perform impedance acquisition and rectification. For example, assuming the BMS detects that the first battery cell 10 needs active charging, the BMS provides the required charging voltage for active charging of the first battery cell 10 through the PACK high voltage. The BMS controls the drive module 100 to activate the first rectification and impedance acquisition module 210 corresponding to the first battery cell 10, so that the charging voltage required for active charging of the first battery cell 10 is rectified by the first rectification and impedance acquisition module 210 and output to the corresponding first active balancing module 310 to provide the active charging voltage for the first battery cell 10, achieving active balancing of the first battery cell 10. Simultaneously, the first rectification and impedance acquisition module 210 acquires the electrochemical impedance of the first battery cell 10 for subsequent safety testing of the battery cell based on its electrochemical impedance. Therefore, this circuit can simultaneously achieve electrochemical impedance detection and active balancing of the first cell. Similarly, the active balancing and electrochemical impedance detection principles for the other cells are the same as those for the first cell, and will not be repeated here.
[0041] One way the BMS determines whether active balancing of individual cells is needed is by collecting information such as voltage, current, and SOC of each cell and judging whether active balancing is required based on this information. The specific judgment method is existing technology and will not be elaborated here.
[0042] For example, each active balancing module can integrate an analog front-end (AFE) chip to collect information such as voltage, current, temperature, and SOC of each corresponding cell, and send it to the BMS via daisy-chain serial communication. Specifically, the AFE chip can be an MC33771 chip.
[0043] Figure 2 This is a block diagram illustrating the principle structure of another impedance acquisition and active equalization circuit provided in this application embodiment. Please refer to... Figure 2The rectification and impedance acquisition module includes a first insulation and impedance acquisition unit 211, a second insulation and impedance acquisition unit 212, a third insulation and impedance acquisition unit 213, a fourth insulation and impedance acquisition unit 214, a first switching unit 215, a second switching unit 216, a third switching unit 217, a fourth switching unit 218, and a transformer 219. The first insulation and impedance acquisition unit 211 is electrically connected to the drive module 100 and the first switching unit 215, respectively. The first switching unit 215 is electrically connected to the second insulation and impedance acquisition unit 212, and the second insulation and impedance acquisition unit 212 is electrically connected to the drive module 100 and the second switching unit 216, respectively. The second switching unit 216 is electrically connected to the transformer 219. The transformer 219 is electrically connected to the third switching unit 217, the third switching unit 217 is electrically connected to the third insulation and impedance acquisition unit 213, the third insulation and impedance acquisition unit 213 is electrically connected to the drive module 100 and the third switching unit 217 respectively, the fourth switching unit 218 is electrically connected to the fourth insulation and impedance acquisition unit 214, and the fourth insulation and impedance acquisition unit 214 is electrically connected to the drive module 100; wherein, the first insulation and impedance acquisition unit 211, the second insulation and impedance acquisition unit 212, the third insulation and impedance acquisition unit 213, the fourth insulation and impedance acquisition unit 214, the first switching unit 215, the second switching unit 216, the third switching unit 217 and the fourth switching unit 218 form a rectifier bridge.
[0044] The first switch unit 215, the second switch unit 216, the third switch unit 217 and the fourth switch unit 218 are also electrically connected to the BMS.
[0045] See Figure 2The first insulation and impedance acquisition unit 211, the second insulation and impedance acquisition unit 212, the third insulation and impedance acquisition unit 213, the fourth insulation and impedance acquisition unit 214, the first switching unit 215, the second switching unit 216, the third switching unit 217, and the fourth switching unit 218 form a rectifier bridge. On one hand, this bridge rectifies the active charging voltage required by the corresponding battery cell provided by the PACK high voltage and outputs it to the active balancing module corresponding to the battery cell, thus providing the active charging voltage and achieving cell balancing. On the other hand, the high-precision PWM signal from the MCU controls each insulation and impedance acquisition unit (i.e., the first insulation and impedance acquisition unit 211, the second insulation and impedance acquisition unit 212, the third insulation and impedance acquisition unit 213, and the fourth insulation and impedance acquisition unit 214). This process generates a disturbance signal of a certain frequency on the cell under test. During this process, the battery voltage and current response are measured, and finally, the impedance spectrum curve preset in the MCU is used (where the electrochemical impedance spectroscopy (EIS) curve is obtained by applying a small amplitude AC potential or current disturbance and measuring the battery's impedance response at different frequencies, which can reflect the dynamic characteristics of the internal electrochemical process of the battery. In the EIS curve, the semi-circular arc in the high-frequency range mainly reflects the combination of the battery's internal resistance and charge transfer impedance. In this application, the preset impedance spectrum curve is measured in advance by an electrochemical workstation, fitted by an algorithm, and stored in flash as a preset lookup table value). The accurate internal resistance of the battery at this time is obtained, thereby achieving cell balancing while acquiring the corresponding cell's electrochemical impedance to enable safe cell testing. This allows the acquisition and active balancing of the electrochemical impedance of each cell to be achieved through the same circuit structure, without the need for separate circuit design and layout. This simplifies the circuit structure, reduces the number of components used, optimizes the layout, reduces power consumption, reduces the complexity of energy storage devices, and reduces design costs.
[0046] Among them, the first insulation and impedance acquisition unit 211, the second insulation and impedance acquisition unit 212, the third insulation and impedance acquisition unit 213 and the fourth insulation and impedance acquisition unit 214 are impedance acquisition switches ISO7741F-Q1.
[0047] Figure 3 This is a schematic diagram illustrating the principle structure of an impedance acquisition switch ISO7741F-Q1 provided in an embodiment of this application. For an example, please refer to [link to example]. Figure 3 The impedance acquisition switch ISO7741F-Q1 includes a transmitter, an isolation unit, and a receiver. The transmitter includes a signal modulation unit 101, a transmit signal conditioning unit 102, an oscillator 103, and an emission reduction technology unit 104. The isolation unit employs a silicon dioxide-based capacitor isolation unit. The receiver includes a receive signal conditioning unit 201 and an envelope detection unit 202.
[0048] Figure 4 This is a pinout diagram of an impedance acquisition switch ISO7741F-Q1 provided in an embodiment of this application. For an example, please refer to [link to example]. Figure 4 The impedance acquisition switch ISO7741F-Q1 includes 16 pins. The eight input pins are as follows: Pin 1, Input Power (VCC1), connected to the input power supply voltage (typically positive); Pin 2, Input Ground (GND1), connected to the input ground (GND); Pin 3, Input Signal (INA), receiving input signals from external circuitry; Pin 4, Input Signal (INB), receiving input signals from external circuitry; Pin 5, Input Signal (INC), receiving input signals from external circuitry; Pin 6, Input Power (OUTD), connected to the input power supply voltage; Pin 7, Output Drive Voltage (EN1), used to control the output drive voltage; and Pin 8, Input Ground (GND1), connected to the input ground (GND).
[0049] The eight output pins are as follows: Pin 16, Output Power Pin VCC2, connected to the output power supply voltage (usually positive); Pin 15, Output Ground Pin GND2, connected to the output ground (GND); Pin 14, Output Signal Pin OUTA, outputs the converted signal; Pin 13, Output Signal Pin OUTB, outputs the converted signal; Pin 12, Output Signal Pin OUTC, outputs the converted signal; Pin 11, Output Power Pin IND, connected to the output power supply voltage; Pin 10, Output Drive Voltage Pin EN2, used to control the output drive voltage; Pin 9, Output Ground Pin GND2, connected to the output ground (GND).
[0050] Figure 5 This is a schematic diagram of an impedance acquisition and active equalization circuit provided in an embodiment of this application. Please refer to... Figure 5 The first switch unit 215, the second switch unit 216, the third switch unit 217 and the fourth switch unit 218 each include a first switch K1 and a second switch K2 connected in parallel; wherein the first switch K1 and the second switch K2 are respectively connected to the battery management system BMS.
[0051] For example, see Figure 5 The first insulation and impedance acquisition unit 211, the second insulation and impedance acquisition unit 212, the third insulation and impedance acquisition unit 213 and the fourth insulation and impedance acquisition unit 214 all adopt the impedance acquisition switch ISO7741F-Q1.
[0052] For example, the first switching unit 215 includes a first switch K1 and a second switch K2. Similarly, the second switching unit 216, the third switching unit 217, and the fourth switching unit 218 also include a first switch K1 and a second switch K2.
[0053] Among them, the first switch K1 and the second switch K2 are MOS switches.
[0054] Among them, the first switch K1 and the second switch K2 are NPN type MOS switches.
[0055] In some embodiments, please refer to Figure 5 The active balancing module includes a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a first resistor R1, a second resistor R2, a third resistor R3, and an analog front-end acquisition unit (AFE). The third switch K3 is integrated within the analog front-end acquisition unit AFE. The first terminal of the third switch K3 is electrically connected to the battery management system (BMS), and the second terminal of the third switch K3 is connected to the second terminal of the fifth switch K5 and the corresponding battery cell (assuming it is a battery cell). Figure 5 The positive terminal of the first battery cell is electrically connected, and the third terminal of the third switch K3 is connected to the first terminal of the fourth switch K4, the second terminal of the sixth switch K6, and the corresponding battery cell (assuming it is a battery cell). Figure 5 The negative terminal of the first battery cell is electrically connected; the second terminal of the fourth switch K4 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the fifth switch K5, respectively; the third terminal of the fourth switch K4 is electrically connected to the first terminal of the second resistor R2 and the second terminal of the sixth switch K6, respectively; the third terminal of the fifth switch K5 is electrically connected to the second terminal of the first resistor R1 and the corresponding rectification and impedance acquisition module (assuming it is...). Figure 5 The first rectifier and impedance acquisition module (i.e., the first rectifier bridge) is electrically connected; the first terminal of the sixth switch K6 is electrically connected to the second terminal of the second resistor R2 and the first terminal of the third resistor R3, respectively; the third terminal of the sixth switch K6 is electrically connected to the second terminal of the third resistor R3 and the corresponding rectifier and impedance acquisition module (assuming it is...). Figure 5 The first rectifier and impedance acquisition module (i.e., the first rectifier bridge) is electrically connected.
[0056] In this design, the first resistor R1 is the upper bias resistor, and the third resistor R3 is the lower bias resistor. The resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 can be set according to the actual situation, and no specific limitation is made here.
[0057] In this configuration, the third switch K3 can be a MOSFET. The fourth switch K4, the fifth switch K5, and the sixth switch K6 can be transistors. Furthermore, the third switch K3 can be an NPN MOSFET. The fourth switch K4 is an NPN transistor, the fifth switch K5 is a PNP transistor, and the sixth switch K6 is an NPN transistor.
[0058] In addition, see Figure 5 The active balancing module also includes a fourth resistor R4, a fifth resistor R5, and a first diode D1. The first terminal of the fourth resistor R4 is connected to the corresponding battery cell (assuming it is...). Figure 5 The positive terminal of the first battery cell is electrically connected, the second terminal of the fourth resistor R4 is electrically connected to the second terminal of the third switch K3, and the first terminal of the fifth resistor R5 is electrically connected to the corresponding battery cell (assuming it is a battery cell). Figure 5 The negative terminal of the first battery cell is electrically connected, the second terminal of the fifth resistor R5 is electrically connected to the first terminal of the fourth switch K4, the anode of the first diode D1 is electrically connected to the third terminal of the fourth switch K4 and the first terminal of the second resistor R2, and the cathode of the first diode D1 is electrically connected to the second terminal of the sixth switch K6. The first diode D1 is used for reverse polarity protection.
[0059] The analog front-end acquisition unit is an AFE chip.
[0060] The AFE chip can be the MC33771 chip.
[0061] In the technical solution of this embodiment, the implementation process of the impedance acquisition and active equalization circuit is as follows: (See...) Figure 5When the BMS determines that an active balancing command is needed, the MCU sends an instruction to the driver chip F280039C via SPI / PWM. The F280039C drives the impedance acquisition switch ISO7741F-Q1, turning on the MOS circuit to achieve balancing via the active balancing module. For example, assuming the BMS detects that the first cell needs active balancing, the BMS provides the necessary charging voltage for active balancing to the first cell through the PACK high voltage and controls the F280039C chip to drive each impedance acquisition switch ISO7741F-Q1 in the first rectifier bridge, turning on the corresponding first switch K1 and second switch K2. This rectifies the charging voltage and outputs it to the first active balancing module. Simultaneously, the impedance acquisition switch ISO7741F-Q1 acquires the electrochemical impedance of the first cell. Furthermore, the BMS controls the third switch K3 in the first active balancing module to turn on. At this point, with the third switch K3 conducting, the rectified charging voltage is output to DC+ via the first rectifier bridge. The power from DC+ then flows sequentially through the first resistor R1, the fourth switch K4, the second resistor R2, and the third resistor R3 to DC-, forming a current path. This opens the fifth switch K5 and the sixth switch K6, allowing the active charging voltage to charge the first cell, achieving active balancing of the first cell. Since the AFE's sampling circuit continuously samples during charging, the AFE sends the battery voltage to the BMS via a daisy chain. The BMS determines whether the required charging voltage has been reached. When the BMS determines that charging is complete, it closes the third switch K3, thereby closing the fifth switch K5 and the sixth switch K6 to stop charging the first cell. This achieves active balancing of each cell and the acquisition of electrochemical impedance.
[0062] Figure 6 This is a schematic diagram illustrating the workflow of an impedance acquisition and active equalization circuit provided in an embodiment of this application. For an example, please refer to [link to example]. Figure 6First, a SOC difference threshold needs to be set. Then, the BMS monitors the temperature and voltage status of each cell in real time and calculates the SOC value of each cell. Next, the BMS determines whether the average SOC difference between any cell and the PACK exceeds the set difference threshold. If it does not exceed the set difference threshold, it is considered that equalization does not need to be activated, and real-time thermal runaway detection is performed. If thermal runaway is detected, a thermal runaway warning is activated; otherwise, other calculations are performed. If the SOC difference threshold is exceeded, the cells that need equalization are marked, and equalization calculations are performed on them. Then, the BMS determines whether equalization can be activated under the current operating conditions. After determining that equalization can be activated, the system starts collecting electrochemical impedance data from all cells (while the hardware has already implemented equalization for cells with abnormal SOC values), and the hardware uses sinusoidal current equalization in frequency sweep mode. Then, the equalization charge is calculated in real time (sinusoidal current integration method in frequency sweep mode). It is then determined whether equalization has ended. If equalization has ended, the cell electrochemical impedance data collection is stopped; otherwise, equalization continues. Finally, the electrochemical impedance of the scanned cells is recorded and updated, and cells not yet scanned continue to be scanned in the next round of equalization. Therefore, the circuit provided in this application, by actively equalizing while simultaneously acquiring equivalent electrochemical impedance, can monitor the battery's internal resistance parameters in real time, providing early warnings of abnormal cells, thermal runaway, and manufacturing defects. This is more accurate than big data (which requires network connectivity and provides second-level warnings) (this application can achieve offline millisecond-level warnings). Currently, big data cannot provide early warnings for dead cells, while this application can provide early warnings, improving the accuracy of the SOX algorithm, thereby fully utilizing battery performance and increasing battery life. Furthermore, this application uses the PACK high voltage as a power source, and after rectification by the rectifier bridge, it replenishes the individual cells that need equalization, greatly improving the equalization rate and efficiency. Compared to equalization methods using resistor discharge, it improves battery utilization and indirectly increases driving range. Furthermore, this application combines electrochemical impedance acquisition with active equalization circuitry, which not only enables independent control of equalization, freeing it from the limitations of AFE chip and improving equalization capability, but also achieves low cost, low power consumption and high efficiency as the circuit is mostly composed of MOS and transistors.
[0063] Figure 7 This is a schematic diagram of the circuit structure of an energy storage device provided in an embodiment of this application. Accordingly, this application also provides an energy storage device, including the impedance acquisition and active balancing circuit provided in any embodiment of this application.
[0064] Among them, energy storage devices can be new energy vehicle battery packs, etc., and the specific configuration can be set according to the actual situation. No specific restrictions are made here.
[0065] For example, taking a new energy vehicle battery pack as an example, see [link / reference]. Figure 7The new energy vehicle battery pack includes: a BMS main board, a BMS slave board, a high-voltage contactor, interconnected battery cells, an MCU, a driver chip F280039C, and an SBC power IC. Each battery cell is equipped with a corresponding AFE chip, an active balancing module, and a rectifier bridge. The rectifier bridge consists of a transformer, an impedance acquisition switch ISO7741F-Q1, and a MOS circuit (for detailed rectifier bridge structure, please refer to...). Figure 5 Therefore, this new energy vehicle battery pack can achieve active balancing of each cell, and at the same time, it can collect the electrochemical impedance of the cells, thereby simplifying the structure, reducing the number of components, reducing complexity, power consumption and cost.
[0066] The data processing method and apparatus for battery degradation provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. An impedance acquisition and active equalization circuit, characterized in that, The circuit is applied to an energy storage device, which includes a battery management system and multiple battery cells; the circuit includes: a drive module, multiple rectification and impedance acquisition modules, and multiple active balancing modules. The drive module is electrically connected to the battery management system and each of the rectification and impedance acquisition modules; each rectification and impedance acquisition module is electrically connected to an active balancing module, and each active balancing module is electrically connected to a battery cell.
2. The impedance acquisition and active equalization circuit according to claim 1, characterized in that, The rectification and impedance acquisition module includes a first insulation and impedance acquisition unit, a second insulation and impedance acquisition unit, a third insulation and impedance acquisition unit, a fourth insulation and impedance acquisition unit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, and a transformer; The first insulation and impedance acquisition unit is electrically connected to the drive module and the first switch unit, the first switch unit is electrically connected to the second insulation and impedance acquisition unit, and the second insulation and impedance acquisition unit is electrically connected to the drive module and the second switch unit, respectively; the second switch unit is electrically connected to the transformer. The transformer is electrically connected to the third switching unit, the third switching unit is electrically connected to the third insulation and impedance acquisition unit, the third insulation and impedance acquisition unit is electrically connected to the drive module and the third switching unit respectively, the fourth switching unit is electrically connected to the fourth insulation and impedance acquisition unit, and the fourth insulation and impedance acquisition unit is electrically connected to the drive module. The first insulation and impedance acquisition unit, the second insulation and impedance acquisition unit, the third insulation and impedance acquisition unit, the fourth insulation and impedance acquisition unit, the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit constitute a rectifier bridge.
3. The impedance acquisition and active equalization circuit according to claim 2, characterized in that, The first insulation and impedance acquisition unit, the second insulation and impedance acquisition unit, the third insulation and impedance acquisition unit, and the fourth insulation and impedance acquisition unit are impedance acquisition switches ISO7741F-Q1.
4. The impedance acquisition and active equalization circuit according to claim 2, characterized in that, The first switch unit, the second switch unit, the third switch unit, and the fourth switch unit each include a first switch and a second switch connected in parallel; wherein the first switch and the second switch are respectively connected to the battery management system.
5. The impedance acquisition and active equalization circuit according to claim 4, characterized in that, The first switch and the second switch are MOS switches.
6. The impedance acquisition and active equalization circuit according to claim 5, characterized in that, The first switch and the second switch are NPN type MOS switches.
7. The impedance acquisition and active equalization circuit according to claim 1, characterized in that, The active balancing module includes a third switch, a fourth switch, a fifth switch, a sixth switch, a first resistor, a second resistor, a third resistor, and an analog front-end acquisition unit; wherein the third switch is integrated inside the analog front-end acquisition unit; Wherein, the first end of the third switch is electrically connected to the battery management system, the second end of the third switch is electrically connected to the second end of the fifth switch and the positive electrode of the corresponding battery cell, and the third end of the third switch is electrically connected to the first end of the fourth switch, the second end of the sixth switch and the negative electrode of the corresponding battery cell. The second terminal of the fourth switch is electrically connected to the first terminal of the first resistor and the first terminal of the fifth switch, respectively; the third terminal of the fourth switch is electrically connected to the first terminal of the second resistor and the second terminal of the sixth switch, respectively. The third terminal of the fifth switch is electrically connected to the second terminal of the first resistor and the corresponding rectification and impedance acquisition module, respectively; the first terminal of the sixth switch is electrically connected to the second terminal of the second resistor and the first terminal of the third resistor, respectively; and the third terminal of the sixth switch is electrically connected to the second terminal of the third resistor and the corresponding rectification and impedance acquisition module, respectively.
8. The impedance acquisition and active equalization circuit according to claim 7, characterized in that, The analog front-end acquisition unit is an AFE chip.
9. The impedance acquisition and active equalization circuit according to claim 1, characterized in that, The driver module is an F280039C chip.
10. An energy storage device, characterized in that, Includes the impedance acquisition and active equalization circuit as described in any one of claims 1-9.