Pre-discharge circuit for intelligently activating BMS (Battery Management System) and battery
By intelligently activating the pre-discharge circuit of the BMS, monitoring the current, and activating the circuit to conduct when the preset value is reached, the BMS can quickly switch from dormant state to active state, solving the problem of slow switching speed between pre-discharge and main discharge, and improving the safety of lithium batteries.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- EVE ENERGY CO LTD
- Filing Date
- 2025-03-26
- Publication Date
- 2026-05-19
AI Technical Summary
Existing BMS systems are slow to switch between pre-discharge and main discharge states and are prone to damage, resulting in insufficient safety of lithium batteries.
A pre-discharge circuit for intelligent activation of BMS was designed. The target chip monitors the current of the pre-discharge circuit. When the current reaches a preset value, the activation circuit is turned on, realizing the transition of BMS from dormant state to active state and turning on the main discharge circuit to achieve rapid switching.
The switching rate between the preamplifier circuit and the main amplifier circuit is accelerated, the possibility of damage from excessive current is reduced, and the safety of lithium batteries is improved.
Smart Images
Figure CN224264695U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of battery technology, and in particular to a pre-discharge circuit and battery for intelligent activation BMS. Background Technology
[0002] With the implementation of new national standards and the popularization of green travel concepts, the demand for lithium batteries for electric vehicles continues to rise. For safety reasons, most electric vehicle batteries now require a pre-discharge function; however, the switching between pre-discharge and main discharge states has become a pressing problem to be solved.
[0003] Currently, most battery management systems (BMS) on the market rely on external activation circuits for activation, which is a relatively simple method and makes it difficult to achieve rapid switching between the pre-discharge circuit and the main discharge circuit. On the one hand, the pre-discharge circuit has weak overcurrent capacity and is easily damaged if the current is too high; on the other hand, the switching to the main discharge circuit takes a long time, increasing the risk of circuit damage and thus increasing the possibility of lithium battery explosion and fire. Therefore, it is particularly important to propose a technical solution that enables the BMS to achieve intelligent switching in low-power sleep mode, while accelerating the switching rate between the pre-discharge circuit and the main discharge circuit, thereby improving the safety of lithium batteries. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide a pre-amplifier circuit and battery for intelligent activation of BMS, which enables BMS to achieve intelligent switching in low-power sleep mode, while accelerating the switching rate between the pre-amplifier circuit and the main amplifier circuit, thereby improving the safety of lithium battery.
[0005] To address the aforementioned technical problems, the first aspect of this utility model discloses a pre-discharge circuit for intelligent activation BMS, characterized in that the circuit includes a target chip, an activation circuit, a pre-discharge circuit, and a main discharge circuit, wherein:
[0006] The first terminal of the target chip is electrically connected to the first terminal of the activation circuit, the second terminal of the target chip is electrically connected to the first terminal of the pre-discharge circuit, the third terminal of the target chip is electrically connected to the first terminal of the main discharge circuit, the second terminal of the pre-discharge circuit and the second terminal of the main discharge circuit are respectively electrically connected to the second terminal of the activation circuit, and the third terminal of the pre-discharge circuit is electrically connected to the third terminal of the main discharge circuit.
[0007] When the current flowing through the pre-discharge circuit reaches a preset current value, the activation circuit is used to activate the target chip so that the BMS changes from a dormant state to an active state and turns on the main discharge circuit.
[0008] As an optional implementation, in the first aspect of this utility model, the pre-discharge circuit includes a first NMOS transistor, a first resistor, a second resistor, and the target chip, wherein:
[0009] The gate of the first NMOS transistor is electrically connected to the second terminal of the target chip, the source of the first NMOS transistor is electrically connected to the third terminal of the main discharge circuit, the drain of the first NMOS transistor is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively, and the second terminal of the first resistor, the second terminal of the second resistor and the second terminal of the main discharge circuit are electrically connected to the second terminal of the activation circuit.
[0010] The first resistor and the second resistor are used to adjust the preset current value.
[0011] As an optional implementation, in the first aspect of this utility model, the activation circuit includes a first transistor, a second transistor, a first diode, a second diode, and the target chip, wherein:
[0012] The collector of the first transistor is electrically connected to the anode of the first diode, the cathode of the first diode is electrically connected to the first terminal of the target chip, the base of the first transistor is electrically connected to the collector of the second transistor, the base of the second transistor is electrically connected to the cathode of the second diode, and the anode of the second diode is electrically connected to the second terminal of the pre-discharge circuit and the second terminal of the main discharge circuit, respectively.
[0013] As an optional implementation, in the first aspect of this utility model, the main discharge circuit includes a second NMOS transistor, a third NMOS transistor, and the target chip, wherein:
[0014] The gates of the second NMOS transistor and the third NMOS transistor are electrically connected to the third terminal of the target chip, respectively. The drains of the second NMOS transistor, the drains of the third NMOS transistor, and the second terminal of the pre-discharge circuit are electrically connected to the second terminal of the activation circuit, respectively.
[0015] As an optional implementation, in the first aspect of this utility model, the circuit further includes a power supply circuit, wherein:
[0016] The first terminal of the power supply circuit is electrically connected to the emitter of the first transistor;
[0017] The power supply circuit is used to provide an activation voltage to the target chip when the activation circuit is used to activate the target chip.
[0018] As an optional implementation, in the first aspect of this utility model, the power supply circuit includes a third diode, a third transistor, a fourth transistor, and a Zener diode, wherein:
[0019] The negative terminal of the third diode is electrically connected to the collector of the third transistor and the collector of the fourth transistor, respectively. The base of the third transistor is electrically connected to the negative terminal of the Zener diode. The positive terminal of the Zener diode is used for grounding. The emitter of the third transistor is electrically connected to the base of the fourth transistor. The emitter of the fourth transistor is electrically connected to the emitter of the first transistor.
[0020] As an optional implementation, in the first aspect of this utility model, the circuit further includes a current limiting circuit, which includes a third resistor and a fourth resistor, wherein:
[0021] The first end of the third resistor and the first end of the fourth resistor are respectively used to be electrically connected to the negative terminal of the battery cell, and the second end of the third resistor and the second end of the fourth resistor are respectively electrically connected to the fourth terminal of the target chip, the third terminal of the pre-discharge circuit and the source of the second NMOS transistor.
[0022] Furthermore, the source of the third NMOS transistor is used to electrically connect to the negative terminal of the load, and the anode of the third diode is used to electrically connect to the positive terminal of the battery cell and the positive terminal of the load, respectively.
[0023] As an optional implementation, in the first aspect of this invention, the target chip includes target pins, wherein:
[0024] The emitter of the second transistor is electrically connected to the target pin;
[0025] Specifically, when the activation circuit is used to activate the target chip to change the BMS from a dormant state to an active state, the target pin of the target chip is detected, and when the activation voltage is detected on the target pin, the main discharge circuit is turned on.
[0026] As an optional implementation, in the first aspect of this utility model, the target chip includes the model number OZ7710.
[0027] The second aspect of this utility model discloses a battery, the battery including a pre-discharge circuit for intelligent activation BMS as disclosed in the first aspect of this utility model.
[0028] Implementing this utility model has the following beneficial effects:
[0029] This invention enables intelligent switching of the BMS in low-power sleep mode, while simultaneously accelerating the switching rate between the pre-discharge circuit and the main discharge circuit, thus improving lithium battery safety. Specifically, this invention, while the BMS is in sleep mode, monitors the current flowing through the pre-discharge circuit. When the current reaches a preset value, the voltage drop across the pre-discharge circuit activates the activation circuit, which then activates the target chip, transitioning the BMS from sleep to active state. Once activated, the main discharge circuit is activated, enabling intelligent activation of the BMS in low-power sleep mode and intelligent switching between the pre-discharge and main discharge circuits. This accelerates the switching rate between the pre-discharge and main discharge circuits, reduces the possibility of damage from excessive current in the pre-discharge circuit, lowers the risk of lithium battery explosion and fire, and improves lithium battery safety. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the preamplifier circuit for intelligent activation of BMS disclosed in an embodiment of this utility model;
[0032] Figure 2 This is a schematic diagram of another preamplifier circuit for intelligent activation of BMS disclosed in this utility model embodiment;
[0033] Figure 3 This is a schematic diagram of the preamplifier circuit for another intelligent activation BMS disclosed in this utility model embodiment;
[0034] Figure 4 This is a schematic diagram of the structure of a battery disclosed in an embodiment of this utility model. Detailed Implementation
[0035] To better understand and implement this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0036] It should be noted that, unless otherwise expressly specified and limited, the term "electrical connection" in the specification, claims, and accompanying drawings of this utility model should be interpreted broadly. For example, it can be a fixed electrical connection, a detachable electrical connection, or an integral electrical connection; it can be a mechanical electrical connection, an electrical-electrical connection, or a connection that allows for communication; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two elements or an interaction between two elements. Furthermore, the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0037] This utility model discloses a pre-discharge circuit and battery for intelligently activating a BMS, which enables intelligent activation of the BMS in a low-power sleep state and intelligent switching between the pre-discharge circuit and the main discharge circuit. This accelerates the switching rate between the pre-discharge circuit and the main discharge circuit, reduces the possibility of damage from excessive current in the pre-discharge circuit, lowers the likelihood of lithium battery explosion and fire, and improves lithium battery safety. Detailed descriptions follow.
[0038] Example 1
[0039] Please see Figure 1 , Figure 1 This is a schematic diagram of the preamplifier circuit for an intelligent activated BMS disclosed in an embodiment of this utility model. Wherein, Figure 1 The pre-amplifier circuit of the intelligent activation BMS shown can be applied to battery cells, but this embodiment of the invention is not limited thereto. Figure 1 As shown, the pre-discharge circuit of the intelligent activation BMS may include a target chip U1, an activation circuit 101, a pre-discharge circuit 102, and a main discharge circuit 103, wherein:
[0040] The first terminal of the target chip U1 is electrically connected to the first terminal of the activation circuit 101, the second terminal of the target chip U1 is electrically connected to the first terminal of the pre-discharge circuit 102, the third terminal of the target chip U1 is electrically connected to the first terminal of the main discharge circuit 103, the second terminals of the pre-discharge circuit 102 and the second terminals of the main discharge circuit 103 are respectively electrically connected to the second terminal of the activation circuit 101, and the third terminal of the pre-discharge circuit 102 is electrically connected to the third terminal of the main discharge circuit 103.
[0041] When the current flowing through the pre-discharge circuit 102 reaches a preset current value, the activation circuit 101 is used to activate the target chip U1 so that the BMS changes from a dormant state to an active state and turns on the main discharge circuit 103.
[0042] Optionally, the target chip may include an analog front-end chip. Specifically, the target chip model may include OZ7710. When the BMS is in sleep mode, the current value flowing through the pre-discharge circuit is monitored. When the current flowing through the pre-discharge circuit reaches a preset current value, the voltage drop generated on the pre-discharge circuit will cause the activation circuit to conduct. In turn, the activation circuit is used to activate the target chip, thereby causing the BMS to change from sleep mode to activation mode. After the BMS enters the activation mode, the main discharge circuit is turned on, realizing the intelligent activation of the BMS in low-power sleep mode and the intelligent switching between the pre-discharge circuit and the main discharge circuit. This utility model embodiment is not limited.
[0043] It is evident that implementation Figure 1 The described intelligent BMS activation pre-discharge circuit can monitor the current flowing through the pre-discharge circuit while the BMS is in sleep mode. When the current flowing through the pre-discharge circuit reaches a preset current value, the voltage drop generated on the pre-discharge circuit will cause the activation circuit to conduct. The activation circuit then activates the target chip, thereby causing the BMS to switch from sleep mode to active mode. After the BMS enters the active mode, the main discharge circuit is turned on, realizing intelligent activation of the BMS in low-power sleep mode and intelligent switching between the pre-discharge circuit and the main discharge circuit. This can accelerate the switching rate between the pre-discharge circuit and the main discharge circuit, reduce the possibility of damage from excessive current in the pre-discharge circuit, reduce the possibility of lithium battery explosion and fire, and improve lithium battery safety.
[0044] In an optional embodiment, such as Figure 2 As shown, Figure 2 This is a schematic diagram of another pre-discharge circuit for intelligent activation of the BMS disclosed in this utility model embodiment. The pre-discharge circuit 102 includes a first NMOS transistor M1, a first resistor R1, a second resistor R2, and a target chip U1, wherein:
[0045] The gate of the first NMOS transistor M1 is electrically connected to the second terminal of the target chip U1, the source of the first NMOS transistor M1 is electrically connected to the third terminal of the main discharge circuit 103, the drain of the first NMOS transistor M1 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R1, and the second terminal of the first resistor R1, the second terminal of the second resistor R2 and the second terminal of the main discharge circuit 103 are electrically connected to the second terminal of the activation circuit 101.
[0046] Among them, the first resistor R1 and the second resistor R2 are used to adjust the preset current value.
[0047] Optionally, when the BMS is in a dormant state, there is always a current flowing through the pre-discharge circuit. When the current flowing through the pre-discharge circuit reaches a preset current value, the voltage drop generated on the pre-discharge circuit will cause the activation circuit to conduct. The preset current value can be changed by adjusting the resistance values of the first resistor and the second resistor. This embodiment of the present invention is not limited.
[0048] As can be seen, this optional embodiment can intelligently control the activation of the BMS and the intelligent switching between the pre-discharge circuit and the main discharge circuit by monitoring the current value flowing through the pre-discharge circuit when the BMS is in a dormant state. Furthermore, it can change the preset current value by adjusting the resistance values of the first resistor and the second resistor, thereby accelerating the switching rate between the pre-discharge circuit and the main discharge circuit, reducing the possibility of damage from excessive current in the pre-discharge circuit, reducing the possibility of lithium battery explosion and fire, and improving lithium battery safety.
[0049] In another alternative embodiment, such as Figure 2 As shown, the activation circuit 101 includes a first transistor Q1, a second transistor Q2, a first diode D1, a second diode D2, and a target chip U1, wherein:
[0050] The collector of the first transistor Q1 is electrically connected to the positive terminal of the first diode D1, the negative terminal of the first diode D1 is electrically connected to the first terminal of the target chip U1, the base of the first transistor Q1 is electrically connected to the collector of the second transistor Q2, the base of the second transistor Q2 is electrically connected to the negative terminal of the second diode D2, and the positive terminal of the second diode D2 is electrically connected to the second terminal of the pre-discharge circuit 102 and the second terminal of the main discharge circuit 103, respectively.
[0051] Optionally, the activation circuit can be used to activate the target chip and thus activate the BMS. Specifically, when the current flowing through the pre-discharge circuit reaches a preset current value, the voltage drop generated on the pre-discharge circuit will cause the first transistor and the second transistor to conduct, thereby activating the target chip. Since the conduction voltage drop of the second transistor is fixed, the preset current value can be changed by adjusting the resistance values of the first resistor and the second resistor, thereby enabling the second transistor to conduct under different currents. This embodiment of the present invention is not limited to this.
[0052] As can be seen, this optional embodiment can achieve intelligent activation of the BMS based on the fixed on-state voltage drop of the transistor, thereby improving the accuracy of BMS activation.
[0053] In yet another alternative embodiment, such as Figure 2 As shown, the main discharge circuit 103 includes a second NMOS transistor M2, a third NMOS transistor M3, and the target chip U1, wherein:
[0054] The gates of the second NMOS transistor M2 and the third NMOS transistor M3 are electrically connected to the third terminal of the target chip U1, respectively. The drains of the second NMOS transistor M2 and the third NMOS transistor M3, as well as the second terminal of the pre-discharge circuit 102, are electrically connected to the second terminal of the activation circuit 101, respectively.
[0055] Optionally, after the BMS enters the active state, the main discharge circuit can be turned on, that is, the second NMOS transistor and the third NMOS transistor can be turned on, so as to realize the intelligent activation of the BMS in the low power sleep state and the intelligent switching between the pre-discharge circuit and the main discharge circuit. This embodiment of the present invention is not limited.
[0056] As can be seen, this optional embodiment can switch between the preamplifier circuit and the main amplifier circuit by turning on the MOS transistor, which can speed up the switching rate between the preamplifier circuit and the main amplifier circuit.
[0057] In yet another alternative embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of another preamplifier circuit for intelligent BMS activation disclosed in this utility model embodiment. The preamplifier circuit for intelligent BMS activation may further include a power supply circuit 104, wherein:
[0058] The first terminal of the power supply circuit 104 is electrically connected to the emitter of the first transistor Q1;
[0059] The power supply circuit 104 is used to provide an activation voltage to the target chip U1 when the activation circuit 101 is used to activate the target chip U1.
[0060] Optional, such as Figure 2 As shown, the power supply circuit includes a third diode D3, a third transistor Q3, a fourth transistor Q4, and a Zener diode D4, wherein:
[0061] The cathode of the third diode D3 is electrically connected to the collector of the third transistor Q3 and the collector of the fourth transistor Q4. The base of the third transistor Q3 is electrically connected to the cathode of the Zener diode D4. The anode of the Zener diode D4 is grounded. The emitter of the third transistor Q3 is electrically connected to the base of the fourth transistor Q4. The emitter of the fourth transistor Q4 is electrically connected to the emitter of the first transistor Q1.
[0062] Optionally, the power supply circuit is used to provide an activation voltage to the target chip when the activation circuit is turned on and used to activate the target chip. The power supply circuit has a step-down function to reduce the voltage to obtain the activation voltage. The voltage value of the activation voltage includes 3.3V, and the error range of the activation voltage includes greater than 2.5V and less than 5V. This embodiment of the present invention does not limit the voltage value.
[0063] Optionally, the power supply circuit may specifically include a step-down circuit composed of a third diode, a third transistor, a fourth transistor, and a Zener diode. The power supply circuit may be connected to the battery cell for power supply. This embodiment of the present invention does not limit the scope of the power supply circuit.
[0064] As can be seen, this optional embodiment can provide an activation voltage based on the power supply circuit to activate the target chip, thereby enabling the BMS to switch from a dormant state to an active state, realizing the intelligent activation of the BMS in a low-power dormant state.
[0065] In yet another alternative embodiment, such as Figure 3 As shown, the preamplifier circuit of the intelligent activation BMS may also include a current limiting circuit 105, such as... Figure 2 As shown, the current limiting circuit 105 includes a third resistor R3 and a fourth resistor R4, wherein:
[0066] The first end of the third resistor R3 and the first end of the fourth resistor R4 are respectively used to connect to the negative terminal B- of the battery cell. The second end of the third resistor R3 and the second end of the fourth resistor R4 are respectively connected to the fourth terminal of the target chip U1, the third terminal of the pre-discharge circuit 102, and the source of the second NMOS transistor M2.
[0067] Furthermore, the source of the third NMOS transistor M3 is used to electrically connect to the negative terminal P- of the load, and the positive terminal of the third diode D3 is used to electrically connect to the positive terminal B+ of the battery cell and the positive terminal P+ of the load, respectively.
[0068] Optionally, the current limiting circuit may include a single resistor or a combination of multiple resistors connected in series or in parallel; the first terminals of the third resistor and the fourth resistor are respectively used to electrically connect to the negative terminal of the battery cell, the source of the third NMOS transistor is used to electrically connect to the negative terminal of the load, and the anode of the third diode is used to electrically connect to the positive terminal of the battery cell and the positive terminal of the load respectively. That is, one end of the preamplifier circuit of the intelligent activation BMS is connected to the positive and negative terminals of the battery cell, and the other end is connected to the positive and negative terminals of the load, which plays a role in protecting the battery cell and the load.
[0069] As can be seen, this optional embodiment can protect the pre-discharge circuit through the current limiting circuit, realize the intelligent activation of the BMS in the low-power sleep state and the intelligent switching between the pre-discharge circuit and the main discharge circuit through the pre-discharge circuit, accelerate the switching rate between the pre-discharge circuit and the main discharge circuit, reduce the possibility of damage from excessive current in the pre-discharge circuit, reduce the possibility of lithium battery explosion and fire, and improve the safety of lithium battery.
[0070] In yet another alternative embodiment, such as Figure 2 As shown, the target chip U1 includes target pins, wherein:
[0071] The emitter of the second transistor Q2 is electrically connected to the target pin;
[0072] Specifically, when the activation circuit 101 is used to activate the target chip U1 to change the BMS from the sleep state to the active state, the target pin of the target chip U1 is detected. When the activation voltage is detected on the target pin, the main discharge circuit 103 is turned on.
[0073] Optionally, the target chip includes a target pin ISEN_CHK. When the current flowing through the pre-discharge circuit reaches a preset current value, the voltage drop generated on the pre-discharge circuit will cause the activation circuit to conduct. The activation circuit is then used to activate the target chip, thereby causing the BMS to switch from a dormant state to an active state. After the BMS enters the active state, the target pin ISEN_CHK can be detected by the target chip current. When a high level is detected on the target pin ISEN_CHK, the main discharge circuit is turned on, realizing the intelligent activation of the BMS in a low-power dormant state and the intelligent switching between the pre-discharge circuit and the main discharge circuit. The high level includes the activation voltage, i.e., 3.3V. This embodiment of the present invention is not limited to this.
[0074] As can be seen, this optional embodiment can, after the BMS enters the active state, detect the target pin ISEN_CHK through the target chip current. When a high level is detected on the target pin ISEN_CHK, the main discharge circuit is turned on, thereby realizing the intelligent activation of the BMS in the low-power sleep state and the intelligent switching between the pre-discharge circuit and the main discharge circuit.
[0075] Example 2
[0076] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a battery disclosed in an embodiment of this utility model. Wherein, Figure 4 The battery shown may include a pre-discharge circuit for intelligently activating the BMS as disclosed in Embodiment 1. This battery enables intelligent activation of the BMS in a low-power sleep state and intelligent switching between the pre-discharge circuit and the main discharge circuit. This accelerates the switching rate between the pre-discharge circuit and the main discharge circuit, reduces the possibility of damage from excessive current in the pre-discharge circuit, reduces the possibility of battery explosion and fire, and improves battery safety. This embodiment of the invention is not limited in scope. It should be noted that for a detailed description of the pre-discharge circuit for intelligently activating the BMS, please refer to the specific description in Embodiment 1; it will not be repeated in this embodiment.
[0077] It is evident that implementation Figure 4 The described battery enables intelligent activation of the BMS in a low-power sleep state and intelligent switching between the pre-discharge circuit and the main discharge circuit. This accelerates the switching rate between the pre-discharge circuit and the main discharge circuit, reduces the possibility of damage from excessive current in the pre-discharge circuit, reduces the possibility of battery explosion and fire, and improves battery safety.
[0078] The pre-discharge circuit and battery for intelligent activation BMS disclosed in the embodiments of this utility model have been described in detail above. Specific embodiments have been used to illustrate the principle and implementation of this utility model. However, the above preferred embodiments are not intended to limit this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of this utility model. At the same time, for those skilled in the art, based on the idea of this utility model, there will be changes in the specific implementation and application scope without departing from the spirit and scope of this utility model. Therefore, the protection scope of this utility model is determined by the scope defined in the claims.
Claims
1. A preamplifier circuit for intelligently activating a BMS, characterized in that, The circuit includes a target chip, an activation circuit, a pre-discharge circuit, and a main discharge circuit, wherein: The first terminal of the target chip is electrically connected to the first terminal of the activation circuit, the second terminal of the target chip is electrically connected to the first terminal of the pre-discharge circuit, the third terminal of the target chip is electrically connected to the first terminal of the main discharge circuit, the second terminal of the pre-discharge circuit and the second terminal of the main discharge circuit are respectively electrically connected to the second terminal of the activation circuit, and the third terminal of the pre-discharge circuit is electrically connected to the third terminal of the main discharge circuit. When the current flowing through the pre-discharge circuit reaches a preset current value, the activation circuit is used to activate the target chip so that the BMS changes from a dormant state to an active state and turns on the main discharge circuit.
2. The preamplifier circuit for the intelligent activation BMS according to claim 1, characterized in that, The pre-discharge circuit includes a first NMOS transistor, a first resistor, a second resistor, and the target chip, wherein: The gate of the first NMOS transistor is electrically connected to the second terminal of the target chip, the source of the first NMOS transistor is electrically connected to the third terminal of the main discharge circuit, the drain of the first NMOS transistor is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively, and the second terminal of the first resistor, the second terminal of the second resistor and the second terminal of the main discharge circuit are electrically connected to the second terminal of the activation circuit. The first resistor and the second resistor are used to adjust the preset current value.
3. The preamplifier circuit for the intelligent activation BMS according to claim 1 or 2, characterized in that, The activation circuit includes a first transistor, a second transistor, a first diode, a second diode, and the target chip, wherein: The collector of the first transistor is electrically connected to the anode of the first diode, the cathode of the first diode is electrically connected to the first terminal of the target chip, the base of the first transistor is electrically connected to the collector of the second transistor, the base of the second transistor is electrically connected to the cathode of the second diode, and the anode of the second diode is electrically connected to the second terminal of the pre-discharge circuit and the second terminal of the main discharge circuit, respectively.
4. The preamplifier circuit for the intelligent activation BMS according to claim 3, characterized in that, The main discharge circuit includes a second NMOS transistor, a third NMOS transistor, and the target chip, wherein: The gates of the second NMOS transistor and the third NMOS transistor are electrically connected to the third terminal of the target chip, respectively. The drains of the second NMOS transistor, the drains of the third NMOS transistor, and the second terminal of the pre-discharge circuit are electrically connected to the second terminal of the activation circuit, respectively.
5. The preamplifier circuit for the intelligent activation BMS according to claim 4, characterized in that, The circuit also includes a power supply circuit, wherein: The first terminal of the power supply circuit is electrically connected to the emitter of the first transistor; The power supply circuit is used to provide an activation voltage to the target chip when the activation circuit is used to activate the target chip.
6. The preamplifier circuit for the intelligent activation BMS according to claim 5, characterized in that, The power supply circuit includes a third diode, a third transistor, a fourth transistor, and a Zener diode, wherein: The negative terminal of the third diode is electrically connected to the collector of the third transistor and the collector of the fourth transistor, respectively. The base of the third transistor is electrically connected to the negative terminal of the Zener diode. The positive terminal of the Zener diode is used for grounding. The emitter of the third transistor is electrically connected to the base of the fourth transistor. The emitter of the fourth transistor is electrically connected to the emitter of the first transistor.
7. The preamplifier circuit for the intelligent activation BMS according to claim 6, characterized in that, The circuit further includes a current limiting circuit, which comprises a third resistor and a fourth resistor, wherein: The first end of the third resistor and the first end of the fourth resistor are respectively used to be electrically connected to the negative terminal of the battery cell, and the second end of the third resistor and the second end of the fourth resistor are respectively electrically connected to the fourth terminal of the target chip, the third terminal of the pre-discharge circuit and the source of the second NMOS transistor. Furthermore, the source of the third NMOS transistor is used to electrically connect to the negative terminal of the load, and the anode of the third diode is used to electrically connect to the positive terminal of the battery cell and the positive terminal of the load, respectively.
8. The preamplifier circuit for the intelligent activation BMS according to any one of claims 5-7, characterized in that, The target chip includes target pins, wherein: The emitter of the second transistor is electrically connected to the target pin; Specifically, when the activation circuit is used to activate the target chip to change the BMS from a dormant state to an active state, the target pin of the target chip is detected, and when the activation voltage is detected on the target pin, the main discharge circuit is turned on.
9. The preamplifier circuit for the intelligent activation BMS according to any one of claims 1, 2, 4, 5, 6, and 7, characterized in that, The target chip model includes OZ7710.
10. A battery comprising a pre-discharge circuit for a smart activation BMS as described in any one of claims 1-9.