Peak current control circuit and switching power supply equipment
By employing a peak current control circuit composed of discrete circuit modules, the problems of high cost and limited flexibility in traditional solutions are solved, achieving fast response and high stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SINENG ELECTRIC CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-19
AI Technical Summary
Traditional peak current control schemes rely on integrated chips, resulting in high costs, limited system design flexibility, and limited dynamic response speed.
The peak current control circuit, which is composed of discrete circuit modules, includes a digital controller, a digital-to-analog converter, a dual-channel sampling and comparison circuit, and a dual-channel trigger logic circuit. It achieves peak current control through an external method, thus overcoming the limitations of chip resources.
It reduces system costs, increases design flexibility, and achieves rapid dynamic response and high stability.
Smart Images
Figure CN224264857U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of switching power supply technology, and in particular to a peak current control circuit and a switching power supply device. Background Technology
[0002] In the field of switching power supplies, peak current control technology is widely used in various power supply topologies due to its fast dynamic response and good stability.
[0003] Traditional peak current control schemes are mainly implemented through integrated chips. Specifically, they use a built-in comparator to detect the current of the switching transistor, compare it with a reference signal generated by the chip, and then adjust the duty cycle of the drive signal to limit the peak current.
[0004] However, traditional peak current control schemes have the following drawbacks:
[0005] Built-in control chips and external DAC modules are expensive and need to be laid out on the same board as the controller, which limits the flexibility and cost of system design;
[0006] The reliance on internal chip resources, such as the number of DAC channels and comparators, limits system scalability.
[0007] Most of them use average current control, and their feedback loop depends on the filtered average current signal, which limits the dynamic response speed. Utility Model Content
[0008] This invention proposes a peak current control circuit and a switching power supply device, aiming to solve the problem of peak current control being limited by chip resources.
[0009] To achieve the above objectives, this utility model provides a peak current control circuit applied to a dual-transistor forward power circuit. The dual-transistor forward power circuit includes a set of upper switching transistors and a set of lower switching transistors. The peak current control circuit includes a digital controller, a digital-to-analog converter circuit, a dual-channel sampling and comparison circuit, and a dual-channel trigger logic circuit.
[0010] The digital controller receives the isolation voltage sampling signal output by the dual-transistor forward power circuit at its input terminal. The first output terminal of the digital controller is connected to the input terminal of the digital-to-analog converter circuit. The second and third output terminals of the digital controller are respectively connected to the first and second clock terminals of the dual-path trigger logic circuit. The output terminal of the digital-to-analog converter circuit is connected to the first and third input terminals of the dual-path sampling comparator circuit. The second and fourth input terminals of the dual-path sampling comparator circuit sample the current signals of the upper and lower switching transistors, respectively. The first and second output terminals of the dual-path sampling comparator circuit are respectively connected to the first and second reset terminals of the dual-path trigger logic circuit. The first and second output terminals of the dual-path trigger logic circuit are respectively connected to the driving circuits of the upper and lower switching transistors.
[0011] The digital controller is used to generate a pulse width modulation signal based on the isolation voltage sampling signal and output two clock signals.
[0012] The digital-to-analog converter circuit is used to convert the pulse width modulation signal into a reference current signal through active filtering and ripple suppression.
[0013] The dual-channel sampling and comparison circuit is used to generate a low-level trigger reset signal when the current signal of the switching transistor exceeds the reference current signal.
[0014] The dual-path trigger logic circuit is used to turn on the switch transistor on the rising edge of the clock signal, turn off the switch transistor when the trigger reset signal is low, and turn off the switch transistor on the falling edge of the clock signal when the trigger reset signal is high.
[0015] Furthermore, the digital-to-analog conversion circuit includes an inverter circuit and an active filter circuit;
[0016] The input terminal of the inverter circuit is connected to the first output terminal of the digital controller, the output terminal of the inverter circuit is connected to the input terminal of the active filter circuit, and the output terminal of the active filter circuit is connected to the first and third input terminals of the dual-channel sampling comparison circuit.
[0017] Furthermore, the inverter circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh diode, an eighth diode, a first inverter, and a second inverter;
[0018] The first resistor and the second resistor are connected in parallel. One end of the first resistor is connected to the first output terminal of the digital controller, and the other end is connected to the input terminal of the first inverter.
[0019] The anode of the seventh diode and the cathode of the eighth diode are connected to the input terminal of the first inverter. The cathode of the seventh diode is connected to a power supply, and the anode of the eighth diode is grounded.
[0020] One end of the third resistor and one end of the fourth capacitor are connected to the input terminal of the first inverter, and the other end of the third resistor and the other end of the fourth capacitor are grounded.
[0021] The output terminal of the first inverter is connected to the input terminal of the second inverter and one end of the fourth resistor, and the output terminal of the second inverter is connected to the input terminal of the active filter circuit via the fifth resistor;
[0022] The other end of the fourth resistor is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the input terminal of the active filter circuit and one end of the sixth capacitor, and the other end of the sixth capacitor is grounded.
[0023] Furthermore, the active filter circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a seventh capacitor, an eighth capacitor, and a first operational amplifier;
[0024] One end of the sixth resistor is connected to the output terminal of the inverter circuit, the other end of the sixth resistor is connected to one end of the seventh resistor and one end of the seventh capacitor, and the other end of the seventh resistor is connected to the positive input terminal of the first operational amplifier.
[0025] The eighth resistor and the eighth capacitor are connected in parallel, with one end connected to the positive input terminal of the first operational amplifier and the other end grounded; the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier and the other end of the seventh capacitor.
[0026] The output terminal of the first operational amplifier is connected to the first input terminal and the third input terminal of the dual-channel sampling and comparison circuit.
[0027] Furthermore, the dual-channel sampling comparison circuit includes two sets of sampling comparison circuits;
[0028] The first input terminal and the second input terminal of one set of the sampling comparison circuits are respectively the first input terminal and the second input terminal of the dual-channel sampling comparison circuit, and the output terminal of one set of the sampling comparison circuits is the first output terminal of the dual-channel sampling comparison circuit;
[0029] The first and second input terminals of the other set of sampling comparison circuits are the third and fourth input terminals of the dual-channel sampling comparison circuit, respectively, and the output terminal of the other set of sampling comparison circuits is the second output terminal of the dual-channel sampling comparison circuit.
[0030] Furthermore, the sampling and comparison circuit includes a DC pulse transformer, a ninth resistor, a tenth resistor, an eleventh resistor, a ninth diode, a tenth diode, an eleventh diode, a ninth capacitor, an emitter follower, and a comparator;
[0031] One end of the main coil of the DC pulse transformer is the second input terminal of the sampling comparison circuit. The other end of the main coil is connected to the intermediate bus or grounded. One end of the secondary coil of the DC pulse transformer is connected to the positive terminal of the ninth diode. The negative terminal of the ninth diode is connected to one end of the ninth resistor, one end of the tenth resistor, and one end of the eleventh resistor. The other end of the secondary coil, the other end of the ninth resistor, and the other end of the tenth resistor are grounded.
[0032] The other end of the eleventh resistor is connected to the positive input terminal of the emitter follower, the positive terminal of the tenth diode, the negative terminal of the eleventh diode, and one end of the ninth capacitor.
[0033] The negative terminal of the tenth diode is connected to a power source, the positive terminal of the eleventh diode is grounded, and the other end of the ninth capacitor is grounded.
[0034] The output terminal of the emitter follower is connected to the negative input terminal of the emitter follower and the negative input terminal of the comparator. The positive input terminal of the comparator is the first input terminal of the sampling comparison circuit, and the output terminal of the comparator is the output terminal of the sampling comparison circuit.
[0035] Furthermore, the dual-path triggering logic circuit includes two sets of flip-flops and AND gates;
[0036] The clock port of one group of the flip-flops and the first input of one group of the AND gates are both connected to the second output of the digital controller. The reset port of one group of the flip-flops is connected to the first output of the dual-channel sampling comparison circuit. The output port of one group of the flip-flops is connected to the second input of one group of the AND gates. The output of one group of the AND gates is connected to the driving circuit of the upper switching transistor.
[0037] The clock port of the other set of flip-flops and the first input of the other set of AND gates are both connected to the third output of the digital controller. The reset port of the other set of flip-flops is connected to the second output of the dual-channel sampling comparison circuit. The output port of the other set of flip-flops is connected to the second input of the other set of AND gates. The output of the other set of AND gates is connected to the driving circuit of the lower switching transistor.
[0038] This utility model also provides a switching power supply device, which includes a dual-transistor forward power circuit and a peak current control circuit as described in any of the above claims, wherein the dual-transistor forward power circuit and the peak current control circuit are electrically connected.
[0039] Furthermore, the dual-transistor forward power circuit includes a first capacitor, a second capacitor, a third capacitor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first inductor, a first upper switch transistor, a second upper switch transistor, a first lower switch transistor, a second lower switch transistor, a high-frequency transformer, and an isolation circuit;
[0040] The first capacitor and the second capacitor are connected in series at both ends of the bus. The middle node of the first capacitor and the second capacitor is connected to the positive terminal of the first diode, the negative terminal of the fourth diode, the source of the second upper switch, and the drain of the first lower switch.
[0041] The drain of the first upper switch transistor and the cathode of the second diode are connected to one end of the bus, and the source of the first upper switch transistor is connected to the cathode of the first diode and the same-name terminal of the primary winding of the high-frequency transformer.
[0042] The drain of the second upper switch is connected to the anode of the second diode and the opposite terminal of the primary winding of the high-frequency transformer; the source of the second upper switch is connected to the second input terminal of the dual-channel sampling comparison circuit of the peak current control circuit; the gates of the first upper switch and the second upper switch are connected to the driving circuit of the upper switch.
[0043] The source of the first lower switch is connected to the negative terminal of the third diode and the same terminal of the primary winding of the high-frequency transformer, and the positive terminal of the third diode is connected to the other end of the bus.
[0044] The drain of the second lower switch is connected to the anode of the fourth diode and the opposite terminal of the second winding of the primary side of the high-frequency transformer; the source of the second lower switch is connected to the other end of the bus and the fourth input terminal of the dual-channel sampling and comparison circuit; the gates of the first lower switch and the second lower switch are connected to the driving circuit of the lower switch.
[0045] The same-name terminal of the first secondary winding of the high-frequency transformer is connected to the positive terminal of the fifth diode and the same-name terminal of the second secondary winding; the negative terminal of the fifth diode is connected to the negative terminal of the sixth diode and one end of the first inductor; the other end of the first inductor is connected to one end of the third capacitor and the input terminal of the isolation circuit; the output terminal of the isolation circuit is connected to the input terminal of the digital controller of the peak current control circuit.
[0046] The opposite terminal of the first secondary winding of the high-frequency transformer is connected to the opposite terminal of the second secondary winding, the positive terminal of the sixth diode, and the other end of the third capacitor.
[0047] The technical solution of this utility model involves a digital controller generating a pulse width modulation (PWM) signal and two clock signals based on the isolation voltage sampling signal output from the dual-transistor forward power circuit. A digital-to-analog converter (DAC) converts the PWM signal into a reference current signal through active filtering and ripple suppression. A dual-channel sampling and comparison circuit compares the sampled current signals of the upper and lower switching transistors with the reference current signal. When the current signals of the upper and lower switching transistors exceed the reference current signal, a low-level trigger reset signal is output to the dual-channel trigger logic circuit. The dual-channel trigger logic circuit activates the switching transistors on the rising edge of the clock signal, drives them to turn off when the trigger reset signal is low, and turns them off on the falling edge of the clock signal when the trigger reset signal is high. Because this utility model uses discrete circuit modules to construct the external peak current control circuit of the dual-transistor forward power circuit, it overcomes the limitations of chip resources and reduces the cost of peak current control, significantly lowering the system cost. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0049] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the peak current control circuit and the dual-transistor forward power circuit of this utility model;
[0050] Figure 2 for Figure 1 A circuit block diagram of an embodiment of a digital-to-analog converter circuit;
[0051] Figure 3 for Figure 2 A schematic diagram of the circuit structure of an embodiment of a digital-to-analog converter circuit;
[0052] Figure 4 for Figure 1 A block diagram of an embodiment of a dual-channel sampling comparison circuit;
[0053] Figure 5 for Figure 4 A schematic diagram of the circuit structure of an embodiment of a sampling comparison circuit;
[0054] Figure 6 for Figure 1 A schematic diagram of the circuit structure of an embodiment of a dual-path trigger logic circuit.
[0055] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0056] It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0057] Existing technologies rely on chip integration to achieve peak current control, which is limited by chip resources and requires additional slope compensation circuitry. This invention uses discrete circuit modules to construct an external peak current control circuit for a dual-transistor forward power circuit. Therefore, it can overcome the limitations of chip resources in peak current control and reduce the cost of peak current control, significantly lowering the overall system cost.
[0058] Example 1
[0059] Reference Figure 1 The peak current control circuit 200 is applied to a dual-transistor forward power circuit, which includes a set of upper switching transistors Q1 and Q2 and a set of lower switching transistors Q3 and Q4. The peak current control circuit 200 includes a digital controller 10, a digital-to-analog converter circuit 20, a dual-channel sampling and comparison circuit 30, and a dual-channel trigger logic circuit 40.
[0060] The connection is as follows: The input terminal of digital controller 10 receives the isolation voltage sampling signal V from the output of the dual-transistor forward power circuit. O The first output terminal of the digital controller 10 is connected to the input terminal of the digital-to-analog converter circuit 20. The second and third output terminals of the digital controller 10 are respectively connected to the first and second clock terminals of the dual-channel trigger logic circuit 40. The output terminal of the digital-to-analog converter circuit 20 is connected to the first and third input terminals of the dual-channel sampling and comparison circuit 30. The second and fourth input terminals of the dual-channel sampling and comparison circuit 30 respectively sample the current signal i of the switching transistor Q2. Q2 and the current signal i of the lower switching transistor Q4 Q4 The first and second output terminals of the dual-channel sampling and comparison circuit 30 are respectively connected to the first and second reset terminals of the dual-channel trigger logic circuit 40; the first and second output terminals of the dual-channel trigger logic circuit 40 are respectively connected to the driving circuits of a set of upper switching transistors and a set of driving circuits of lower switching transistors.
[0061] The digital controller 10, which can be an MCU, DSP, or other programmable logic device, is used to sample the isolated voltage signal V output by the dual-transistor forward power circuit. OThe voltage is compared with its internal set voltage, and a pulse width modulation signal PWM_DA is generated using pulse width chopping. Furthermore, the digital controller 10 outputs two clock signals PWM_CLK1 and PWM_CLK2 with a phase difference of 180° according to a preset duty cycle threshold. This preset duty cycle threshold can be set to 0.4. By setting the duty cycle threshold to 0.4, the risk of subharmonic oscillation is eliminated, thus eliminating the need for an additional slope compensation device, resulting in a more stable system. The clock signals PWM_CLK1 and PWM_CLK2 are complementary signals with a phase difference of 180°. This configuration enables the dual-transistor forward power circuit to achieve high power density, high reliability, and fast dynamic response.
[0062] The digital-to-analog converter circuit 20 converts the pulse width modulation signal PWM_DA into a reference current signal Iref through reverse ripple suppression and multi-stage active filtering, providing a reference for the current loop ratio. This invention converts the isolated voltage sampling signal Vo output from the dual-transistor forward power circuit into a pulse width modulation signal PWM_DA, and then obtains the reference current signal Iref based on the PWM_DA to achieve closed-loop voltage control. It can also cope with changes in input load, achieving high stability and fast response.
[0063] The dual-channel sampling and comparison circuit 30 can be composed of two sets of DC pulse transformers and a comparison circuit; the dual-channel sampling and comparison circuit 30 is used to sample the current signal i of the upper and lower switching transistors respectively. Q2 andi Q4 The current signal i of the upper switching transistor Q2 The current signal i of the upper switching transistor is compared with the reference current signal Iref. Q2 When the reference current signal Iref is exceeded, a low-level trigger reset signal RESET1 is output to the first reset terminal of the dual-channel trigger logic circuit 40; and the current signal i of the lower switching transistor is... Q4 The current signal i of the lower switching transistor is compared with the reference current signal Iref. Q4 When the current exceeds the reference current signal Iref, a low-level trigger reset signal RESET2 is output to the second reset terminal of the dual-path trigger logic circuit 40.
[0064] The dual-trigger logic circuit 40 can be composed of dual D flip-flops such as 74HC74 and two AND gates. The dual-trigger logic circuit 40 is used to start the upper and lower sets of switching transistors on the rising edges of the clock signal PWM_CLK1 and the rising edges of the clock signal PWM_CLK2, respectively, and drive the upper and lower sets of switching transistors to turn off according to the low-level trigger reset signals RESET1 and RESET2 when the upper and lower switching transistors are overcurrent.
[0065] The specific process is as follows:
[0066] The digital controller 10 samples the isolation voltage signal V from the output of the two-transistor forward power circuit. O The pulse width modulation signal PWM_DA is dynamically generated. After reverse ripple suppression and multi-stage active filtering by the digital-to-analog converter circuit 10, the PWM_DA signal is converted into a reference current signal Iref. The dual-channel sampling and comparison circuit 30 samples the current signal i of the switching transistor. Q2 and the current signal i of the switching transistor Q4 And compare it with the reference current signal Iref respectively; if the current signal i of the upper switch transistor is... Q2 If the current exceeds the reference current signal Iref, indicating an overcurrent in the upper switching transistor, the dual-channel sampling and comparison circuit 30 outputs a low-level trigger reset signal RESET1; if the current signal i of the lower switching transistor exceeds the reference current signal Iref, the upper switching transistor experiences an overcurrent. Q4 If the current exceeds the reference current signal Iref, indicating an overcurrent in the lower switching transistor, the dual-channel sampling and comparison circuit 30 outputs a low-level trigger reset signal RESET2.
[0067] The dual-path trigger logic circuit 40 performs the following operations: A set of upper switching transistors is turned on at the rising edge of the clock signal PWM_CLK1; when an upper switching transistor experiences overcurrent, a set of upper switching transistors is turned off according to the low-level trigger reset signal RESET1 to limit the peak current; when the trigger reset signal RESET1 is high, a set of upper switching transistors is turned off by the falling edge of the clock signal PWM_CLK1. Similarly, a set of lower switching transistors is turned on at the rising edge of the clock signal PWM_CLK2; when a lower switching transistor experiences overcurrent, a set of lower switching transistors is turned off according to the low-level trigger reset signal RESET2 to limit the peak current; when the trigger reset signal RESET2 is high, a set of lower switching transistors is turned off by the falling edge of the clock signal PWM_CLK2, thereby achieving closed-loop control of the peak current.
[0068] This invention achieves peak current control through an external discrete circuit module, enabling rapid closed-loop response and ensuring stable output voltage. It overcomes the limitations of traditional peak current control, which is constrained by chip resources, and reduces the cost of peak current control. Furthermore, this invention allows the external peak current control circuit to be placed on different circuit boards, improving design flexibility.
[0069] Example 2
[0070] Reference Figure 2 In one specific embodiment of this utility model, the digital-to-analog converter circuit 20 includes an inverter circuit 201 and an active filter circuit 202; the input terminal of the inverter circuit 201 is connected to the first output terminal of the digital controller 10, the output terminal of the inverter circuit 201 is connected to the input terminal of the active filter circuit 202, and the output terminal of the active filter circuit 202 is connected to the first and third input terminals of the dual-channel sampling comparison circuit 30.
[0071] In this embodiment, the inverter circuit 201 is used to reverse the pulse width modulation signal to generate a ripple component with opposite phase. The reverse ripple is then coupled to the filter node and superimposed and canceled by the high-frequency ripple of the original signal, thereby suppressing the output ripple.
[0072] The active filter circuit 202 is a high-order active filter circuit used to filter out high-frequency noise in the pulse width modulation signal PWM_DA in order to output a low-ripple voltage signal.
[0073] To better illustrate the technical concept of this invention, the voltage signal output by the active filter circuit 202 is equivalent to a reference current signal Iref for comparison with the current signals of the upper and lower switching transistors. Here, voltage = D (duty cycle) * PWM_DA (amplitude), meaning the voltage output by the digital-to-analog converter circuit 20 is determined by the duty cycle of the pulse width modulation signal PWM_DA. It is understandable that the corresponding reference current signal Iref is also determined by the duty cycle of the pulse width modulation signal PWM_DA. This embodiment, through the coordinated operation of reverse ripple suppression and multi-stage filtering, converts the pulse width modulation signal PWM_DA into an equivalent reference current signal Iref, thereby achieving high-precision, high-dynamic digital-to-analog conversion.
[0074] Reference Figure 3 In one specific embodiment, the inverter circuit 201 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh diode D7, an eighth diode D8, a first inverter U1, and a second inverter U2.
[0075] The connections are as follows: The first resistor R1 and the second resistor R2 are connected in parallel, with one end connected to the first output terminal of the digital controller 10 and the other end connected to the input terminal of the first inverter U1; the anode of the seventh diode D7 and the cathode of the eighth diode D8 are connected to the input terminal of the first inverter U1, the cathode of the seventh diode D7 is connected to a power supply VCC, and the anode of the eighth diode D8 is grounded; one end of the third resistor R3 and one end of the fourth capacitor C4 are connected to the input terminal of the first inverter U1, and the other end of the third resistor R3 and the other end of the fourth capacitor C4 are grounded; the output terminal of the first inverter U1 is connected to the input terminal of the second inverter U2 and one end of the fourth resistor R4, and the output terminal of the second inverter U2 is connected to the input terminal of the active filter circuit 202 via the fifth resistor R5; the other end of the fourth resistor R4 is connected to one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is connected to the input terminal of the active filter circuit 202 and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded.
[0076] In this embodiment, the pulse width modulation signal PWM_DA output by the digital controller 10 is inverted by the first inverter U1, and coupled to the filter node through the fourth resistor R4 and the fifth capacitor C5, so as to superimpose the high frequency ripple of the original signal in the opposite direction and achieve ripple cancellation.
[0077] More specifically, the pulse width modulation signal PWM_DA, after being divided, enters a first-order RC filter composed of the fifth resistor R5 and the sixth capacitor C6; the other path is coupled to the filter node via the first inverter U1, the fourth resistor R4, and the fifth capacitor C5. The high-frequency ripples of the two signals are out of phase, and theoretically, they can cancel each other out by appropriately setting the resistor values. However, because the fifth capacitor C5 generates a voltage drop, the ripples of the two signals cannot be completely canceled out. If the resistance values of the fourth resistor R4 and the fifth resistor R5 are small, the response speed is fast, but the ripple suppression effect is reduced; if the resistance values of the fourth resistor R4 and the fifth resistor R5 are large, the ripple suppression effect is strong, but the response delay increases. Therefore, the resistance values of the fourth resistor R4 and the fifth resistor R5 can be set appropriately as needed. Furthermore, the resistance values of the fourth resistor R4 and the fifth resistor R5 can be the same.
[0078] Reference Figure 3 In one specific embodiment, the active filter circuit 202 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a seventh capacitor C7, an eighth capacitor C8, and a first operational amplifier U3;
[0079] The connections are as follows: one end of the sixth resistor R6 is connected to the output of the inverter circuit 201, the other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and one end of the seventh capacitor C7, and the other end of the seventh resistor R7 is connected to the positive input of the first operational amplifier U3; one end of the eighth resistor R8 and the eighth capacitor C8 connected in parallel is connected to the positive input of the first operational amplifier U3, and the other end is grounded to GND; the negative input of the first operational amplifier U3 is connected to the output of the first operational amplifier U3 and the other end of the seventh capacitor C7; the output of the first operational amplifier U3 is connected to the first and third inputs of the dual-channel sampling comparator circuit 30.
[0080] In this embodiment, the first operational amplifier U3, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the seventh capacitor C7, and the eighth capacitor C8 constitute a multi-stage active filter to further filter out high-frequency noise.
[0081] Example 3
[0082] Reference Figure 4 In one specific embodiment of this utility model, the dual-channel sampling comparison circuit 30 includes two sets of sampling comparison circuits;
[0083] The first and second input terminals of one set of sampling comparison circuits are respectively the first and second input terminals of the dual-channel sampling comparison circuit 30, and the output terminal of one set of sampling comparison circuits is the first output terminal of the dual-channel sampling comparison circuit 30; the first and second input terminals of the other set of sampling comparison circuits are respectively the third and fourth input terminals of the dual-channel sampling comparison circuit 30, and the output terminal of the other set of sampling comparison circuits is the second output terminal of the dual-channel sampling comparison circuit 30.
[0084] If the two sets of sampling comparison circuits are represented as the first set of sampling comparison circuits and the second set of sampling comparison circuits, then the first input terminal and the second input terminal of the first set of sampling comparison circuits are the first input terminal and the second input terminal of the dual-channel sampling comparison circuit 30, respectively, and the output terminal of the first set of sampling comparison circuits is the first output terminal of the dual-channel sampling comparison circuit 30; the first input terminal and the second input terminal of the second set of sampling comparison circuits are the third input terminal and the fourth input terminal of the dual-channel sampling comparison circuit 30, respectively, and the output terminal of the second set of sampling comparison circuits is the second output terminal of the dual-channel sampling comparison circuit 30.
[0085] In this embodiment, one set of sampling and comparison circuits samples the current signal i of the upper switch Q2. Q2 And sample the current signal i of the upper switch Q2 Q2 The current signal i of the upper switching transistor is compared with the reference current signal Iref. Q2 When the current exceeds the reference current signal Iref, one of the sampling and comparison circuits outputs a low-level trigger reset signal RESET1 to the dual-channel trigger logic circuit 40, which then turns off a set of upper switching transistors Q1 and Q2. If the sampled current signal i... Q2 If the reference current signal Iref is never exceeded during the cycle, then the upper switching transistors Q1 and Q2 are turned off by the falling edge of the clock signal PWM_CLK1.
[0086] Another set of sampling and comparison circuits samples the current signal i of the switch Q4. Q4 And sample the current signal i of the lower switching transistor. Q4 The current signal i of the lower switch Q4 is compared with the analog reference current Iref. Q4 When the current exceeds the reference current signal Iref, another set of sampling and comparison circuits outputs a low-level trigger reset signal RESET2 to the dual-channel trigger logic circuit 40, which then turns off one set of lower switching transistors. If the sampled current signal i... Q4 If the reference current signal Iref is never exceeded during the cycle, then a set of lower switching transistors Q3 and Q4 are turned off by the falling edge of the clock signal PWM_CLK2.
[0087] Reference Figure 5 In one specific embodiment, the two sets of sampling comparison circuits have the same structure, both including a DC pulse transformer T1, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a ninth diode D9, a tenth diode D10, an eleventh diode D11, a ninth capacitor C9, an emitter follower U4, and a comparator U5.
[0088] The connection is as follows: one end of the main coil of DC pulse transformer T1 is the second input terminal of the sampling comparator circuit to sample the current signal of the upper or lower switching transistor; the other end of the main coil is connected to the intermediate bus BUS_M or to ground; one end of the secondary coil of DC pulse transformer T1 is connected to the positive terminal of the ninth diode D9, the negative terminal of the ninth diode D9 is connected to one end of the ninth resistor R9, one end of the tenth resistor R10, and one end of the eleventh resistor R11, and the other end of the secondary coil, the other end of the ninth resistor R9, and the other end of the tenth resistor R10 are grounded; the other end of the eleventh resistor R11 is connected to... The positive input terminal of emitter follower U4, the positive terminal of the tenth diode D10, the negative terminal of the eleventh diode D11, and one end of the ninth capacitor C9 are connected; the negative terminal of the tenth diode D10 is connected to a power supply VCC, the positive terminal of the eleventh diode D11 is grounded, and the other end of the ninth capacitor C9 is grounded; the output terminal of emitter follower U4 is connected to the negative input terminal of emitter follower U4 and the negative input terminal of comparator U5, the positive input terminal of comparator U5 is the first input terminal of the sampling comparison circuit to receive the reference current signal Iref output by the digital-to-analog converter circuit 20, and the output terminal of comparator U5 is the output terminal of the sampling comparison circuit.
[0089] If we represent the two sets of sampling comparison circuits as the first set of sampling comparison circuits and the second set of sampling comparison circuits, the connection relationships of the DC pulse transformers T1 in the two sets of sampling comparison circuits differ as follows: In the first set of sampling comparison circuits, one end of the main coil of the DC pulse transformer T1 is connected to the source of the upper switching transistor Q2, and the other end of the main coil of the DC pulse transformer T1 is connected to the intermediate bus BUS_M. In the second set of sampling comparison circuits, one end of the main coil of the DC pulse transformer T1 is connected to the source of the lower switching transistor Q4, and the other end of the main coil of the DC pulse transformer T1 is grounded to GND.
[0090] In this embodiment, the DC pulse transformer T1 in the two sets of sampling and comparison circuits is used to sample the current signal of the upper switch Q2 and the current signal of the lower switch Q4, respectively, and converts the sampled current signal into a small current. The sampled current signal forms a voltage signal across the ninth resistor R9 and the tenth resistor R10. This voltage signal is then limited by the tenth diode D10, filtered by the eleventh resistor R11 and the ninth capacitor C9, and finally amplified by the emitter follower U4 before being input to the negative input terminal of the comparator U5. The positive input terminal of the comparator U5 receives the reference current signal Iref output by the digital-to-analog converter circuit 20. When the current signal of the upper or lower switch exceeds the reference current signal Iref, the comparator U5 outputs a low-level trigger reset signal RESET1 or a low-level trigger reset signal RESET2 to the dual-path trigger logic circuit 40.
[0091] Example 4
[0092] Reference Figure 6 In one specific embodiment of this utility model, the dual-path trigger logic circuit 40 includes two sets of flip-flops and AND gates;
[0093] The clock port C of one set of flip-flops U6 and the first input of one set of AND gates U7 are both connected to the second output of digital controller 10 to receive clock signal PWM_CLK1; the reset port R of one set of flip-flops U6 is connected to the first output of dual-channel sampling and comparison circuit 30; the output port Q of one set of flip-flops U6 is connected to the second input of one set of AND gates U7; and the output of one set of AND gates U7 is connected to the drive circuit of the upper switching transistor.
[0094] The clock port of another set of flip-flops U6 and the first input of another set of AND gates U7 are both connected to the third output of digital controller 10 to receive the clock signal PWM_CLK2. The reset port R of another set of flip-flops U6 is connected to the second output of dual-channel sampling and comparison circuit 30. The output port Q of another set of flip-flops U6 is connected to the second input of another set of AND gates U7. The output of another set of AND gates is connected to the driving circuit of the lower switching transistor.
[0095] If the two sets of flip-flops and AND gates are represented as the first set of flip-flops and AND gates and the second set of flip-flops and AND gates, then the clock port C of the first set of flip-flops U6 and the first input of the first set of AND gates U7 are both connected to the second output of the digital controller 10 to receive the clock signal PWM_CLK1; the reset port R of the first set of flip-flops U6 is connected to the first output of the dual-channel sampling and comparison circuit 30; the output port Q of the first set of flip-flops U6 is connected to the second input of the first set of AND gates U7; and the output of the first set of AND gates U7 is connected to the driving circuit of the upper switching transistor.
[0096] The clock port C of the second group of flip-flops U6 and the first input of the second group of AND gates U7 are both connected to the third output of the digital controller 10 to receive the clock signal PWM_CLK2. The reset port R of the second group of flip-flops U6 is connected to the second output of the dual-channel sampling and comparison circuit 30. The output port Q of the second group of flip-flops U6 is connected to the second input of the second group of AND gates U7. The output of the second group of AND gates is connected to the driving circuit of the lower switching transistor.
[0097] In this embodiment, the working principle of the dual-path triggering logic circuit is as follows:
[0098] For a group of upper switching transistors: The upper switching transistors are turned on at the rising edge of the clock signal PWM_CLK1. When the current signal i of the upper switching transistor Q2... Q2 When the current exceeds the reference current signal Iref, the first output of the dual-channel sampling and comparison circuit 30 outputs a low-level trigger reset signal RESET1 to the reset terminal of one of the flip-flops U6, thereby causing the normal output terminal Q of one of the flip-flops U6 to output 0. At this time, the drive signal PWM1 output by one of the AND gates U7 is equal to 0, thereby forcing the upper switching transistors Q1 and Q2 to turn off simultaneously, thus achieving peak current limiting.
[0099] For a group of lower switching transistors: A group of lower switching transistors is turned on at the rising edge of the clock signal PWM_CLK2, and the current signal i of the lower switching transistor is... Q4 When the current exceeds the reference current signal Iref, the second output of the dual-channel sampling and comparison circuit 30 outputs a low-level trigger reset signal RESET2 to the reset terminal of another set of flip-flops U6, thereby causing the normal output terminal Q of the other set of flip-flops U6 to output 0. At this time, the drive signal PWM2 output by the other set of AND gates U7 is equal to 0, thereby forcing the lower set of switching transistors Q3 and Q4 to turn off simultaneously, thus achieving peak current limiting.
[0100] If the current signals of the upper and lower switching transistors are less than the reference current signal, i.e. Q2 Less than Iref, or i Q4 If the value is less than Iref, the duty cycle of the drive signal is determined by a preset duty cycle threshold of the clock signal, which is 0.4. In this embodiment, a dual D flip-flop, such as a 74HC74 flip-flop, is used as two sets of flip-flops. The set input S and data input D of the flip-flops are connected to a power supply VCC.
[0101] The flip-flop, through asynchronous reset, immediately shuts off the switching transistor during overcurrent, resulting in a fast response. Furthermore, the flip-flop's data terminal D always receives a high level, allowing it to rely solely on the clock and reset signals for switching control, eliminating the need for a complex state machine.
[0102] Example 5
[0103] Reference Figure 1 This utility model also provides a switching power supply device, which includes a two-transistor forward power circuit and a peak current control circuit as described in any of the above embodiments. The two-transistor forward power circuit and the peak current control circuit are electrically connected. The detailed structure of the peak current control circuit can be found in the above embodiments and will not be repeated here. It is understood that since the above-mentioned peak current control circuit is used in the switching power supply device of this utility model, the embodiments of the switching power supply device of this utility model include all the technical solutions of all embodiments of the above-mentioned peak current control circuit, and the achieved technical effects are completely the same, and will not be repeated here.
[0104] Reference Figure 1 In one specific embodiment, the dual-transistor forward power circuit of this utility model includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a first inductor L1, a first upper switch Q1, a second upper switch Q2, a first lower switch Q3, a second lower switch Q4, a high-frequency transformer, and an isolation circuit 100.
[0105] The connection is as follows: the first capacitor C1 and the second capacitor C2 are connected in series across the two ends of the bus Vbus. The midpoint between the first capacitor C1 and the second capacitor C2 is connected to the anode of the first diode D1, the cathode of the fourth diode D4, the source of the second upper switch Q2, and the drain of the first lower switch Q3. The drain of the first upper switch Q1 and the cathode of the second diode D2 are connected to one end of the bus Vbus. The source of the first upper switch Q1 is connected to the cathode of the first diode D1 and the same-name terminal of the first winding of the primary side of the high-frequency transformer. The drain of the second upper switch Q2 is connected to the anode of the second diode D2 and the opposite-name terminal of the first winding of the primary side of the high-frequency transformer. The source of the second upper switch Q2 is connected to the second input terminal of the dual-channel sampling comparison circuit 30 of the peak current control circuit. The gates of the first upper switch Q1 and the second upper switch Q2 are connected to the driving circuit of the upper switch. The source of the first lower switch Q3 is connected to the cathode of the third diode D3 and the same-name terminal of the second winding of the primary side of the high-frequency transformer. The anode of diode D3 is connected to the other end of bus Vbus; the drain of the second lower switch Q4 is connected to the anode of the fourth diode D4 and the opposite terminal of the second winding of the primary side of the high-frequency transformer; the source of the second lower switch Q4 is connected to the other end of bus Vbus and the fourth input terminal of the dual-channel sampling comparison circuit 30; the gates of the first lower switch Q3 and the second lower switch Q4 are connected to the driving circuit of the lower switch; the same terminal of the first winding of the secondary side of the high-frequency transformer is connected to the anode of the fifth diode D5 and the same terminal of the second winding of the secondary side; the cathode of the fifth diode D5 is connected to the cathode of the sixth diode D6 and one end of the first inductor L1; the other end of the first inductor L1 is connected to one end of the third capacitor C3 and the input terminal of the isolation circuit 100; the output terminal of the isolation circuit 100 is connected to the input terminal of the digital controller 10 of the peak current control circuit; the opposite terminal of the first winding of the secondary side of the high-frequency transformer is connected to the opposite terminal of the second winding of the secondary side, the anode of the sixth diode D6, and the other end of the third capacitor C3.
[0106] In this embodiment, the dual-transistor forward power circuit is used to complete the isolation conversion of the input voltage and the power output, supporting high voltage input and high current output.
[0107] The first upper switch Q1 and the second upper switch Q2 form a pair of upper switches, and the first lower switch Q3 and the second lower switch Q4 form a pair of lower switches. Each pair of switches is connected in series to withstand half of the input voltage, thereby reducing the voltage stress on individual switches. The two pairs of switches conduct alternately with a phase difference of 180°, converting the input DC voltage into a high-frequency AC signal. The first upper switch Q1, the second upper switch Q2, the first lower switch Q3, and the second lower switch Q4 can be selected as MOSFETs.
[0108] Diodes D1, D2, D3, and D4 are clamping diodes used to absorb leakage inductance energy from the transformer and prevent voltage spikes when the switching transistor is turned off. Diodes D5 and D6 are rectifier diodes used to rectify the AC current on the secondary side of the high-frequency transformer into DC current. Inductor L1 and capacitor C3 are used to smooth the output current and voltage, reducing ripple.
[0109] High-frequency transformers are used to achieve voltage transformation and electrical isolation; parallel output on the secondary side of a high-frequency transformer can achieve high current output and significantly improve the output current capability.
[0110] The isolation circuit 100 can use a controllable precision voltage regulator TL431 plus an optocoupler or a magnetic coupler to achieve voltage signal isolation.
[0111] In one specific embodiment, the isolation circuit 100 includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a thyristor, and an optocoupler.
[0112] The connection is as follows: one end of the twelfth resistor is connected to a power supply, and the other end of the twelfth resistor is connected to the input terminal of the digital controller 10 and the collector of the optocoupler through a connector. The emitter of the optocoupler is grounded. The anode of the optocoupler is connected to one end of the thirteenth resistor, and the other end of the thirteenth resistor is interconnected with one end of the fourteenth resistor, one end of the sixteenth resistor, and one end of the thirteenth capacitor. The common terminal of the thirteenth resistor, the fourteenth resistor, the sixteenth resistor, and the thirteenth capacitor is connected to the common terminal of the first inductor and the third capacitor.
[0113] The cathode of the optocoupler is connected to the other end of the fourteenth resistor, one end of the tenth capacitor, one end of the eleventh capacitor, one end of the twelfth capacitor, and the cathode of the thyristor; the other ends of the tenth capacitor and the eleventh capacitor are connected to one end of the fifteenth resistor; the other end of the fifteenth resistor is interconnected with the other end of the sixteenth resistor, the other end of the twelfth capacitor, one end of the seventeenth resistor, and the control electrode of the thyristor; the anode of the thyristor, the other end of the seventeenth resistor, and the other end of the thirteenth capacitor are grounded.
[0114] The above description is only an optional embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.
Claims
1. A peak current control circuit, applied to a two-transistor forward power circuit, the two-transistor forward power circuit comprising a set of upper switching transistors and a set of lower switching transistors, characterized in that, The peak current control circuit includes a digital controller, a digital-to-analog converter, a dual-channel sampling and comparison circuit, and a dual-channel trigger logic circuit. The digital controller receives the isolation voltage sampling signal output by the dual-transistor forward power circuit at its input terminal. The first output terminal of the digital controller is connected to the input terminal of the digital-to-analog converter circuit. The second and third output terminals of the digital controller are respectively connected to the first and second clock terminals of the dual-channel trigger logic circuit. The output terminal of the digital-to-analog converter circuit is connected to the first and third input terminals of the dual-channel sampling comparator circuit. The second and fourth input terminals of the dual-channel sampling comparator circuit sample the current signals of the upper and lower switching transistors, respectively. The first and second output terminals of the dual-channel sampling comparator circuit are respectively connected to the first and second reset terminals of the dual-channel trigger logic circuit. The first and second output terminals of the dual-channel trigger logic circuit are respectively connected to the driving circuits of the upper and lower switching transistors. The digital controller is used to generate a pulse width modulation signal based on the isolation voltage sampling signal and output two clock signals. The digital-to-analog converter circuit is used to convert the pulse width modulation signal into a reference current signal through active filtering and ripple suppression. The dual-channel sampling and comparison circuit is used to generate a low-level trigger reset signal when the current signal of the switching transistor exceeds the reference current signal. The dual-path trigger logic circuit is used to turn on the switch transistor on the rising edge of the clock signal, turn off the switch transistor when the trigger reset signal is low, and turn off the switch transistor on the falling edge of the clock signal when the trigger reset signal is high.
2. The peak current control circuit as described in claim 1, characterized in that, The digital-to-analog conversion circuit includes an inverter circuit and an active filter circuit; The input terminal of the inverter circuit is connected to the first output terminal of the digital controller, the output terminal of the inverter circuit is connected to the input terminal of the active filter circuit, and the output terminal of the active filter circuit is connected to the first and third input terminals of the dual-channel sampling comparison circuit.
3. The peak current control circuit as described in claim 2, characterized in that, The inverter circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh diode, an eighth diode, a first inverter, and a second inverter; The first resistor and the second resistor are connected in parallel. One end of the first resistor is connected to the first output terminal of the digital controller, and the other end is connected to the input terminal of the first inverter. The positive terminal of the seventh diode and the negative terminal of the eighth diode are connected to the input terminal of the first inverter. The negative terminal of the seventh diode is connected to a power supply, and the positive terminal of the eighth diode is grounded. One end of the third resistor and one end of the fourth capacitor are connected to the input terminal of the first inverter, and the other end of the third resistor and the other end of the fourth capacitor are grounded. The output terminal of the first inverter is connected to the input terminal of the second inverter and one end of the fourth resistor, and the output terminal of the second inverter is connected to the input terminal of the active filter circuit via the fifth resistor; The other end of the fourth resistor is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the input terminal of the active filter circuit and one end of the sixth capacitor, and the other end of the sixth capacitor is grounded.
4. The peak current control circuit as described in claim 3, characterized in that, The active filter circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a seventh capacitor, an eighth capacitor, and a first operational amplifier; One end of the sixth resistor is connected to the output terminal of the inverter circuit, the other end of the sixth resistor is connected to one end of the seventh resistor and one end of the seventh capacitor, and the other end of the seventh resistor is connected to the positive input terminal of the first operational amplifier. The eighth resistor and the eighth capacitor are connected in parallel, with one end connected to the positive input terminal of the first operational amplifier and the other end grounded; the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier and the other end of the seventh capacitor. The output terminal of the first operational amplifier is connected to the first input terminal and the third input terminal of the dual-channel sampling and comparison circuit.
5. The peak current control circuit as described in claim 1, characterized in that, The dual-channel sampling comparison circuit includes two sets of sampling comparison circuits; The first input terminal and the second input terminal of one set of the sampling comparison circuits are respectively the first input terminal and the second input terminal of the dual-channel sampling comparison circuit, and the output terminal of one set of the sampling comparison circuits is the first output terminal of the dual-channel sampling comparison circuit; The first and second input terminals of the other set of sampling comparison circuits are respectively the third and fourth input terminals of the dual-channel sampling comparison circuit, and the output terminal of the other set of sampling comparison circuits is the second output terminal of the dual-channel sampling comparison circuit.
6. The peak current control circuit as described in claim 5, characterized in that, The sampling and comparison circuit includes a DC pulse transformer, a ninth resistor, a tenth resistor, an eleventh resistor, a ninth diode, a tenth diode, an eleventh diode, a ninth capacitor, an emitter follower, and a comparator. One end of the main coil of the DC pulse transformer is the second input terminal of the sampling comparison circuit. The other end of the main coil is connected to the intermediate bus or grounded. One end of the secondary coil of the DC pulse transformer is connected to the positive terminal of the ninth diode. The negative terminal of the ninth diode is connected to one end of the ninth resistor, one end of the tenth resistor, and one end of the eleventh resistor. The other end of the secondary coil, the other end of the ninth resistor, and the other end of the tenth resistor are grounded. The other end of the eleventh resistor is connected to the positive input terminal of the emitter follower, the positive terminal of the tenth diode, the negative terminal of the eleventh diode, and one end of the ninth capacitor. The negative terminal of the tenth diode is connected to a power source, the positive terminal of the eleventh diode is grounded, and the other end of the ninth capacitor is grounded. The output terminal of the emitter follower is connected to the negative input terminal of the emitter follower and the negative input terminal of the comparator. The positive input terminal of the comparator is the first input terminal of the sampling comparison circuit, and the output terminal of the comparator is the output terminal of the sampling comparison circuit.
7. The peak current control circuit as described in claim 1, characterized in that, The dual-path triggering logic circuit includes two sets of flip-flops and AND gates; The clock port of one group of the flip-flops and the first input of one group of the AND gates are both connected to the second output of the digital controller. The reset port of one group of the flip-flops is connected to the first output of the dual-channel sampling comparison circuit. The output port of one group of the flip-flops is connected to the second input of one group of the AND gates. The output of one group of the AND gates is connected to the driving circuit of the upper switching transistor. The clock port of the other set of flip-flops and the first input of the other set of AND gates are both connected to the third output of the digital controller. The reset port of the other set of flip-flops is connected to the second output of the dual-channel sampling comparison circuit. The output port of the other set of flip-flops is connected to the second input of the other set of AND gates. The output of the other set of AND gates is connected to the driving circuit of the lower switching transistor.
8. A switching power supply device, characterized in that, The switching power supply device includes a dual-transistor forward power circuit and a peak current control circuit as described in any one of claims 1-7, wherein the dual-transistor forward power circuit and the peak current control circuit are electrically connected.
9. The switching power supply device as described in claim 8, characterized in that, The dual-transistor forward power circuit includes a first capacitor, a second capacitor, a third capacitor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first inductor, a first upper switch transistor, a second upper switch transistor, a first lower switch transistor, a second lower switch transistor, a high-frequency transformer, and an isolation circuit. The first capacitor and the second capacitor are connected in series at both ends of the bus. The middle node of the first capacitor and the second capacitor is connected to the positive terminal of the first diode, the negative terminal of the fourth diode, the source of the second upper switch, and the drain of the first lower switch. The drain of the first upper switch transistor and the cathode of the second diode are connected to one end of the bus, and the source of the first upper switch transistor is connected to the cathode of the first diode and the same-name terminal of the primary winding of the high-frequency transformer. The drain of the second upper switch is connected to the anode of the second diode and the opposite terminal of the primary winding of the high-frequency transformer; the source of the second upper switch is connected to the second input terminal of the dual-channel sampling comparison circuit of the peak current control circuit; the gates of the first upper switch and the second upper switch are connected to the driving circuit of the upper switch. The source of the first lower switch is connected to the negative terminal of the third diode and the same terminal of the primary winding of the high-frequency transformer, and the positive terminal of the third diode is connected to the other end of the bus. The drain of the second lower switch is connected to the anode of the fourth diode and the opposite terminal of the second winding of the primary side of the high-frequency transformer; the source of the second lower switch is connected to the other end of the bus and the fourth input terminal of the dual-channel sampling and comparison circuit; the gates of the first lower switch and the second lower switch are connected to the driving circuit of the lower switch. The same-name terminal of the first secondary winding of the high-frequency transformer is connected to the positive terminal of the fifth diode and the same-name terminal of the second secondary winding; the negative terminal of the fifth diode is connected to the negative terminal of the sixth diode and one end of the first inductor; the other end of the first inductor is connected to one end of the third capacitor and the input terminal of the isolation circuit; the output terminal of the isolation circuit is connected to the input terminal of the digital controller of the peak current control circuit. The opposite terminal of the first secondary winding of the high-frequency transformer is connected to the opposite terminal of the second secondary winding, the positive terminal of the sixth diode, and the other end of the third capacitor.