Damage detection circuit

Abstract

This utility model discloses a wire damage detection circuit, comprising a signal acquisition unit, a frequency conversion unit, a phase-locked loop (PLL) processing unit, a signal output unit, and a main control unit. The acquisition unit introduces the capacitance change between the isolation tool and the wire core into the circuit via a shielded single-core cable; an inverting oscillator-adjustable digital potentiometer network converts the capacitance difference into a frequency signal; the PLL performs phase comparison on this signal and outputs a linear analog voltage; the signal output unit amplifies, performs threshold comparison, and drives the signal to achieve visual alarm of the wire damage status and MCU quantization sampling. This circuit features high sensitivity, compact structure, low cost, and adaptive calibration and software filtering functions, enabling real-time detection of contact damage under high-speed wire stripping conditions.

Description

Technical Field

[0001] This application relates to the field of cable testing technology, and in particular to a damaged cable detection circuit. Background Technology

[0002] The wire stripping process is located at the beginning of the wire harness processing chain, and its quality directly affects the subsequent crimping, welding, and even the electrical reliability of the entire machine. Currently, the detection of damaged wires after stripping mainly relies on manual visual inspection and machine vision inspection. Manual visual inspection requires operators to check each wire one by one with a magnifying glass, which is labor-intensive, has limited cycle time, and is prone to fatigue and missed detections. Machine vision inspection relies on high-definition cameras, constant illumination light sources, and precision motion platforms, which are costly, complex to debug, occupy a large space, and are sensitive to working conditions such as oil stains, color differences, and shadows, and still have problems with misjudgment and maintenance costs. With the increasing requirements for wire harness reliability in industries such as new energy vehicles and high-speed communications, the shortcomings of traditional solutions in terms of efficiency, cost, scalability, and miniaturization are becoming increasingly prominent. Especially under the high-speed cycle of automated wire stripping machines, how to capture the micron-level contact state between the blade and the wire core in a limited space in real time and without contact, and stably map it into an electrical signal that can be quickly judged by the MCU, has become a key problem restricting the improvement of production line yield. This invention addresses the aforementioned pain points by proposing an integrated detection circuit based on capacitive sensing-phase-locked loop conversion. Without increasing mechanical complexity, it achieves high-speed, high-sensitivity, and low-cost online monitoring of damaged wires, injecting new intelligent vitality into wire harness manufacturing.

[0003] Currently, in the cable harness industry, cable stripping is mostly performed using visual optical inspection or manual optical inspection. Visual optical inspection requires manufacturers to have sophisticated equipment, such as high-definition cameras, adjustable precision light sources, and auxiliary motion mechanisms, making it relatively costly and structurally complex. Manual optical inspection, on the other hand, requires sequentially examining the cable cores under an optical microscope, which is tiring for personnel and relatively inefficient. Existing solutions collect capacitance difference signals caused by changes in the contact distance between the cable and the cutting tool. These capacitance difference signals are then converted into frequency difference and analog signals by a subsequent driver chip. After data processing by an MCU, filtering and algorithmic calculations are performed to obtain relatively reliable signal data to confirm whether the cable cores are damaged. This method requires high precision in image, camera, and light source parameters and has a certain degree of false alarms. Manual optical inspection, however, requires long-term operation by specialized personnel, making it relatively time-consuming and inefficient. Summary of the Invention

[0004] This application provides a filament detection circuit that effectively improves the sensitivity and accuracy of filament detection through the following innovations.

[0005] To achieve the above objectives, this application proposes a wire damage detection circuit, comprising:

[0006] The system comprises a signal acquisition unit, a frequency conversion unit, a phase-locked loop (PLL) processing unit, a signal output unit, and a main control unit. The signal acquisition unit is connected between the cable under test and the isolation tool via a shielded single-core cable to form a capacitive induction. The frequency conversion unit converts the capacitance change into a frequency signal output. The PLL processing unit receives the frequency signal and converts it into an analog voltage signal. The signal output unit receives the analog voltage signal and feeds it back to the main control unit.

[0007] In one embodiment, the signal acquisition unit includes an SMA connector, an EMC protection device, and a DC current-limiting resistor to achieve stability and protection of the input signal.

[0008] In one embodiment, the frequency conversion unit includes an inverting oscillation circuit, a digital potentiometer, and an inverting chip. The digital potentiometer is connected in a bridge series-parallel configuration and is used to adjust the feedback resistance value.

[0009] In one embodiment, the digital potentiometer is connected to the main control unit via an SPI communication signal to achieve dynamic adjustment of the resistance value.

[0010] In one embodiment, the phase-locked processing unit includes a phase-locked chip, a voltage-controlled oscillator, and an external low-pass filter to perform frequency-to-analog voltage conversion.

[0011] In one embodiment, the external low-pass filter includes a resistor and a capacitor for filtering out high-frequency interference signals.

[0012] In one embodiment, the signal output unit includes an in-phase amplifier circuit, a comparator circuit, and a drive circuit, used to indicate whether the cable core is damaged.

[0013] In one embodiment, the driving circuit includes a transistor, a current-limiting resistor, and a reverse freewheeling diode for driving a status indicator LED.

[0014] In one embodiment, a voltage follower circuit is also included to buffer the input signal, increase the drive current, and enhance the ADC detection accuracy of the back-end main control unit.

[0015] In one embodiment, the main control unit is an MCU, which has data acquisition, signal processing and software filtering algorithm functions, and is used to realize automatic correction and adaptive parameter adjustment of cable detection.

[0016] The cable stripping damage detection circuit of this utility model has the following technical effects:

[0017] By employing a capacitance induction-inverting oscillation-phase-locked loop detection link, the minute capacitance changes between the tool and the wire core are converted into analog voltage signals in real time and linearly, effectively improving the sensitivity and accuracy of wire damage detection.

[0018] A dual-channel digital potentiometer series-parallel adjustable network is introduced, with a resistance adjustment range of 0kΩ-100kΩ and a minimum resolution of no more than 0.1%. It can perform rapid adaptive calibration for different wire diameters, dielectrics and stripping depths.

[0019] After being amplified in phase and processed by comparison threshold, the phase-locked loop output can generate an alarm signal within ≤3ms, meeting the online detection requirements under high-speed wire stripping conditions of ≥60 times / minute.

[0020] The overall power consumption of the circuit is ≤1W, and all components are in general surface mount packages. It can be directly integrated into the control board of existing wire stripping equipment without the need for optical components, which significantly reduces the complexity of the system structure and the cost of BOM.

[0021] Compared with traditional visual inspection solutions, this circuit can reduce initial investment costs by about 70%, significantly reduce maintenance time, and improve the overall yield of the production line to over 99% in the long term.

[0022] By combining MCU-side filtering and self-calibration algorithms, this circuit can operate stably under different ambient temperatures, humidity levels, and operating cycles, with a false alarm rate of ≤1%, ensuring product consistency and reliability. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the functional framework of the wire damage detection circuit in this application;

[0027] Figure 2 This is a circuit schematic diagram showing the communication interface and data interaction interface between the wire damage detection circuit and the MCU in this application.

[0028] Figure 3 The schematic diagram of the digital potentiometer adjustment network and SPI communication branch of the wire damage detection circuit in this application is shown.

[0029] Figure 4 This is a schematic diagram of the inverting oscillation circuit of the wire damage detection circuit in this application;

[0030] Figure 5This is a schematic diagram of the analog signal amplification, threshold comparison, and LED indicator circuit of the wire damage detection circuit in this application.

[0031] Figure 6 This is a schematic diagram of the phase-locked processing unit and analog signal output unit of the wire damage detection circuit in this application.

[0032] Figure 7 This is a schematic diagram of the mirrored digital potentiometer adjustment network and SPI communication branch of the wire damage detection circuit in this application.

[0033] Figure 8 This is a schematic diagram of the mirror-image inverted oscillation and signal acquisition interface circuit of the wire damage detection circuit in this application;

[0034] Figure 9 This is a schematic diagram of the mirror analog signal amplification, threshold comparison, and LED indicator circuit of the wire damage detection circuit in this application.

[0035] Figure 10 This is a schematic diagram of the mirror phase-locked processing unit and analog signal output unit of the wire damage detection circuit in this application.

[0036] The above figures are all arranged in functional modules, using module schematics or enlarged partial diagrams to illustrate the connection relationships between each unit. Figures 2-10 These correspond to the key circuit structures for signal acquisition, frequency conversion, signal processing, and two parallel detection links, respectively.

[0037] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0038] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0039] This application provides a wire damage detection circuit; please refer to [link / reference]. Figure 1 The provided functional framework diagram of the suture detection circuit.

[0040] As shown in Figure 1, the circuit consists of five functional units: the signal acquisition unit 101 couples the capacitance change between the isolation tool and the wire core to the circuit input terminal through a shielded single-core cable, and completes the pre-stage protection through EMC protection devices and current-limiting resistors; the frequency conversion unit 102 uses an RC inverting oscillation network and a programmable digital potentiometer to convert the small capacitance variable into the corresponding oscillation frequency signal in real time; the phase-locked loop processing unit 103 performs phase comparison on the frequency signal and outputs a linear analog voltage through a voltage-controlled oscillator to provide a reference for subsequent amplification and thresholding; the signal output unit 104 includes a non-inverting amplifier, a comparator, and an LED driver circuit, which performs gain conditioning, threshold determination, and outputs a visual alarm signal for the analog voltage; the main control unit 105 uses a microcontroller to perform ADC sampling and filtering operations on the analog quantity, and dynamically adjusts the digital potentiometer through the SPI bus to realize automatic calibration, adaptive compensation, and communication reporting functions.

[0041] To further facilitate understanding of the application of the present invention, the following supplementary explanations of the three embodiments are provided in conjunction with specific implementation scenarios, respectively demonstrating the application details and implementation logic of the technical solutions of the present invention in different deployment environments.

[0042] This embodiment provides a wire damage detection circuit suitable for automatic wire stripping equipment, focusing on the signal acquisition unit and its integration with the whole machine.

[0043] Figure 2 The diagram shows a top-down view of the signal acquisition unit and external interface circuitry, with the SMA / BNC signal input interface J301 at the center. The interface housing is reliably grounded to the equipment's metal frame via dedicated solder joints, and a pressure spring is used to ensure shielding continuity, effectively suppressing external common-mode interference. The core wire is connected to the inner wall of the isolation tool via a Teflon-insulated conductor, ensuring mechanical reliability and insulation performance. The EMC protection network consists of a high-frequency bypass capacitor C311 (capacity determined by actual design, commonly 1000pF), a series current-limiting resistor R336 (1MΩ), and an ESD protection diode D301 connected in parallel between the signal line and ground. These three components work together to suppress external surges and radio frequency interference, improving the input port's anti-interference and electrostatic protection capabilities. The signal line enters the inverting oscillation unit after passing through R331 (a 0Ω jumper, used only for direct signal connection, without actual current limiting or discharge function). This structure ensures that external radio frequency interference and electrostatic pulses are effectively suppressed, allowing the input signal to enter the subsequent detection stage with good integrity.

[0044] During the stripping process of the cable under test, a capacitance Cvar is formed between the exposed conductor and the isolation blade. If the cable core comes into contact with the blade, it can cause reverse oscillation failure or output frequency changes. The signal acquisition unit consists of a J301SMA connector, an EMC protection network, and a DC current-limiting resistor R331. The SMA connector shell is welded to the metal frame of the equipment and serves as a reference ground. A 360° crimp spring ensures the continuity of the shielding layer and suppresses common-mode interference. The signal core wire is connected to the inner wall of the blade via a Teflon-insulated conductor, ensuring temperature resistance and bending life.

[0045] To suppress radio frequency and electrostatic discharge (ESD) pulses, a C311 (1000pF) is first connected in parallel to ground on the core wire to form a high-frequency bypass; then an R336 (1MΩ) is connected in parallel to limit peak current; and an ESD diode D301 is connected in parallel between the core wire and ground to clamp ESD surges. R331 is a 0Ω jumper, used only for direct signal connection. These components together provide EMC and ESD protection for the input signal, improving the system's immunity to interference.

[0046] In the frequency conversion unit, Cvar, along with R324, R329, R330, R333, and dual-channel digital potentiometers U301 and U302, constitute an RC anti-phase oscillation network. U301 and U302 are 8-bit resolution digital potentiometers with 255 taps per channel and a minimum step of 392Ω. The two cores are first connected in series and then in parallel, achieving a 0.1% resolution for the equivalent resistance within the range of 0kΩ–100kΩ. The center oscillation frequency f0 ≈ 1 / (2πR_eq·C_eq), where C_eq is the parallel capacitance between C305 and Cvar. A 1pF change in Cvar causes approximately a 45kHz frequency shift.

[0047] The phase-locked loop (PLL) processing unit U303 adopts a PFD+VCO architecture, converting the oscillation frequency into an analog control voltage Vout. After filtering by R325 / C308, the voltage is input to the non-inverting amplifier U305A and sampled by the MCU's ADC. The system is powered by 3.3V and isolated from device ground through a multi-point star topology. The PCB trace impedance is controlled at 50Ω to ensure that the phase noise is below −80dBc / Hz@1kHz offset. Experiments show that when the contact depth between the tool and the wire core is 5µm, Cvar increases by approximately 1.8pF, corresponding to a 0.85V increase in Vout. The MCU can distinguish contact changes at the 1µm level with 12-bit resolution.

[0048] This signal acquisition unit uses only general-purpose SMD capacitors, resistors, and TVS diodes, requiring no optical components or mechanical displacement parts, resulting in low incremental cost of the entire unit's BOM.

[0049] Example 2

[0050] This embodiment is based on the above. Figure 1 Based on the architecture, a complete implementation of frequency conversion, digital adjustment, phase-locked loop processing, signal output, buffer amplification and main control is further provided.

[0051] Figure 2 This diagram illustrates the interface and data interaction principle between the wire damage detection circuit and the main control MCU. It includes the power input (24VIN), multiple grounds (DGND / GND / PE), power distribution, the FPC interface, and several output terminals. These cover SPI bus signals such as SPI2_MOSI, SPI2_SCK, and SPI2_CS0, analog signal inputs such as IN_ADC0 / 1, and connections to other MCU peripherals. Each interface, in conjunction with subsequent functional modules, achieves a complete closed loop for data, control, and status signals.

[0052] (a) Frequency conversion unit, see Figure 4 After the capacitor under test, Cvar, is connected in parallel with the static capacitor, C305, a bridge series-parallel digital potentiometer network is introduced. Figure 3 (As shown).

[0053] The network consists of two 8-bit digital potentiometers, U301 and U302: the P0W terminal of U301 is connected in series with the P1B terminal of U302, and the P0B terminal is connected in parallel with the P1W terminal. The output terminal is connected to the input terminal of inverter U304 via R329 (220Ω) and R333 (11kΩ), forming a variable feedback resistance value Req. Simulation results show that the Req adjustment step is 0.097%, and the frequency sensitivity df / dR is not less than 0.35 kHz / Ω, which can meet the 0.5 µm contact depth resolution requirement.

[0054] (ii) Dynamic adjustment of digital potentiometer, see [link / reference] Figure 3

[0055] The MCU's SPI2 port is connected to the CS, SCK, MOSI, and MISO pins of U301 / 302 via pull-up resistors R317 (3.3K), R318 (3.3K), R319 (3.3K), R320 (3.3K), and R321 (3.3K) respectively. The clock speed is 15 MHz, and the command "0XXXh" takes effect within 3 µs after being written to the register. This process does not interfere with the main loop interrupt, ensuring system real-time performance.

[0056] (iii) Phase-locked loop processing unit, see Figure 6

[0057] U303 is a monolithic phase-locked loop. PCA_in receives f_sig, and the output pulse of the internal PFD is filtered by a second-order low-pass filter through R326 (0Ω) / R327 (2K) / C304 (1nF). Vctrl controls VCO_in.

[0058] U303 is a phase-locked loop (PLL) IC (MC14046BDWR2G). Its VCO input (pin 9, L_VCOin) is grounded after being filtered by C309 (100pF) and is also connected to the external signal input. Pin 16 of the chip is VDD, and pin 16 is grounded after decoupling by C303 (100nF). Pin 13 of PC2out is connected to L_VCOin through a network of R326 (0Ω), R327 (2KΩ), and C304 (1uF), and pulled down to ground by R328 (10KΩ) and R332 (10KΩ). Pins 5, 6, and 7 of U303 are connected to ground by C306 (220pF) to realize basic functions such as phase-locking and frequency discrimination. This part realizes frequency locking and discrimination processing of input signals.

[0059] (iv) Low-pass filter design, see Figure 6 (Including MC14046B phase-locked loop)

[0060] The phase-locked loop U303 (MC14046BDWR2G) and its peripheral RC filter and signal output circuit are used. VCO in (pin 9) is filtered to ground via C309 (100pF). The PC2 out (pin 13) signal is connected in series and parallel via an RC low-pass network consisting of R326 (0Ω), R327 (2KΩ), and C304 (1uF). VDD (pin 16) is decoupled via C303 (100nF). R328 (10kΩ) and R332 (10kΩ) are used for pull-down. The analog signal, after being filtered by the LPF, is sent to the subsequent amplifier or ADC for acquisition, according to the circuit structure.

[0061] (v) Signal output unit, see Figure 5

[0062] PC2_out is output to MCU ADC1_CH0 after being amplified by non-inverting amplifier U306A (gain 5); the same signal is reserved and buffered by voltage follower U306B, and can be reserved as input to MCU ADC1_CH0. PC2_out is output to voltage comparator U305B after being amplified by non-inverting voltage follower U305A (gain 5). The comparison threshold is generated by voltage divider R347 (1kΩ) / R348 (1kΩ) / R345 (1kΩ) to generate a 1.5V reference. When U305B outputs a high level, it indicates that the tool wire core is in contact and the alarm state is switched.

[0063] Figure 5The U306A / B branch structure below is similar to that described above. Finally, the L_VCOin signal is filtered and amplified to output the L_ADC_IN signal to the subsequent ADC acquisition stage. C315 (100nF) is used for power supply decoupling and filtering.

[0064] (vi) Drive circuit structure, see Figure 5

[0065] U305A, U305B, U306A, and U306B are LM358 operational amplifiers. Taking U305A as an example, the input terminal is connected via R340 (0Ω) and R342 (0Ω), the feedback terminal is connected in parallel with R349 (5.1K), and the filter capacitor C313 (100nF) is connected to ground. The output of U305A is low-pass filtered by R345 (1K) and C314 (10uF) and connected to the positive input terminal of U305B. The negative terminal of U305B is connected in series with R347 (2K) and R348 (330Ω) to the 5V power supply. The output of U305B is connected to L_OUT through R343 (3K), and then controls the LED through Q301 (transistor 2N3904) and D303 (1N4148SWT) freewheeling diode.

[0066] Specifically, the output of U305B drives NPN transistor Q301 via R343 (3kΩ). The collector of Q301 is connected in series with current-limiting resistor R339 (3kΩ) to the positive terminal of indicator LED D302, and the emitter is grounded. D303 is a reverse freewheeling diode, which absorbs transient voltage in the LED inductor circuit when Q301 is turned off, protecting the device. The LED indicator is red to distinguish between normal and damaged wire conditions.

[0067] (vii) Voltage follower circuit, see Figure 5 The operational amplifier U306B adopts a rail-to-rail structure with a non-inverting input PC2_out, configured in unity-gain mode, and an output drive capability of 30mA. This structure ensures signal integrity under high-impedance measurement environments and is compatible with different cables and different phase-locked loop output level conditions. Therefore, analog quantities of phase-locked loop outputs can be output in non-inverting mode or amplified in non-inverting mode.

[0068] (viii) Main control unit functions: The MCU selected is the NXP MIMXRT1052CVL5B with an ARM Cortex-M7 core and a main frequency of 528 MHz. This controller integrates a 12-bit successive approximation ADC, a DMA controller, and industrial interfaces such as RS-485 and CAN. The system uses the on-chip ADC to continuously sample the phase-locked loop processing unit PC2_out. The DMA automatically moves the data to the buffer. The core completes digital filtering, threshold determination, and compensation algorithms, and reports the detection results in real time through the fieldbus. The main control firmware adopts a three-state machine (safety, early warning, alarm) management and supports online threshold adjustment to meet the real-time closed-loop control requirements under high-speed wire stripping conditions.

[0069] Figure 3 The digital potentiometer is connected to the SPI bus and a bridge series-parallel network, which directly realizes adjustable feedback resistance and dynamic adjustment function. Figure 4 Given the anti-phase oscillating core RC network, and... Figure 3 Together they constitute the frequency conversion unit; Figure 6 R326 / R327 / C304 in the phase-locked loop shown is the LPF; Figure 5 The exhibition focuses on in-phase amplifiers, comparators, and drivers. Figure 1 Draw the interfaces between the MCU and each function block to illustrate the software filtering and self-calibration paths; Figures 7-10 It is a dual-channel mirror structure, and Figures 3-6 The function corresponds to the requirements and is used in multi-line parallel detection scenarios.

[0070] This application provides a wire damage detection circuit that addresses the limitations of traditional visual inspection in terms of cost, size, and environmental adaptability. It proposes a novel approach that utilizes the capacitance difference between the tool and the wire core as a detection signal. Through a three-stage conversion of capacitance, frequency, and voltage, it achieves rapid online identification of wire damage.

[0071] The overall circuit can be divided into a signal acquisition area, a frequency conversion area, a phase-locked loop (PLL) analysis area, an analog output and thresholding area, and a main control algorithm area. The signal acquisition area requires high anti-interference capability; the frequency conversion area needs to provide wide dynamic range adjustability; the PLL analysis area focuses on output linearity; the thresholding area balances intuitive indication with MCU quantization; and the main control algorithm area is responsible for initialization calibration, software filtering detection, and long-term adaptive operation.

[0072] The sampling terminal uses a 50 Ω SMA connector with a 100 pF high-frequency filter capacitor and a 33 Ω series resistor; the inverting oscillator uses a CMOS inverter (propagation delay 10 ns) and two 8-bit digital potentiometers to achieve a programmable feedback resistance value of 0 kΩ-100 kΩ; the phase-locked loop uses a PFD+VCO chip with loop filter parameters of 3 kΩ / 1 μF; the non-inverting amplifier and follower use a rail-to-rail amplifier with a gain of 1 and a full-scale output of 0-3.2V; the comparator threshold is set to 1.5 V; the LED is driven by an NPN transistor, a current-limiting resistor, and a reverse diode, with a response time of less than 3 ms.

[0073] Signal chain principle: Change in the capacitance under test (Cvar) → RC network oscillation frequency drift → PFD phase error → low-pass filter → linear output of control voltage Vctrl → op-amp amplification / follower → ADC quantization or comparator thresholding → LED / communication alarm. This allows for a detection cycle to be completed in <3ms.

[0074] EMC and Reliability: The sampling end adopts a fully shielded layout with a short grounding path and single-point grounding; the PCB traces use 50Ω microstrip to prevent impedance discontinuities; the system passes the IEC61000-4-2 ±15kV electrostatic discharge test and the IEC61000-4-42kV electrical fast pulse test; the MTTF of key components is >100kh.

[0075] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0076] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0077] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A fault line detection circuit, characterized by comprising: include: The system comprises a signal acquisition unit, a frequency conversion unit, a phase-locked loop (PLL) processing unit, a signal output unit, and a main control unit. The signal acquisition unit is connected between the cable under test and the isolation tool via a shielded single-core cable to form a capacitive induction. The frequency conversion unit converts the capacitance change into a frequency signal output. The PLL processing unit receives the frequency signal and converts it into an analog voltage signal. The signal output unit receives the analog voltage signal and feeds it back to the main control unit.

2. The circuit according to claim 1, characterized in that, The signal acquisition unit includes an SMA connector, EMC protection devices, and a DC current-limiting resistor, which are used to stabilize and protect the input signal.

3. The circuit according to claim 1, characterized in that, The frequency conversion unit includes an inverting oscillation circuit, a digital potentiometer, and an inverting chip. The digital potentiometer is a bridge-type series-parallel connection used to adjust the feedback resistance value.

4. The circuit according to claim 3, characterized in that, The digital potentiometer is connected to the main control unit via SPI communication signal to realize dynamic adjustment of the resistance value.

5. The circuit according to claim 1, characterized in that, The phase-locked processing unit includes a phase-locked chip, a voltage-controlled oscillator, and an external low-pass filter, which performs frequency-to-analog voltage conversion.

6. The circuit according to claim 5, characterized in that, The external low-pass filter includes resistors and capacitors and is used to filter out high-frequency interference signals.

7. The circuit according to claim 1, characterized in that, The signal output unit includes an in-phase amplifier circuit, a comparator circuit, and a driver circuit, used to indicate whether the cable core is damaged.

8. The circuit according to claim 7, characterized in that, The driving circuit includes a transistor, a current-limiting resistor, and a reverse freewheeling diode, used to drive the status indicator LED.

9. The circuit according to claim 1, characterized in that, It also includes a voltage follower circuit to buffer the input signal, increase the drive current, and enhance the ADC detection accuracy of the back-end main control unit.

10. The circuit according to claim 1, characterized in that, The main control unit is an MCU, which has data acquisition, signal processing and software filtering algorithm functions, and is used to realize automatic correction and adaptive parameter adjustment of cable detection.

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