A modular building gateway device supporting intelligent multi-protocol conversion

Abstract

This utility model belongs to the field of building intelligence technology and discloses a modular building gateway device supporting multi-protocol intelligent conversion. The device includes a core board module, an RS485 interface module, an Ethernet interface module, a USB interface module, and a power supply module. The RS485 interface module, Ethernet interface module, USB interface module, and power supply module are connected to the core board module. This utility model solves the technical bottlenecks of existing building gateways in terms of multi-protocol compatibility, configuration efficiency, and real-time performance. It breaks through protocol barriers and eliminates protocol obstacles for interconnecting heterogeneous devices; improves configuration and maintenance efficiency; adopts a multi-level isolation design to ensure communication stability in complex electromagnetic environments; and controls the conversion latency to within 50ms through hardware-accelerated protocol conversion, meeting real-time control requirements.

Description

Technical Field

[0001] This utility model relates to the field of building intelligence technology, and in particular to a modular building gateway device that supports multi-protocol intelligent conversion. Background Technology

[0002] In the fields of smart buildings and industrial IoT, building automation systems (BAS) need to integrate heterogeneous devices such as HVAC (Heating, Ventilation and Air Conditioning), lighting, and security systems. These devices typically use heterogeneous protocols such as BACnet and Modbus, resulting in significant protocol barriers between systems. Existing protocol conversion solutions for building gateways have the following drawbacks:

[0003] 1. Insufficient protocol compatibility: Traditional gateways mostly only support single protocol conversion (such as Modbus RTU). ModbusTCP cannot achieve cross-protocol conversion (such as Modbus RTU). The lack of a unified bridge between industrial protocols (such as BACnetMS / TP) and IT protocols (such as BACnet IP) necessitates the deployment of additional protocol converters, increasing system complexity.

[0004] 2. Low configuration and maintenance efficiency: Protocol mapping relies on command lines or dedicated configuration tools, requiring professional personnel and resulting in long debugging cycles. Firmware upgrades require disassembling the device for flashing, lacking a localized upgrade solution that can be used with a USB flash drive / USB plug-and-play.

[0005] 3. Real-time and reliability issues: Data frame parsing delays (>100ms) exist during multi-protocol conversion, making it difficult to meet the real-time requirements of building control systems. Insufficient electrical isolation (e.g., RS485 lacks integrated isolation power supply) leads to poor EMC immunity and low communication stability in industrial scenarios.

[0006] Therefore, how to provide a modular building gateway device that supports intelligent conversion of multiple protocols is an urgent problem to be solved. Utility Model Content

[0007] This utility model provides a modular building gateway device that supports intelligent conversion of multiple protocols, in order to solve the problems of insufficient protocol compatibility, low configuration and maintenance efficiency, and real-time performance and reliability in the prior art.

[0008] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0009] Therefore, the specific technical solution adopted by this utility model is as follows: A modular building gateway device supporting intelligent conversion of multiple protocols, comprising:

[0010] The core board module is used to bring out various communication interface resources through board-to-board connectors and connect to the peripheral circuits of the baseboard through pin connectors;

[0011] The RS485 interface module is used to perform level conversion and electrical isolation of the asynchronous serial communication protocol signals of the core board module, and to release the IO pin resources on the main control side; it also optimizes the impedance matching of the RS485 link and improves the tolerance to electromagnetic interference.

[0012] The Ethernet interface module is used to electrically isolate and impedance match the media-independent interface signals of the core board module, and to connect to external network devices.

[0013] The USB interface module is used for expanding storage and system upgrades, and it also purifies and regulates the power supply, suppresses common-mode interference, and enables lossless transmission of differential-mode signals.

[0014] The power module is used to connect to a DC power supply and filter out common-mode and differential-mode interference from the power input, suppress surge overvoltage, realize voltage conversion, and stabilize the output voltage.

[0015] The RS485 interface module, Ethernet interface module, USB interface module, and power supply module are connected to the core board module.

[0016] Preferably, the core board module includes: a development board processor, a power management integrated circuit, memory, flash memory, and an Ethernet transceiver;

[0017] The development board processor (AM335X processor) is connected in sequence to the power management integrated circuit (PMIC), memory (DDR3), flash memory (NAND Flash), and Ethernet transceiver (Ethernet PHY circuit), and the Ethernet transceiver is connected in sequence to the power management integrated circuit, memory, and flash memory.

[0018] Preferably, the RS485 interface module includes capacitor C1, chip U1, capacitor C2, resistor R1, resistor R2, capacitor C3, resistor R3, chip U7, resistor R4, capacitor C4, resistor R5, resistor R6, resistor R7, pin header J15, diode array Z1, resistor RV2, resistor RV3, resistor R8, MOSFET Q1, and pin header J1.

[0019] Among them, the first terminal of chip U1 is connected to capacitor C1, the eighth terminal of chip U1 is connected to capacitor C2, the seventh terminal of chip U1 is connected to one end of resistor R2, capacitor C3 and one end of resistor R3 in sequence, the other end of resistor R2 is connected to one end of resistor R1, the other end of resistor R1 is connected to chip U7 and the drain of MOSFET in sequence, the sixth terminal of chip U1 is connected to the fourth terminal of chip U7 and one end of resistor R4 in sequence, the other end of resistor R4 is connected to the gate of MOSFET, and the other end of resistor R3 is connected to the first terminal of chip U7.

[0020] The fifth terminal of chip U7 is connected in sequence to the source of MOSFET Q1, one end of resistor R5, the third terminal of diode array Z1, one end of resistor RV2, one end of resistor RV3, and one end of resistor R8. The other end of resistor R8 is connected to the first terminal of pin header J1. The sixth terminal of chip U7 is connected in sequence to one end of resistor R6, one end of resistor R7, the first terminal of diode array Z1, the other end of resistor RV2, and the third terminal of pin header J1. The other end of resistor R7 is connected to the first terminal of pin header J15. The seventh terminal of chip U7 is connected to the other end of resistor R5, the second terminal of pin header J15, the second terminal of diode array Z1, the other end of resistor RV3, and the second terminal of pin header J1. The eighth terminal of chip U7 is connected in sequence to the other end of resistor R6 and capacitor C4.

[0021] Preferably, the Ethernet interface module includes a transformer T2, resistors R57 and R58, capacitors C40, R59, R60, and C30, interface J7, resistors R67, R36, and R68, capacitors C111 and C31, resistors R61, R62, R63, R64, R65, R66, and R37.

[0022] Specifically, the first terminal of transformer T2 is connected to one end of resistor R57, the other end of resistor R57 is connected in sequence to one end of resistor R58 and capacitor C40, the other end of resistor R58 is connected to the third terminal of transformer T2, the sixth terminal of transformer T2 is connected to one end of resistor R59, the other end of resistor R59 is connected in sequence to one end of resistor R60 and capacitor C30, and the other end of resistor R60 is connected to the eighth terminal of transformer T2.

[0023] The sixteenth, fourteenth, eleventh, and ninth terminals of transformer T2 are connected to the first, second, third, and sixth terminals of interface J7 in sequence. The ninth terminal of connector J7 is connected to one end of resistor R67, the other end of resistor R67 is connected to one end of resistor R68, resistor R36 is connected to the tenth terminal of interface J7, the other end of resistor R68 is connected to the eleventh terminal of interface J7, and the twelfth terminal of interface J7 is connected to resistor R37.

[0024] One end of capacitor C111 is connected to one end of capacitor C31. The other end of capacitor C31 is connected in sequence to one end of resistor R61, one end of resistor R62, one end of resistor R63, one end of resistor R64, one end of resistor R65, and one end of resistor R66. The other ends of resistors R61, R62, R63, R64, R65, and R66 are respectively connected to different pins of interface J7.

[0025] Preferably, the USB interface module includes: a current limiting switch U13, capacitors C19 and C20, resistors R130 and R132, capacitors C33 and C21, resistors R18 and C12, capacitors C13, a USB_A terminal J14, a common-mode filter L1, and a chip U5.

[0026] Specifically, the second and third terminals of the current limiting switch U13 are connected sequentially to one end of capacitor C20 and one end of capacitor C19. The other end of capacitor C20 is connected sequentially to the other end of capacitor C19 and one end of resistor R130. The other end of resistor R130 is connected to the fourth terminal of the current limiting switch U13. The fifth terminal of the current limiting switch U13 is connected to resistor R132. The sixth, seventh, and eighth terminals of the current limiting switch U13 are connected sequentially to one end of capacitor C33, one end of capacitor C21, one end of resistor R18, one end of capacitor C12, one end of capacitor C13, and the first terminal of USB_A terminal J14. The other end of capacitor C33 is connected sequentially to the other end of capacitor C21 and the other end of resistor R18. The other end of capacitor C12 is connected to the other end of capacitor C13.

[0027] The second end of the USB_A terminal J14 is connected in sequence to the first end of the common-mode filter L1 and the fourth end of the chip U5, and the third end of the USB_A terminal J14 is connected in sequence to the second end of the common-mode filter L1 and the third end of the chip U5.

[0028] Preferably, the power module includes: pin header J8, fuse F5, capacitor C43, capacitor C44, capacitor C72, resistor RV5, diode TVS10, transformer T1, diode D48, diode D42, diode D50, diode D49, capacitor C63, capacitor C71, capacitor C52, capacitor C69, capacitor C70, resistor R19, resistor R20, capacitor C53, chip U11, capacitor C54, diode D6, resistor R21, resistor R23, inductor L2, resistor R21, resistor R23, capacitor C68, capacitor C67, capacitor C66, capacitor C14, capacitor C48, chip U23, diode D46, capacitor C47, capacitor C61, and resistor R22;

[0029] Specifically, the first end of pin header J8 is connected in sequence to one end of capacitor C43 and one end of capacitor C44; the second end of pin header J8 is connected in sequence to the other end of capacitor C43, one end of capacitor C72, one end of resistor RV5, the second end of diode TVS10, and the first end of transformer T1; the third end of pin header J8 is connected to one end of fuse F5; the other end of fuse F5 is connected in sequence to the other end of capacitor C44, the other end of capacitor C72, the other end of resistor RV5, the first end of diode TVS10, and the second end of transformer T1; the third end of transformer T1 is connected in sequence to the positive terminal of diode D42 and the negative terminal of diode D50; the fourth end of transformer T1 is connected in sequence to the positive terminal of diode D48 and the negative terminal of diode D49; the negative terminal of diode D48 is connected in sequence to the negative terminal of diode D42, one end of capacitor C63, and one end of capacitor C71; and the positive terminal of diode D50 is connected in sequence to the positive terminal of diode D49, the other end of capacitor C63, and the other end of capacitor C71.

[0030] Capacitor C52 is connected in parallel with capacitors C69 and C70, and is connected in sequence to the second terminal of chip U11 and one end of resistor R19. The third terminal of chip U11 is connected to the other end of resistor R19. The fourth terminal of chip U11 is connected to one end of resistor R20. The other end of resistor R20 is connected to one end of capacitor C53. The other end of capacitor C53 is connected to the sixth terminal of chip U11. The first terminal of chip U11 is connected to one end of capacitor C54. The other end of capacitor C54 is connected in sequence to one end of inductor L2, the negative terminal of diode D6, and the eighth terminal of chip U11. The positive terminal of diode D6 is connected in sequence to the seventh and ninth terminals of chip U11 and one end of resistor R23. The other end of resistor R23 is connected in sequence to one end of resistor R21 and the fifth terminal of chip U11. Capacitor C68 is connected in parallel with capacitors C67 and C66, and is connected in sequence to the other end of inductor L2 and the other end of resistor R21.

[0031] Capacitors C14 and C48 are connected in parallel, and the two ends of capacitors C14 and C48 are connected to the third and first ends of chip U23, respectively. The second and fourth ends of chip U23 are connected to one end of capacitor C47, one end of capacitor C61, and the positive terminal of diode D46 in sequence. The negative terminal of diode D46 is connected to one end of resistor R22. The other end of resistor R22 is connected to the other end of capacitor C61 and the other end of capacitor C47 in sequence.

[0032] Preferably, a modular building gateway device supporting intelligent conversion of multiple protocols further includes: a reset circuit module, used to reset the modular building gateway device supporting intelligent conversion of multiple protocols according to the external signal of the switch being pressed. The reset circuit module includes: a resistor R33, a capacitor C11 and a switch SW2.

[0033] One end of resistor R33 is connected to one end of capacitor C11 and the third end of switch SW2 in sequence, and the other end of capacitor C11 is connected to the second end of switch SW2.

[0034] The technical solution provided by this utility model embodiment may include the following beneficial effects:

[0035] (1) This utility model solves the technical bottlenecks of existing building gateways in terms of multi-protocol compatibility, configuration efficiency, and real-time performance. Specifically, it includes: 1. Breaking through protocol barriers: Providing a hardware-scalable gateway architecture, which natively supports bidirectional intelligent conversion of protocols such as BACnet and Modbus through a core board + baseboard design, eliminating protocol barriers to interconnection of heterogeneous devices. 2. Improving configuration and maintenance efficiency: Developing a visual APP configuration tool, which realizes "one-click" operation of protocol mapping and device binding through a graphical interface, reducing the technical threshold. Integrating USB flash drive upgrade function, supporting local firmware updates, avoiding disassembly for maintenance. 3. Enhancing system reliability: Adopting a multi-level isolation design (RS485 optocoupler isolation) to ensure communication stability in complex electromagnetic environments. Through hardware-accelerated protocol conversion (such as direct connection of NAND Flash to GPMC interface), the conversion delay is controlled within 50ms to meet real-time control requirements.

[0036] (2) High-efficiency compatibility with multiple protocols: Supports intelligent conversion between mainstream protocols such as BACnet and Modbus, enabling seamless interconnection of heterogeneous devices in building automation systems (BAS) and avoiding system fragmentation caused by protocol differences. Protocol conversion latency is as low as less than 50ms, meeting the real-time requirements of building control systems and ensuring rapid response of devices such as HVAC systems. Supports serial port pass-through mode, compatible with non-standard protocol devices, improving system adaptability.

[0037] (3) Modular design, flexible expansion: Core board pin + baseboard architecture, connected by pins. The core board is responsible for basic protocol conversion, eliminating the need to replace the entire machine in case of hardware failure, reducing maintenance costs. Automatic identification of expansion daughter boards reduces manual configuration and improves deployment efficiency.

[0038] (4) Convenient configuration and reduced maintenance difficulty: The visual APP configuration interface supports BACNet device scanning, adding protocol mapping gateways, and automatically generating configuration files. Gateway settings can be completed without professional programming knowledge, greatly reducing the technical threshold. Local upgrade via USB flash drive / USB eliminates the need to disassemble the device or connect a dedicated burning tool, simplifying the firmware update process and improving maintenance efficiency.

[0039] (5) High reliability and adaptability to complex industrial environments: Wide voltage input (9-36V DC), suitable for various power supply environments. PMIC power monitoring with automatic reset in case of abnormality greatly improves system reliability. Multi-level electrical isolation design (RS485 optocoupler isolation), withstand voltage 2500Vrms, effectively suppresses surge, electrostatic interference and other interference, ensuring stable communication in industrial environments. TVS + varistor composite protection circuit complies with IEC61000-4-5 immunity standard, enhancing the equipment's survivability in harsh electromagnetic environments.

[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0042] Figure 1 This is one of the circuit diagrams of an RS485 interface module in a modular building gateway device that supports intelligent multi-protocol conversion, according to an exemplary embodiment.

[0043] Figure 2 This is a second circuit diagram of an RS485 interface module in a modular building gateway device supporting multi-protocol intelligent conversion, according to an exemplary embodiment.

[0044] Figure 3 This is a circuit diagram of an Ethernet interface module in a modular building gateway device that supports intelligent multi-protocol conversion, according to an exemplary embodiment.

[0045] Figure 4 This is a circuit diagram of a USB interface module in a modular building gateway device that supports intelligent multi-protocol conversion, according to an exemplary embodiment.

[0046] Figure 5 This is one of the circuit diagrams of a power module in a modular building gateway device supporting multi-protocol intelligent conversion, according to an exemplary embodiment.

[0047] Figure 6 This is a second circuit diagram of a power module in a modular building gateway device supporting multi-protocol intelligent conversion, according to an exemplary embodiment.

[0048] Figure 7 This is the third circuit diagram of a power module in a modular building gateway device supporting multi-protocol intelligent conversion, according to an exemplary embodiment.

[0049] Figure 8This is the fourth circuit diagram of a power module in a modular building gateway device supporting multi-protocol intelligent conversion, according to an exemplary embodiment.

[0050] Figure 9 This is a circuit diagram of a reset circuit module in a modular building gateway device that supports intelligent multi-protocol conversion, according to an exemplary embodiment.

[0051] Figure 10 This is a framework diagram of the core board module in a modular building gateway device that supports intelligent multi-protocol conversion, according to an exemplary embodiment.

[0052] Figure 11 This is a schematic diagram of a modular building gateway device that supports intelligent multi-protocol conversion, according to an exemplary embodiment. Detailed Implementation

[0053] The following description and accompanying drawings fully illustrate specific embodiments described herein to enable those skilled in the art to practice them. Some embodiments may include or substitute parts and features of other embodiments. The scope of the embodiments herein encompasses the entire scope of the claims and all available equivalents thereof. Throughout this document, the terms “first,” “second,” etc., are used only to distinguish one element from another without requiring or implying any actual relationship or order between the elements. Indeed, a first element can also be referred to as a second element, and vice versa. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a structure, apparatus, or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the structure, apparatus, or device that includes said element. The various embodiments described herein are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0054] The terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this document to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings. They are used solely for the convenience of describing this document and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In the description herein, unless otherwise specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two elements; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0055] In this document, unless otherwise stated, the term "multiple" means two or more.

[0056] In this article, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0057] In this article, the term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0058] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0059] The modules in the apparatus or system of this application can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0060] Where there is no conflict, the embodiments and features in the embodiments of this utility model can be combined with each other.

[0061] Figures 1-11An embodiment of the present invention, a modular building gateway device supporting intelligent multi-protocol conversion, is shown.

[0062] In this optional embodiment, the modular building gateway device supporting multi-protocol intelligent conversion includes: a core board module 1, used to bring out various communication interface resources through board-to-board connectors and connect to the peripheral circuit of the baseboard through pin connectors; an RS485 interface module 2, used to perform level conversion and electrical isolation of the asynchronous serial communication protocol signal of the core board module, and release the IO pin resources of the main control side; to optimize the impedance matching of the RS485 link and improve the tolerance to electromagnetic interference; an Ethernet interface module 3, used to perform electrical isolation and impedance matching of the media independent interface signal of the core board module, and to connect to external network devices; a USB interface module 4, used to expand storage and system upgrade, and to purify and regulate the power supply, suppress common-mode interference, and enable lossless transmission of differential-mode signals; a power supply module 5, used to connect to a DC power supply, and to filter out common-mode and differential-mode interference of the power input, suppress surge overvoltage, realize voltage conversion, and stabilize the output voltage; the RS485 interface module 2, Ethernet interface module 3, USB interface module 4, and power supply module 5 are connected to the core board module 1.

[0063] In this optional embodiment, the core board module 1 includes: a development board processor, a power management integrated circuit, memory, flash memory, and an Ethernet transceiver; the development board processor is connected in sequence to the power management integrated circuit, memory, flash memory, and Ethernet transceiver, and the Ethernet transceiver is connected in sequence to the power management integrated circuit, memory, and flash memory.

[0064] In this optional embodiment, the RS485 interface module 2 includes capacitor C1, chip U1, capacitor C2, resistors R1, R2, C3, R3, chip U7, resistor R4, capacitor C4, resistor R5, resistor R6, R7, pin header J15, diode array Z1, resistors RV2, RV3, R8, MOSFET Q1, and pin header J1. Specifically, the first terminal of chip U1 is connected to capacitor C1, the eighth terminal of chip U1 is connected to capacitor C2, the seventh terminal of chip U1 is sequentially connected to one end of resistor R2, one end of capacitor C3, and one end of resistor R3, the other end of resistor R2 is connected to one end of resistor R1, the other end of resistor R1 is sequentially connected to chip U7 and the drain of the MOSFET, the sixth terminal of chip U1 is sequentially connected to the fourth terminal of chip U7 and one end of resistor R4, and the other end of resistor R4 is connected to the MOSFET. The gate of the transistor is connected, and the other end of resistor R3 is connected to the first end of chip U7. The fifth end of chip U7 is connected in sequence to the source of MOSFET Q1, one end of resistor R5, the third end of diode array Z1, one end of resistor RV2, one end of resistor RV3, and one end of resistor R8. The other end of resistor R8 is connected to the first end of pin header J1. The sixth end of chip U7 is connected in sequence to one end of resistor R6, one end of resistor R7, the first end of diode array Z1, the other end of resistor RV2, and the third end of pin header J1. The other end of resistor R7 is connected to the first end of pin header J15. The seventh end of chip U7 is connected to the other end of resistor R5, the second end of pin header J15, the second end of diode array Z1, the other end of resistor RV3, and the second end of pin header J1. The eighth end of chip U7 is connected in sequence to the other end of resistor R6 and capacitor C4.

[0065] In this optional embodiment, the Ethernet interface module 3 includes a transformer T2, resistors R57 and R58, capacitors C40, R59, R60, and C30, interface J7, resistors R67, R36, and R68, capacitors C111 and C31, resistors R61, R62, R63, R64, R65, R66, and R37; wherein, the first terminal of the transformer T2 is connected to one end of resistor R57, the other end of resistor R57 is sequentially connected to one end of resistor R58 and capacitor C40, the other end of resistor R58 is connected to the third terminal of the transformer T2, the sixth terminal of the transformer T2 is connected to one end of resistor R59, the other end of resistor R59 is sequentially connected to one end of resistor R60 and capacitor C30, and the other end of resistor R60 is connected to the eighth terminal of the transformer T2; the sixteenth and fourteenth terminals of the transformer T2... The eleventh and ninth terminals are connected to the first, second, third, and sixth terminals of interface J7 in sequence. The ninth terminal of connector J7 is connected to one end of resistor R67, and the other end of resistor R67 is connected to one end of resistor R68. Resistor R36 is connected to the tenth terminal of interface J7, and the other end of resistor R68 is connected to the eleventh terminal of interface J7. The twelfth terminal of interface J7 is connected to resistor R37. One end of capacitor C111 is connected to one end of capacitor C31. The other end of capacitor C31 is connected to one end of resistor R61, one end of resistor R62, one end of resistor R63, one end of resistor R64, one end of resistor R65, and one end of resistor R66 in sequence. The other ends of resistors R61, R62, R63, R64, R65, and R66 are respectively connected to different pins of interface J7.

[0066] In this optional embodiment, the USB interface module 4 includes: a current limiting switch U13, capacitors C19 and C20, resistors R130 and R132, capacitors C33 and C21, resistors R18 and C12, capacitors C13, a USB-A terminal J14, a common-mode filter L1, and a chip U5; wherein, the second and third terminals of the current limiting switch U13 are sequentially connected to one end of capacitor C20 and one end of capacitor C19, the other end of capacitor C20 is sequentially connected to the other end of capacitor C19 and one end of resistor R130, the other end of resistor R130 is connected to the fourth terminal of the current limiting switch U13, and the fifth terminal of the current limiting switch U13 is connected to resistor R18. 32. The sixth, seventh, and eighth terminals of the current limiting switch U13 are connected sequentially to one end of capacitor C33, one end of capacitor C21, one end of resistor R18, one end of capacitor C12, one end of capacitor C13, and the first terminal of USB_A terminal J14. The other end of capacitor C33 is connected sequentially to the other end of capacitor C21 and the other end of resistor R18, and the other end of capacitor C12 is connected to the other end of capacitor C13. The second terminal of USB_A terminal J14 is connected sequentially to the first terminal of common-mode filter L1 and the fourth terminal of chip U5, and the third terminal of USB_A terminal J14 is connected sequentially to the second terminal of common-mode filter L1 and the third terminal of chip U5.

[0067] In this optional embodiment, the power module 5 includes: pin header J8, fuse F5, capacitor C43, capacitor C44, capacitor C72, resistor RV5, diode TVS10, transformer T1, diode D48, diode D42, diode D50, diode D49, capacitor C63, capacitor C71, capacitor C52, capacitor C69, capacitor C70, resistor R19, resistor R20, capacitor C53, chip U11, capacitor C54, diode D6, resistor R21, resistor R23, inductor L2, resistor R21, resistor R23, capacitor C68, capacitor C67, capacitor C66, capacitor C14, capacitor C48, and chip U23. The system consists of diode D46, capacitor C47, capacitor C61, and resistor R22. The first end of pin header J8 is connected sequentially to one end of capacitor C43 and one end of capacitor C44. The second end of pin header J8 is connected sequentially to the other end of capacitor C43, one end of capacitor C72, one end of resistor RV5, the second end of diode TVS10, and the first end of transformer T1. The third end of pin header J8 is connected to one end of fuse F5. The other end of fuse F5 is connected sequentially to the other end of capacitor C44, the other end of capacitor C72, the other end of resistor RV5, the first end of diode TVS10, and the second end of transformer T1. The third end of transformer T1 is connected sequentially to diode D46, capacitor C47, capacitor C61, and resistor R22. The positive terminal of diode D42 and the negative terminal of diode D50 are connected. The fourth terminal of transformer T1 is connected in sequence to the positive terminal of diode D48 and the negative terminal of diode D49. The negative terminal of diode D48 is connected in sequence to the negative terminal of diode D42, one end of capacitor C63, and one end of capacitor C71. The positive terminal of diode D50 is connected in sequence to the positive terminal of diode D49, the other end of capacitor C63, and the other end of capacitor C71. Capacitor C52 is connected in parallel with capacitors C69 and C70, and is connected in sequence to the second terminal of chip U11 and one end of resistor R19. The third terminal of chip U11 is connected to the other end of resistor R19. The fourth terminal of chip U11 is connected to one end of resistor R20. The terminals are connected as follows: the other end of resistor R20 is connected to one end of capacitor C53, the other end of capacitor C53 is connected to the sixth terminal of chip U11, the first terminal of chip U11 is connected to one end of capacitor C54, the other end of capacitor C54 is connected in sequence to one end of inductor L2, the negative terminal of diode D6 and the eighth terminal of chip U11, the positive terminal of diode D6 is connected in sequence to the seventh and ninth terminals of chip U11 and one end of resistor R23, the other end of resistor R23 is connected in sequence to one end of resistor R21 and the fifth terminal of chip U11, capacitor C68 is connected in parallel with capacitors C67 and C66, and is connected in sequence to the other end of inductor L2 and the other end of resistor R21.Capacitors C14 and C48 are connected in parallel, with their two ends connected to the third and first terminals of chip U23, respectively. The second and fourth terminals of chip U23 are connected sequentially to one end of capacitor C47, one end of capacitor C61, and the anode of diode D46. The cathode of diode D46 is connected to one end of resistor R22. The other end of resistor R22 is connected sequentially to the other end of capacitor C61 and the other end of capacitor C47.

[0068] In this optional embodiment, a modular building gateway device supporting intelligent multi-protocol conversion further includes: a reset circuit module, used to reset the modular building gateway device supporting intelligent multi-protocol conversion according to the external signal of the switch being pressed. The reset circuit module includes: a resistor R33, a capacitor C11, and a switch SW2; wherein, one end of the resistor R33 is connected to one end of the capacitor C11 and the third end of the switch SW2 in sequence, and the other end of the capacitor C11 is connected to the second end of the switch SW2.

[0069] To facilitate understanding of the above-mentioned technical solution of this utility model, the following further explains the above-mentioned technical solution of this utility model from the perspective of architecture and principle, as follows:

[0070] This utility model relates to a modular building gateway device that supports conversion between multiple protocols such as BACnet and Modbus. The device includes:

[0071] Core board pin module: as shown in the core board frame diagram, as shown Figure 10 As shown, it integrates an AM335X processor, PMIC, DDR3 SDRAM, NAND Flash, and two Ethernet transceivers. The interface is a three-pin connector that connects to the peripheral circuitry of the baseboard.

[0072] The PMIC communicates with the AM335X processor via the I2C (Inter-Integrated Circuit, a synchronous serial communication bus protocol) bus, providing stable and compatible power to the AM335X processor, DDR3 SDRAM (3rd generation Double Data Rate Synchronous Dynamic Random Access Memory), NAND Flash, and two Ethernet transceivers. The AM335X processor communicates with the DDR3 SDRAM via the address and data buses, using control signals for reset and read / write control, achieving high-speed data storage and retrieval. This provides robust support for system tasks sensitive to data access speed, such as operating system kernel loading and application data caching. In multitasking scenarios, it efficiently exchanges data between different tasks. The AM335X processor connects to the NAND Flash via the GPMC (General Purpose Parallel Memory Controller) interface. The GPMC interface provides the processor with a standardized and configurable interface protocol, enabling convenient access to the NAND Flash. NAND Flash, with its non-volatile storage characteristics (data is not lost after power failure), undertakes the important task of long-term system data storage, such as storing user configuration files, historical records, and large-scale data files. The processor sends address signals (to locate memory cells), data signals (to transmit data to be stored or retrieved), and control signals (such as programming commands and erase commands) to the NAND Flash via the GPMC interface to perform various operations on the NAND Flash. The circuit, centered around the KSZ8041NL Ethernet PHY chip, communicates with the MAC layer of the main control chip AM335X via the RMII interface (RMII_TXD0, RMII_TXEN, etc., which are Ethernet interface specifications defined in the IEEE 802.3u standard) to complete the physical layer processing of Ethernet data frames. The logic gate chip receives the PMIC_RESETOUTn signal from the processor and PMIC, uses AND gate logic to determine and output the final reset signal ETH_RESETn to the Ethernet PHY chip. This enables precise management of the Ethernet module reset operation, ensuring the stable operation of the Ethernet communication function.

[0073] The core board uses three sets of high-reliability headers for interconnection with the baseboard: J1: 2x56pin (2.54mm pitch); J2: 2x56pin (2.54mm pitch); J3: 2x40pin (2.54mm pitch). Input power: DC5V. The PMIC supplies power to the AM335X processor core and I / O, DDR3 memory modules, NAND Flash storage units, and Ethernet circuitry. The PMIC and processor communicate via an I2C bus for digital power management, supporting dynamic voltage regulation and power consumption monitoring. DDR3 memory is connected to the processor via an EMIF interface (external memory interface) for off-chip expansion. The NAND Flash uses a GPMC interface for large-capacity non-volatile storage. The Ethernet PHY connects to the processor via an RMII interface, supporting 10 / 100Mbps adaptive transmission.

[0074] The core board fully exposes various communication interface resources through high-density board-to-board connectors: including a 3xUART (an asynchronous serial communication protocol) control bus; USB 2.0 high-speed differential signals; reserved I / O expansion capabilities (supporting interrupt wake-up capability); providing a basic interconnect architecture for building a complete gateway hardware system on the baseboard. Communication interfaces:

[0075] Two isolated RS485 interfaces (SN65HVD3082E chip). For example... Figures 1-2 The circuit diagram for the RS485 interface is as follows: The 3.3V UART signal on the main control side is converted to a 5V UART signal through U1 (ADUM3201) for level conversion and electrical isolation. This not only achieves isolation and protection between the external interface and the main control unit but also accurately adapts to the level standard of the U7 (SN65HVD3082E) RS485 driver. As the core component for UART signal to RS485 signal conversion, the U7 (SN65HVD3082E) RS485 driver effectively frees up the I / O pin resources on the main control side thanks to its automatic transceiver circuit design. This feature is particularly advantageous in situations where the I / O resources on the main control side are limited. The J15 header configured in the subsequent stage of the circuit performs impedance matching optimization for the RS485 link in complex scenarios with dense device nodes or long communication distances, significantly improving signal transmission quality and effectively extending the communication coverage distance. The interface output adopts a composite suppression architecture of TVS devices and varistors, which greatly enhances the system's tolerance to electromagnetic interference such as surges and static electricity, comprehensively improves the system's electrical performance indicators, and builds a solid electrical foundation for reliable communication. Figure 1 Line segments ①, ②, and ③ in the diagram are respectively connected to... Figure 2 Connect line segments ①, ②, and ③.

[0076] One 10 / 100M Ethernet port. (For example...) Figure 3The diagram shows the Ethernet interface circuit: The MII interface signal (Media Independent Interface) from the Ethernet PHY chip undergoes physical layer signal processing (including conversion from digital signals to analog signals adapted to the transmission medium, signal encoding, and level conversion). Network transformer T2 provides electrical isolation to the signal, preventing external electromagnetic interference from affecting the internal circuitry, while also achieving impedance matching for signal transmission to minimize energy loss. Subsequently, it connects to external network devices via RJ45 interface J7, enabling local device data to be transmitted via TD+ and TD-, and external network data to be received via RD+ and RD-. During this process, indicator lights such as LED1_LINK and LED1_SPEED are linked to provide feedback on the network connection status (LED1_LINK indicates whether the connection is active, and LED1_SPEED's illumination mode or color indicates the connection speed) to facilitate troubleshooting and performance evaluation. In addition, the electrical isolation of capacitors C111 and C31 and the network transformer work together to ensure the stability of the circuit signal and the anti-interference. The +3.3VA power supply provides power to the chips (Ethernet PHY chip, indicator light driver circuit components, etc.) to ensure the reliable operation of Ethernet communication function and reduce communication errors or equipment failures caused by power fluctuations and signal interference.

[0077] One USB-A port. Can be used for storage expansion and system upgrades. (e.g.) Figure 4 The diagram shows the USB_A interface circuit: The +5V power supply is purified by C19 (47μF, low-frequency decoupling) and C20 (0.1μF, high-frequency filtering) before being fed into the current-limiting switch U13 (TPS2065D). U13 detects overcurrent / short circuit and cuts off the output in case of an abnormality. A capacitor is connected to the OUT pin to further stabilize the VBUS voltage. In the signal path, USB0_DN / DP uses ACM2012D to suppress common-mode interference, while differential-mode signals are transmitted without loss. TVS diodes (such as VT1 / VT2 of CM1210) are connected in series on the signal lines, with a clamping voltage ≤8V, meeting the IEC61000-4-2 Level 4 standard. The processed power supply (VBUS) and signal (DN / DP) are connected to the USB_A terminal (J14), supporting hot-swapping and a 500mA load.

[0078] One hardware reset button. (e.g.) Figure 9 The diagram shows the reset circuit: The RSTN node communicates with the processor. When it receives an external signal indicating that the switch is pressed, RSTN is grounded via SW2 and becomes low, triggering a hardware reset. When SW2 is released, R33 charges C11, and RSTN gradually returns to a high level. The system then completes the reset and enters normal operation.

[0079] Power module: such as Figures 5-8The diagram shows the power module circuit: POWER_L and POWER_N are connected to a 9-36V DC power supply, protected against overcurrent damage by fuse F5 (LP60 065). Capacitors filter input common-mode and differential-mode interference; RV5 (10K470) varistors and TVS10 (SMBJ47CA / NP) transient voltage suppression diodes suppress surge overvoltage. The VIN pin of U11 (LMR14030SDDAR) is connected to the pre-processed voltage, filtered by a capacitor. The EN pin is pulled up by R19 to enable the chip; the SS pin is connected to C33 for soft start; the SW pin is connected to L2 and D6, and the inductor stores and releases energy through the internal switching transistor of the chip, realizing voltage conversion; the FB pin forms a feedback network with R21 and R23 to stabilize the output voltage; the converted voltage is filtered by a capacitor, outputting a relatively stable +5V voltage. After being filtered by a capacitor, the +5V voltage is regulated to +3.3V by U23 (TLV1117), and then output from the outlet after filtering. D46 is the core function of this circuit; it acts as an indicator light for the +3.3V power supply, visually reflecting the +3.3V power supply status by whether it is lit or not.

[0080] Protocol conversion function, basic protocol conversion:

[0081] Modbus RTU BACnet IP. Modbus TCP BACnet IP. BACnet MS / TP BACnet IP. Modbus RTU Modbus TCP. Modbus RTU BACnet MS / TP.

[0082] Serial port pass-through mode (serial port data is converted into network data through a gateway device).

[0083] Software features:

[0084] USB Flash Drive Upgrade: First, identify the upgrade file with the specified name on the USB flash drive, and then automatically execute the upgrade script. Visual Configuration Interface (APP): After configuring the protocol conversion gateway, add ports under the gateway. A maximum of 8 ports can be added under one gateway, and a maximum of 32 devices can be added under each port. A configuration file will be generated after configuration; upload the configuration file to the device and restart for the changes to take effect. Visual Management Interface (APP): Allows you to obtain the current running status of gateway devices, modify device IP configuration files, modify device node configuration files, restart devices, and restore factory settings. BACNet (Communication Protocol for Smart Buildings) Device Scan: Can scan devices on the local area network that communicate via the BACnetIP protocol (Communication Protocol for Building Automation and Control Networks) and automatically obtain device information.

[0085] Example 1: Hardware architecture implementation.

[0086] Combination Figures 1-11 The modular building gateway device shown is implemented as follows:

[0087] Core board module:

[0088] Processor Unit: The AM335X processor connects to a 256MB NAND Flash (K9K8G08U0A) via the GPMC interface to store system firmware and protocol mapping tables; it also connects to a 512MB DDR3 (IS43TR16256A) via a 16-bit data bus to run protocol conversion middleware. Power Management: The TPS65910A3 PMIC receives processor commands via the I2C bus and outputs: 1.1V core voltage (AM335X processor); 1.8V (DDR3 terminating resistor); 3.3V (PHY chip and peripherals). Ethernet Interface: Two KSZ8041FTL PHY chips connect to the processor via the RMII interface. The reset signal is controlled by an SN74LVC1G08 AND gate logic (inputs PMIC_RESETOUTn and GPIO).

[0089] Communication interface module:

[0090] RS485 Interface: Signal Path: AM335X_UART1 / 2 → ADUM3201 Isolation

[0091] →SN65HVD3082E driver →TVS + varistor protection. Finally, a 100Ω terminating resistor is configured at the J15 pin header to absorb reflections and echoes, improving signal quality. Ethernet interface: The RMII signal of the KSZ8041FTL is coupled to the RJ45 via the H1102 network transformer; LED1_LINK illuminates to indicate link establishment. USB interface: A TPS2065D current-limiting switch protects VBUS; the signal line is connected in series with an ACM2012D common-mode choke and then ESD protection is provided by a CM1210 TVS array.

[0092] Example 2: Protocol conversion implementation.

[0093] Modbus RTU → BACnet IP translation:

[0094] Hardware trigger: RS485_1 receives Modbus frame (01 03 00 00 00 01 84 0A). Software processing: / / AM335X protocol stack thread:

[0095] bacnet_object_id = modbus_reg_to_bacnet(40001); / / Mapped to AI-101

[0096] build_bacnet_readprop(bacnet_object_id,&apdu);

[0097] send_via_ethernet(apdu).

[0098] In this utility model: the core board module integrates an AM335X processor, a PMIC power management unit, DDR3 memory, NAND Flash, and two Ethernet PHY chips, and is interconnected with the baseboard through a board-to-board connector; the communication interface module includes at least two isolated RS485 interfaces, one Ethernet interface, and one USB interface; the power supply module supports a wide voltage input of 9-36V and provides multiple regulated outputs; and the protocol conversion module realizes bidirectional protocol conversion between BACnet and Modbus.

[0099] In the core board module: the AM335X processor accesses the NAND Flash through the GPMC interface to store the protocol mapping table; the reset signals of the two KSZ8041FTL PHY chips are controlled by the PMIC_RESETOUTn and GPIO signals through AND gate logic.

[0100] The RS485 interface includes: an ADUM3201 digital isolator with an isolation withstand voltage of 2500Vrms; an SN65HVD3082E transceiver with integrated automatic transceiver control circuitry; and a TVS-varistor composite protection circuit that meets the IEC61000-4-5 standard.

[0101] The protocol conversion module supports dynamic mapping between Modbus register addresses and BACnet object identifiers. The USB flash drive upgrade interface supports automatic recognition of FAT32 format firmware packages.

[0102] This invention is not limited to the structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this invention is limited only by the appended claims.

Claims

1. A modular building gateway device supporting intelligent multi-protocol conversion, characterized in that, include: The core board module is used to bring out various communication interface resources through board-to-board connectors and connect to the peripheral circuits of the baseboard through pin connectors; The RS485 interface module is used to perform level conversion and electrical isolation of the asynchronous serial communication protocol signals of the core board module, and to release the IO pin resources on the main control side; it also optimizes the impedance matching of the RS485 link and improves the tolerance to electromagnetic interference. The Ethernet interface module is used to electrically isolate and impedance match the media-independent interface signals of the core board module, and to connect to external network devices. The USB interface module is used for expanding storage and system upgrades, and it also purifies and regulates the power supply, suppresses common-mode interference, and enables lossless transmission of differential-mode signals. The power module is used to connect to a DC power supply and filter out common-mode and differential-mode interference from the power input, suppress surge overvoltage, realize voltage conversion, and stabilize the output voltage. The RS485 interface module, the Ethernet interface module, the USB interface module, and the power supply module are connected to the core board module.

2. The modular building gateway device supporting intelligent multi-protocol conversion according to claim 1, characterized in that, The core board module includes: a development board processor, a power management integrated circuit, memory, flash memory, and an Ethernet transceiver; The development board processor is connected in sequence to the power management integrated circuit, the memory, the flash memory and the Ethernet transceiver, and the Ethernet transceiver is connected in sequence to the power management integrated circuit, the memory and the flash memory.

3. A modular building gateway device supporting intelligent multi-protocol conversion according to claim 1, characterized in that, The RS485 interface module includes capacitor C1, chip U1, capacitor C2, resistor R1, resistor R2, capacitor C3, resistor R3, chip U7, resistor R4, capacitor C4, resistor R5, resistor R6, resistor R7, pin header J15, diode array Z1, resistor RV2, resistor RV3, resistor R8, MOSFET Q1, and pin header J1. Wherein, the first terminal of chip U1 is connected to capacitor C1, the eighth terminal of chip U1 is connected to capacitor C2, the seventh terminal of chip U1 is sequentially connected to one end of resistor R2, one end of capacitor C3 and one end of resistor R3, the other end of resistor R2 is connected to one end of resistor R1, the other end of resistor R1 is sequentially connected to chip U7 and the drain of MOS transistor, the sixth terminal of chip U1 is sequentially connected to the fourth terminal of chip U7 and one end of resistor R4, the other end of resistor R4 is connected to the gate of MOS transistor, and the other end of resistor R3 is connected to the first terminal of chip U7; The fifth terminal of chip U7 is sequentially connected to the source of MOSFET Q1, one end of resistor R5, the third terminal of diode array Z1, one end of resistor RV2, one end of resistor RV3, and one end of resistor R8. The other end of resistor R8 is connected to the first terminal of pin header J1. The sixth terminal of chip U7 is sequentially connected to one end of resistor R6, one end of resistor R7, the first terminal of diode array Z1, the other end of resistor RV2, and the third terminal of pin header J1. The other end of resistor R7 is connected to the first terminal of pin header J15. The seventh terminal of chip U7 is connected to the other end of resistor R5, the second terminal of pin header J15, the second terminal of diode array Z1, the other end of resistor RV3, and the second terminal of pin header J1. The eighth terminal of chip U7 is sequentially connected to the other end of resistor R6 and capacitor C4.

4. A modular building gateway device supporting intelligent multi-protocol conversion according to claim 1, characterized in that, The Ethernet interface module includes a transformer T2, resistors R57 and R58, capacitors C40, R59, R60, and C30, interface J7, resistors R67, R36, and R68, capacitors C111 and C31, resistors R61, R62, R63, R64, R65, R66, and R37. Wherein, the first terminal of the transformer T2 is connected to one terminal of the resistor R57, the other terminal of the resistor R57 is connected in sequence to one terminal of the resistor R58 and the capacitor C40, the other terminal of the resistor R58 is connected to the third terminal of the transformer T2, the sixth terminal of the transformer T2 is connected to one terminal of the resistor R59, the other terminal of the resistor R59 is connected in sequence to one terminal of the resistor R60 and the capacitor C30, and the other terminal of the resistor R60 is connected to the eighth terminal of the transformer T2; The sixteenth, fourteenth, eleventh, and ninth terminals of the transformer T2 are connected to the first, second, third, and sixth terminals of the interface J7 in sequence. The ninth terminal of the connector J7 is connected to one end of the resistor R67, and the other end of the resistor R67 is connected to one end of the resistor R68. The resistor R36 is connected to the tenth terminal of the interface J7, the other end of the resistor R68 is connected to the eleventh terminal of the interface J7, and the twelfth terminal of the interface J7 is connected to the resistor R37. One end of capacitor C111 is connected to one end of capacitor C31. The other end of capacitor C31 is connected in sequence to one end of resistor R61, one end of resistor R62, one end of resistor R63, one end of resistor R64, one end of resistor R65, and one end of resistor R66. The other ends of resistors R61, R62, R63, R64, R65, and R66 are respectively connected to different pins of interface J7.

5. A modular building gateway device supporting intelligent multi-protocol conversion according to claim 1, characterized in that, The USB interface module includes: a current limiting switch U13, capacitors C19 and C20, resistors R130 and R132, capacitors C33 and C21, resistors R18 and C12, capacitors C13, a USB_A terminal J14, a common-mode filter L1, and a chip U5. Specifically, the second and third terminals of the current limiting switch U13 are sequentially connected to one end of capacitor C20 and one end of capacitor C19. The other end of capacitor C20 is sequentially connected to the other end of capacitor C19 and one end of resistor R130. The other end of resistor R130 is connected to the fourth terminal of the current limiting switch U13. The fifth terminal of the current limiting switch U13 is connected to resistor R132. The sixth, seventh, and eighth terminals of the current limiting switch U13 are sequentially connected to one end of capacitor C33, one end of capacitor C21, one end of resistor R18, one end of capacitor C12, one end of capacitor C13, and the first terminal of USB_A terminal J14. The other end of capacitor C33 is sequentially connected to the other end of capacitor C21 and the other end of resistor R18. The other end of capacitor C12 is connected to the other end of capacitor C13. The second end of the USB_A terminal J14 is connected in sequence to the first end of the common-mode filter L1 and the fourth end of the chip U5, and the third end of the USB_A terminal J14 is connected in sequence to the second end of the common-mode filter L1 and the third end of the chip U5.

6. A modular building gateway device supporting intelligent multi-protocol conversion according to claim 1, characterized in that, The power module includes: pin header J8, fuse F5, capacitor C43, capacitor C44, capacitor C72, resistor RV5, diode TVS10, transformer T1, diode D48, diode D42, diode D50, diode D49, capacitor C63, capacitor C71, capacitor C52, capacitor C69, capacitor C70, resistor R19, resistor R20, capacitor C53, chip U11, capacitor C54, diode D6, resistor R21, resistor R23, inductor L2, resistor R21, resistor R23, capacitor C68, capacitor C67, capacitor C66, capacitor C14, capacitor C48, chip U23, diode D46, capacitor C47, capacitor C61, and resistor R22; Specifically, the first end of the pin header J8 is sequentially connected to one end of capacitor C43 and one end of capacitor C44; the second end of the pin header J8 is sequentially connected to the other end of capacitor C43, one end of capacitor C72, one end of resistor RV5, the second end of diode TVS10, and the first end of transformer T1; the third end of the pin header J8 is connected to one end of fuse F5; and the other end of fuse F5 is sequentially connected to the other end of capacitor C44, the other end of capacitor C72, the other end of resistor RV5, and the second end of diode TVS10. The first terminal is connected to the second terminal of the transformer T1. The third terminal of the transformer T1 is connected in sequence to the anode of diode D42 and the cathode of diode D50. The fourth terminal of the transformer T1 is connected in sequence to the anode of diode D48 and the cathode of diode D49. The cathode of diode D48 is connected in sequence to the cathode of diode D42, one end of capacitor C63, and one end of capacitor C71. The anode of diode D50 is connected in sequence to the anode of diode D49, the other end of capacitor C63, and the other end of capacitor C71. The capacitor C52 is connected in parallel with the capacitors C69 and C70, and is sequentially connected to the second terminal of the chip U11 and one end of the resistor R19. The third terminal of the chip U11 is connected to the other end of the resistor R19. The fourth terminal of the chip U11 is connected to one end of the resistor R20. The other end of the resistor R20 is connected to one end of the capacitor C53. The other end of the capacitor C53 is connected to the sixth terminal of the chip U11. The first terminal of the chip U11 is connected to one end of the capacitor C54. The other end of capacitor C54 is connected in sequence to one end of inductor L2, the negative terminal of diode D6, and the eighth terminal of chip U11. The positive terminal of diode D6 is connected in sequence to the seventh and ninth terminals of chip U11 and one end of resistor R23. The other end of resistor R23 is connected in sequence to one end of resistor R21 and the fifth terminal of chip U11. Capacitor C68 is connected in parallel with capacitors C67 and C66, and is connected in sequence to the other end of inductor L2 and the other end of resistor R21. The capacitor C14 and the capacitor C48 are connected in parallel, and the two ends of the capacitors C14 and C48 are respectively connected to the third and first ends of the chip U23. The second and fourth ends of the chip U23 are connected in sequence to one end of the capacitor C47, one end of the capacitor C61, and the positive terminal of the diode D46. The negative terminal of the diode D46 is connected to one end of the resistor R22. The other end of the resistor R22 is connected in sequence to the other end of the capacitor C61 and the other end of the capacitor C47.

7. A modular building gateway device supporting intelligent multi-protocol conversion according to claim 1, characterized in that, Also includes: A reset circuit module is used to reset the modular building gateway device supporting multi-protocol intelligent conversion based on an external signal indicating that the switch has been pressed. The reset circuit module includes: Resistor R33, capacitor C11 and switch SW2; One end of the resistor R33 is connected in sequence to one end of the capacitor C11 and the third end of the switch SW2, and the other end of the capacitor C11 is connected to the second end of the switch SW2.

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