Semiconductor package structure

Abstract

The utility model provides a kind of semiconductor packaging structure, the semiconductor packaging structure includes electric connection structure, by being provided with first support structure below photoelectric integrated chip, that is, a support structure of stacked through silicon via connection is provided below relatively thin photoelectric integrated chip, can reduce the risk of rupture of photoelectric integrated chip too thin on the basis of not increasing through silicon via depth, improve its yield and reliability, simultaneously, photoelectric integrated chip can also reduce the stress borne by it.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and specifically to a semiconductor packaging structure. Background Technology

[0002] Silicon photonics technology is an innovative technology that integrates optical and electronic functions onto a single chip, and it is widely used in fields such as high-speed data transmission, precision sensing, and quantum computing. Among them, the photonic integrated circuit (PIC), as a key component of silicon photonics technology, is mainly responsible for receiving laser light generated by a light source and converting the optical signal into a data signal that can be used for various applications through processes such as modulation, wavelength division, and photoelectric conversion.

[0003] Currently, most photonic integrated chips have through-silicon vias (TSVs). In order to reduce the overall manufacturing cost, photonic integrated chips are usually thinned to shorten the depth of the TSVs.

[0004] However, when photonic integrated chips are excessively thinned, they are prone to cracking due to insufficient mechanical strength during subsequent board mounting or manufacturing processes, which in turn affects their yield and reliability. Utility Model Content

[0005] This invention proposes a semiconductor packaging structure.

[0006] In a first aspect, this utility model proposes a semiconductor packaging structure, comprising:

[0007] Optoelectronic integrated chips;

[0008] The second wafer is disposed above the optoelectronic integrated chip;

[0009] The first support structure is disposed below the optoelectronic integrated chip;

[0010] A redistribution layer is disposed below the first support structure, and the first support structure is electrically connected to the optoelectronic integrated chip and the redistribution layer.

[0011] In some optional embodiments, the semiconductor package structure further includes:

[0012] A first through-silicon via (TSV) structure is disposed inside the optoelectronic integrated chip.

[0013] In some alternative implementations, the first through-silicon via structure extends through the optoelectronic integrated chip.

[0014] In some optional embodiments, the semiconductor package structure further includes:

[0015] A second through-silicon via structure is disposed inside the first support structure.

[0016] In some alternative implementations, the second through-silicon via structure penetrates the first support structure.

[0017] In some alternative implementations, the first through-silicon via (TSV) structure and the second TSV structure are stacked in alignment.

[0018] In some optional embodiments, the semiconductor package structure further includes:

[0019] An optical waveguide is disposed within the redistribution layer.

[0020] In some alternative implementations, the vertical projections of the first and second through-silicon via structures fall within the vertical projection range of the second wafer.

[0021] In some alternative embodiments, the optoelectronic integrated chip is in direct contact with the first support structure and the first through-silicon via structure is in direct contact with the second through-silicon via structure.

[0022] In some optional embodiments, the semiconductor package structure further includes:

[0023] A printed circuit board is disposed below the redistribution layer.

[0024] To address the issue that excessively thin photonic integrated chips are prone to breakage due to insufficient mechanical strength, thus affecting their yield and reliability, this invention proposes a semiconductor packaging structure. By setting a first support structure below the photonic integrated chip—that is, setting a support structure with stacked through-silicon vias (TSVs) below the relatively thin photonic integrated chip—the risk of breakage due to excessive thinness of the photonic integrated chip can be reduced without increasing the depth of the TSVs, thereby improving its yield and reliability. At the same time, it can also reduce the stress borne by the photonic integrated chip. Attached Figure Description

[0025] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a schematic diagram of an existing semiconductor packaging structure;

[0027] Figure 2 This is a schematic diagram of a semiconductor packaging structure 2a according to an embodiment of the present invention;

[0028] Figures 3-11This is a schematic diagram of the manufacturing steps of a semiconductor packaging structure 2a according to an embodiment of the present invention.

[0029] Explanation of reference numerals / symbols in the attached diagram:

[0030] 101-Optical integrated chip; 102-Through silicon via (TSV); 103-Electronic integrated circuit; 104-Redistribution layer; 105-Optical waveguide; 106-Printed circuit board; 107-Virtual chip; 201-Optical integrated chip; 202-Second wafer; 203-First support structure; 204-Redistribution layer; 205-First TSV structure; 206-Second TSV structure; 207-Second support structure; 208-Third support structure; 209-Optical waveguide; 210-Fill layer; 211-Printed circuit board; 212-Solder ball; 2a-Semiconductor packaging structure. Detailed Implementation

[0031] The specific embodiments of this utility model will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this utility model and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0032] It should be readily understood that the meanings of "on," "above," and "on top of" in this utility model should be interpreted in the broadest sense, such that "on" not only means "directly on something," but also means "on something" including intermediate components or layers existing between the two.

[0033] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0034] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0035] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0036] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the implementation conditions of this utility model and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the technical content disclosed in this utility model. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.

[0037] It should also be noted that the longitudinal section corresponding to the embodiment of this utility model can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0038] Furthermore, where there is no conflict, the embodiments and features described in these embodiments can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] refer to Figure 1, Figure 1 This is a schematic diagram of an existing semiconductor packaging structure.

[0040] like Figure 1 As shown, the existing semiconductor packaging structure includes an optoelectronic integrated chip 101, a through-silicon via 102, an electronic integrated circuit 103, a redistribution layer 104, an optical waveguide 105, a printed circuit board 106, and a virtual chip 107.

[0041] The through-silicon via 102 is configured to pass through the optoelectronic integrated chip 101, the electronic integrated circuit 103 is disposed above the optoelectronic integrated chip 101, the redistribution layer 104 is disposed below the optoelectronic integrated chip 101 and the optical waveguide 105 is disposed within the redistribution layer 104, and the virtual chip is disposed above the electronic integrated circuit 103.

[0042] In order to reduce the overall manufacturing cost, the photonic integrated chip 101 is usually thinned during the manufacturing process. As a result, it is prone to cracking due to insufficient mechanical strength in subsequent processes or when it is placed on the printed circuit board 106, which will affect its yield and reliability.

[0043] refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor packaging structure 2a according to an embodiment of the present invention.

[0044] like Figure 2 As shown, the semiconductor packaging structure 2a of this utility model includes an optoelectronic integrated chip 201, a second wafer 202, a first support structure 203, and a redistribution layer 204. The second wafer 202 is disposed above the optoelectronic integrated chip 201, the first support structure 203 is disposed below the optoelectronic integrated chip 201, and the redistribution layer 204 is disposed below the first support structure 203, with the first support structure 203 electrically connecting the optoelectronic integrated chip 201 and the redistribution layer 204.

[0045] Here, the optoelectronic integrated chip 201 can be used to receive the optical signal generated by the light source, and convert the optical signal into a data signal that can be used in various applications through modulation, wavelength division and photoelectric conversion.

[0046] The first support structure 203 can be a structure with support and signal transmission capabilities. For example, the first support structure 203 can be an optoelectronic integrated chip, without any specific limitations.

[0047] Thus, by providing the first support structure 203, effective structural support can be provided for the relatively thin optoelectronic integrated chip 201. This reduces the risk of breakage due to excessive thinness of the optoelectronic integrated chip 201 during board mounting or manufacturing processes, thereby improving the yield and reliability of the optoelectronic integrated chip 201. Furthermore, the first support structure 203 also helps to disperse externally applied mechanical stress, further reducing the stress experienced by the optoelectronic integrated chip 201 during processing and application, and improving the stability and durability of the semiconductor packaging structure 2a.

[0048] In some alternative embodiments, the semiconductor package structure 2a may further include a first through-silicon via structure 205 disposed inside the optoelectronic integrated chip 201.

[0049] In some alternative implementations, the first through-silicon via 205 extends through the optoelectronic integrated chip 201.

[0050] Here, the first through-silicon via structure 205 is disposed inside and through the optoelectronic integrated chip 201, which can realize the electrical connection between the optoelectronic integrated chip 201 and the second wafer 202. Furthermore, the second wafer 202 can be electrically connected to the first support structure 203 through the optoelectronic integrated chip 201.

[0051] In some alternative embodiments, the semiconductor package structure 2a may further include a second through-silicon via structure 206 disposed inside the first support structure 203.

[0052] In some alternative implementations, the second through-silicon via structure 206 penetrates the first support structure 203.

[0053] Here, by placing the second through-silicon via (TSV) structure 206 inside and through the first support structure 203, an electrical connection can be made between the optoelectronic integrated chip 201 and the redistribution layer 204 through the first support structure 203. Furthermore, by placing the second TSV structure 206 and the first TSV structure 205 in the first support structure 203 and the optoelectronic integrated chip 201 respectively, the risk of breakage due to excessive thinness of the optoelectronic integrated chip 201 can be reduced without increasing the depth of the TSVs in the optoelectronic integrated chip 201, thereby improving the yield and reliability of the optoelectronic integrated chip 201.

[0054] In some alternative implementations, the first through-silicon via (TSV) structure 205 and the second TSV structure 206 are stacked in alignment.

[0055] Thus, through precise alignment and stacking, the first through-silicon via (TSV) structure 205 and the second TSV structure 206 can achieve a more reliable vertical electrical connection, ensuring the continuity and stability of the signal transmission path. Furthermore, by aligning and stacking, the first TSV structure 205 and the second TSV structure 206 can be directly connected to form the shortest vertical interconnect path, which can reduce signal delay, lower power consumption, and improve data transmission rate.

[0056] In some alternative implementations, the vertical projections of the first through-silicon via (TSV) structure 205 and the second TSV structure 206 fall within the vertical projection range of the second wafer 202.

[0057] In other words, the first through-silicon via (TSV) structure 205 and the second TSV structure 206 are only disposed below the second wafer 202. This ensures that the signal transmission path is the shortest and most direct, reduces signal delay, and improves the data transmission rate.

[0058] In some alternative implementations, the optoelectronic integrated chip 201 is in direct contact with the first support structure 203 and the first through-silicon via structure 205 is in direct contact with the second through-silicon via structure 206.

[0059] In this way, dielectric bonding can be formed between the interface between the optoelectronic integrated chip 201 and the first support structure 203, and metallic bonding can be formed between the first through-silicon via structure 205 and the second through-silicon via structure 206.

[0060] In some optional embodiments, the thickness of the optoelectronic integrated chip 201 and the first support structure 203 may be the same or different. The thickness of the optoelectronic integrated chip 201 is less than or equal to 50 μm. The specific thickness can be set according to actual needs and is not limited here.

[0061] In some alternative embodiments, the semiconductor package structure 2a further includes a second support structure 207 disposed above the optoelectronic integrated chip 201 and on the side of the second wafer 202.

[0062] Here, there may be a gap between the second support structure 207 and the second chip 202.

[0063] The second support structure 207 can provide additional physical support for the optoelectronic integrated chip 201 and its surrounding components to enhance the mechanical strength of the semiconductor package structure 2a. In addition, the second support structure 207 can also help disperse the mechanical stress applied to the semiconductor package structure 2a, especially the stress concentrated on the optoelectronic integrated chip 201, further reducing the risk of the optoelectronic integrated chip 201 breaking.

[0064] In some alternative implementations, the thickness of the second support structure 207 is the same as the thickness of the second wafer 202.

[0065] In some alternative embodiments, the semiconductor package structure 2a may further include a third support structure 208 disposed above the second wafer 202 and the second support structure 207.

[0066] Here, the third support structure 208 is disposed above the second chip 202 and the second support structure 207, and can form a multi-layer support system with the first support structure 203 and the second support structure 207, which can more effectively disperse stress and enhance the mechanical strength of the overall package. In addition, the third support structure 208 plays a role in protecting the second chip 202 and improving the reliability and durability of the second chip 202.

[0067] In some alternative implementations, the semiconductor package structure 2a may also include an optical waveguide 209 disposed within the redistribution layer 204.

[0068] Here, the optical waveguide 209 can be used to guide and transmit optical signals. Specifically, the optical waveguide 209 can transmit the optical signal via the redistribution layer 204 to the first support structure 203, and then from the first support structure 203 to the optoelectronic integrated chip 201. The optoelectronic integrated chip 201 can convert the optical signal into a data signal that can be used in various applications. By integrating the optical waveguide 209 into the redistribution layer 204, a highly efficient optical signal transmission path can be achieved without increasing the physical space.

[0069] In some alternative embodiments, the semiconductor package structure 2a may further include a filler layer 210 disposed between the optoelectronic integrated chip 201 and the third support structure 208 and covering the second support structure 207 and the second wafer 202.

[0070] Here, the filler layer 210 can protect the second support structure 207 and the second wafer 202.

[0071] In some alternative implementations, the semiconductor package structure 2a may also include a printed circuit board 211 disposed below the redistribution layer 204.

[0072] In some alternative embodiments, the semiconductor package structure 2a may further include solder balls 212 disposed between the printed circuit board 211 and the redistribution layer 204 and electrically connecting the printed circuit board 211 and the redistribution layer 204.

[0073] The above describes a semiconductor packaging structure 2a according to an embodiment of the present invention.

[0074] Figures 3-11 This is a schematic diagram of the manufacturing steps of a semiconductor packaging structure 2a according to an embodiment of the present invention.

[0075] refer to Figure 3 It provides an optoelectronic integrated chip 201 and a first through-silicon via structure 205.

[0076] Here, the first through-silicon via structure 205 is disposed inside the optoelectronic integrated chip 201.

[0077] refer to Figure 4 The optoelectronic integrated chip 201 was ground.

[0078] Here, the optoelectronic integrated chip 201 can be ground so that the first through-silicon via structure 205 penetrates the optoelectronic integrated chip 201.

[0079] refer to Figure 5 A second wafer 202, a second support structure 207, and a filling layer 210 are disposed on one side of the optoelectronic integrated chip 201.

[0080] Here, you can refer to Figure 4 The optoelectronic integrated chip 201 is flipped, and then a second wafer 202 and a second support structure 207 are disposed on top of the optoelectronic integrated chip 201. A filling layer 210 is then disposed to cover the second support structure 207 and the second wafer 202.

[0081] refer to Figure 6 A third support structure 208 is provided above the second chip 202 and the second support structure 207.

[0082] refer to Figure 7 A first support structure 203 and a second through-silicon via structure 206 are provided on the other side of the optoelectronic integrated chip 201.

[0083] Here, the second through-silicon via structure 206 is disposed inside the first support structure 203, and the first through-silicon via structure 205 and the second through-silicon via structure 206 are stacked in alignment.

[0084] refer to Figure 8 The first support structure 203 is ground.

[0085] Here, the first support structure 203 can be ground so that the second through-silicon via structure 206 penetrates the first support structure 203.

[0086] Thus, by setting the first support structure 203, effective structural support can be provided for the relatively thin optoelectronic integrated chip 201, thereby reducing the risk of breakage due to excessive thinness during board mounting or manufacturing processes, and improving the yield and reliability of the optoelectronic integrated chip 201. Furthermore, the first support structure 203 also helps to disperse externally applied mechanical stress, further reducing the stress experienced by the optoelectronic integrated chip 201 during processing and application, and improving the stability and durability of the semiconductor packaging structure.

[0087] refer to Figure 9 A redistribution layer 204 is provided on the first support structure 203 and an optical waveguide 209 is provided within the redistribution layer 204.

[0088] refer to Figure 10 Solder balls 212 are placed on the redistribution layer 204.

[0089] refer to Figure 11 ,right Figure 10 The resulting semiconductor package structure is flipped and cut to form a single semiconductor package structure.

[0090] Although the present invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of the invention. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation of the invention and actual implementation due to variables in the manufacturing process, etc. Other embodiments of the invention may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims

1. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure includes: Optoelectronic integrated chips; The second wafer is disposed above the optoelectronic integrated chip; The first support structure is disposed below the optoelectronic integrated chip; A redistribution layer is disposed below the first support structure, and the first support structure is electrically connected to the optoelectronic integrated chip and the redistribution layer.

2. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure further includes: A first through-silicon via (TSV) structure is disposed inside the optoelectronic integrated chip.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first through-silicon via structure penetrates the optoelectronic integrated chip.

4. The semiconductor packaging structure according to claim 2, characterized in that, The semiconductor packaging structure further includes: A second through-silicon via structure is disposed inside the first support structure.

5. The semiconductor packaging structure according to claim 4, characterized in that, The second through-silicon via structure penetrates the first support structure.

6. The semiconductor packaging structure according to claim 4, characterized in that, The first through-silicon via (TSV) structure and the second TSV structure are stacked in alignment.

7. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure further includes: An optical waveguide is disposed within the redistribution layer.

8. The semiconductor packaging structure according to claim 4, characterized in that, The vertical projections of the first and second through-silicon via structures fall within the vertical projection range of the second wafer.

9. The semiconductor packaging structure according to claim 4, characterized in that, The optoelectronic integrated chip is in direct contact with the first support structure, and the first through-silicon via structure is in contact with the second through-silicon via structure. Direct contact.

10. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure further includes: A printed circuit board is disposed below the redistribution layer.

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