A multilayer board and an LCP antenna
By setting layer offset test points on the substrate of the multilayer board and performing low-resistance measurements, the problem of scrapping caused by abnormal layer offset of the multilayer board was solved, the cost was reduced and the performance of the LCP antenna was guaranteed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUNWAY COMM JIANGSU CO LTD
- Filing Date
- 2025-05-29
- Publication Date
- 2026-06-02
AI Technical Summary
Existing multilayer boards suffer from layer misalignment during full inspection after electronic components are mounted, leading to high scrap costs and the electronic components being scrapped along with the boards.
Layer misalignment test points are set on each substrate layer of the multilayer board. Combined test points are formed by stacking and pressing. The resistance value is detected by low resistance measurement. After the interlayer alignment deviation is qualified, electronic components are installed to reduce the scrap of defective products.
It effectively reduces the scrap cost of multilayer boards while ensuring the performance of LCP antennas, and is suitable for all multilayer board structures.
Smart Images
Figure CN224319579U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of multilayer board deflection technology, and in particular to a multilayer board with a deflection detection and anti-deflection function, which can also reduce scrap costs, and an LCP antenna containing the multilayer board. Background Technology
[0002] In the design of LCP antennas (LCP, Liquid Crystal Polymer), the layer offset of the multilayer board (which can also be understood as the misalignment between layers) has a significant impact on the performance of the LCP antenna.
[0003] In existing technologies, after the electronic components are mounted on the traditional multilayer board (i.e., SMT process; SMT stands for Surface Mount Technology), and before entering the subsequent electronic component testing stage, the multilayer board is tested for layer misalignment (i.e., the traditional multilayer board assembly test to prevent layer misalignment).
[0004] Generally speaking, in order to ensure the performance of LCP antennas, manufacturers usually use professional testing equipment to measure and differentiate them; and manufacturers test 100% of the multilayer boards, rather than sampling them.
[0005] However, traditional multilayer boards undergo 100% testing after electronic components are mounted. If a layer misalignment is found during testing, the board will be scrapped. In this case, the electronic components mounted on the unqualified traditional multilayer board will also be scrapped. Therefore, the traditional multilayer board assembly testing and anti-layer misalignment scheme has the drawback of extremely high scrap costs. Utility Model Content
[0006] The multilayer board and LCP antenna provided by this utility model aim to solve the technical problem of high scrapping cost of existing multilayer boards.
[0007] In a first aspect, this utility model provides a multilayer board. The multilayer board includes:
[0008] At least two different substrates, each of which has a layer offset test point at a preset position;
[0009] The multilayer board is formed by laminating and pressing at least two different substrates, at which time the layer offset test points of each substrate are in contact with each other to form a combined test point.
[0010] When the actual resistance value of the combined test point is not greater than the preset resistance threshold, the interlayer alignment deviation between at least two different substrates is in a qualified state.
[0011] Electronic components can be mounted on the multilayer board when the interlayer alignment deviation between at least two different substrates is acceptable.
[0012] In some embodiments, the formula for calculating the resistance threshold is: R Th =RAvg + 2.5×σ, where R Th R is the resistance threshold. Avg σ is the average resistance of the combined test points of at least 100 qualified multilayer boards, and σ is the standard deviation of the combined test points of at least 100 qualified multilayer boards.
[0013] In some embodiments, the substrate further includes:
[0014] Copper paste, at least one LCP layer and at least one copper layer;
[0015] The LCP layer is coated on the surface of the copper layer, and two adjacent copper layers can be separated by one LCP layer;
[0016] The copper layers can be made conductive through the copper paste.
[0017] In some embodiments, blind vias are formed on the substrate, and the copper paste is filled into the blind vias;
[0018] The blind hole has a first depth in its axial direction, and the copper paste has a first height in the axial direction of the blind hole;
[0019] Wherein, the first height is greater than the first depth.
[0020] In some embodiments, the substrate is a single-sided panel, the single-sided panel including an LCP layer and a copper layer, and the LCP layer is coated on the surface of the copper layer;
[0021] The blind via penetrates the LCP layer until the copper layer is exposed.
[0022] In some embodiments, the substrate is a double-sided panel, which includes an LCP layer and two copper layers, and the two copper layers are respectively disposed on the top and bottom surfaces of the LCP layer opposite to each other in the axial direction of the blind via.
[0023] In some embodiments, the two copper layers include a first copper layer and a second copper layer, wherein the first copper layer is located on the top surface of the LCP layer and the second copper layer is located on the bottom surface of the LCP layer;
[0024] The blind via penetrates the first copper layer and the LCP layer until the second copper layer is exposed.
[0025] In some embodiments, the blind hole has an open end and a closed end opposite each other in its axial direction;
[0026] The blind hole has a first radial dimension at its open end and a second radial dimension at its closed end;
[0027] Wherein, the first radial dimension is greater than the second radial dimension, and the generatrix of the blind hole is inclined to the axis of the blind hole.
[0028] In some embodiments, the layer offset test point and / or the combined test point are pads.
[0029] Secondly, this utility model also provides an LCP antenna. The LCP antenna includes:
[0030] The antenna body and the aforementioned multilayer board;
[0031] The multilayer plate can support the antenna body.
[0032] At least one beneficial effect of the multilayer board and LCP antenna provided by this utility model embodiment is: a novel multilayer board and an LCP antenna including the multilayer board are proposed. The multilayer board includes at least two different substrates. Each substrate has a layer offset test point at a preset position. The multilayer board is formed after the at least two different substrates are stacked and pressed. At this time, the layer offset test points of each substrate are in contact with each other to form a combined test point. When the actual resistance value of the combined test point is not greater than a preset resistance threshold, the interlayer alignment deviation between the at least two different substrates is in a qualified state. When the interlayer alignment deviation between the at least two different substrates is in a qualified state, electronic components can be installed on the multilayer board. This design can effectively reduce the scrap cost of the multilayer board and is also applicable to all multilayer board structures. Attached Figure Description
[0033] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are designated as the same elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0034] Figure 1 This is a front view of substrate L1 in different substrates;
[0035] Figure 2 This is a front view schematic diagram of substrate L2 in different substrates;
[0036] Figure 3 This is a front view schematic diagram of substrate L3 in different substrates;
[0037] Figure 4This is a front view schematic diagram of substrate L4 in different substrates;
[0038] Figure 5 A schematic diagram of a multilayer board with acceptable layer misalignment;
[0039] Figure 6 This is a front view schematic diagram of a multilayer board with acceptable layer misalignment.
[0040] Figure 7 This is a schematic diagram of a multilayer board with a layer misalignment.
[0041] Figure 8 This is a front view schematic diagram of a multilayer board with abnormal layer misalignment;
[0042] Figure 9 This is a schematic diagram of the material cutting process in the single-sided panel manufacturing process.
[0043] Figure 10 This is a schematic diagram of the lamination process in the single-sided panel manufacturing process.
[0044] Figure 11 A schematic diagram of circuit fabrication in the single-sided PCB manufacturing process;
[0045] Figure 12 This is a schematic diagram of laser drilling in the single-sided panel manufacturing process.
[0046] Figure 13 This is a schematic diagram of copper paste printing in the single-sided board manufacturing process.
[0047] Figure 14 This is a schematic diagram of the baking and film removal process in the single-sided panel manufacturing process.
[0048] Figure 15 This is a schematic diagram of the material cutting process in the double-sided panel manufacturing process.
[0049] Figure 16 A schematic diagram of circuit fabrication in the double-sided PCB manufacturing process;
[0050] Figure 17 This is a schematic diagram of the lamination process in the double-sided panel manufacturing process.
[0051] Figure 18 This is a schematic diagram of laser drilling in the double-sided panel manufacturing process.
[0052] Figure 19 This is a schematic diagram of copper paste printing in the double-sided board manufacturing process.
[0053] Figure 20 This is a schematic diagram of the baking and film removal process in the double-sided panel manufacturing process.
[0054] Figure 21 This is a schematic diagram of the overlay of single-sided and double-sided panels;
[0055] Figure 22 This is a schematic diagram of the lamination process for single-sided and double-sided panels.
[0056] Figure label:
[0057] 100. Multilayer board; 1. Substrate; 11. Copper paste; 12. LCP layer; 13. Copper layer; 101. Layer deviation test point; 102. Blind via; 103. Single-sided board; 104. Double-sided board; 1011. Combined test point; 1021. Axial direction; 1022. Open end; 1023. Closed end; 1024. Busbar; 1041. First copper layer; 1042. Second copper layer;
[0058] 200. Covering film;
[0059] 300. Scraper. Detailed Implementation
[0060] The present invention will now be described in detail with reference to specific embodiments. It should be emphasized that the following description is merely exemplary and is not intended to limit the scope and application of the present invention.
[0061] It should be noted that, unless otherwise explicitly specified and limited, the terms "axial," "relative," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. The terms "installation," "fitting," "connection," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixing" can be bolt fixing, snap-fit fixing, or glue fixing. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature. "A plurality" or "several" means two or more. In addition, "and / or" includes any and all combinations of one or more of the related listed items. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.
[0062] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0063] In this embodiment, the specific implementation of the "multilayer board and LCP antenna" is not limited. Those skilled in the art can selectively use any suitable implementation method according to actual needs.
[0064] Figure 1 This is a front view schematic diagram of substrate L1 in different substrates. Figure 2 This is a front view schematic diagram of substrate L2 in different substrates. Figure 3 This is a front view schematic diagram of substrate L3 in different substrates.
[0065] Figure 4 This is a front view schematic diagram of substrate L4 in different substrates. Figure 5 This is a schematic diagram of a multilayer board with acceptable layer misalignment. Figure 6 This is a front view schematic diagram of a multilayer board with acceptable layer misalignment. Figure 7 This is a schematic diagram of a multilayer board with abnormal layer skewing. Figure 8 This is a front view schematic diagram of a multilayer board with abnormal layer misalignment.
[0066] Please see Figures 1-8 The multilayer board 100 includes at least two different substrates 1.
[0067] Different substrates can be understood as having different lines etched on them, or as having different shapes.
[0068] When at least two different substrates are combined (combination can be understood as stacking and lamination, or as stacking and lamination), abnormal layer misalignment usually occurs due to issues such as expansion and contraction (i.e., dimensional changes in materials due to factors such as temperature and humidity) and combination accuracy (i.e., the precision of alignment between each substrate layer). In other words, abnormal layer misalignment means that due to expansion and contraction or combination accuracy issues, the substrate layers are not aligned as expected after combination. In addition, abnormal layer misalignment can have a significant impact on the performance of LCP antennas. For example, if any of the at least two different substrates has a circuit opening design (the substrate with the circuit opening design is called the first substrate), when an abnormal layer misalignment occurs after the combination of at least two different substrates, the non-opening circuits on the first substrate may partially cover the circuits on other substrates due to the abnormal layer misalignment, thereby changing the preset electrical connection path or introducing additional parasitic capacitance, parasitic inductance, etc., which in turn causes changes in the transmission characteristics of the LCP antenna's radio frequency signal (such as signal attenuation, reflection, interference, etc.), ultimately causing abnormal radio frequency signals of the LCP antenna.
[0069] A line opening refers to an area not covered by a line. Line openings may be designed to allow electrical connections to other substrate layers or to avoid signal interference.
[0070] LCP (Liquid Crystal Polymer) is a fully aromatic liquid crystal polyester polymer material composed of rigid polymer chain structure. LCP has advantages such as low dielectric loss, high frequency adaptability, and bendability. LCP antennas are high-performance antennas made of LCP material.
[0071] Each substrate 1 has a layer offset test point 101 set at a preset position.
[0072] In addition, at least two different substrates 1 are laminated and pressed to form a multilayer board 100. At this time, the layer offset test points 101 of each substrate 1 are in contact with each other to form a combined test point 1011.
[0073] Furthermore, when the actual resistance value of the combined test point 1011 is not greater than the preset resistance threshold, the interlayer alignment deviation between at least two different substrates 1 is in a qualified state.
[0074] In this embodiment of the application, when the interlayer alignment deviation between at least two different substrates 1 is in a qualified state, electronic components can be installed on the multilayer board 100.
[0075] In summary, this multilayer board 100 adopts the method of adding layer deviation test points 101 and using low resistance measurement to detect defective products and keep them on the blank board (the blank board is a multilayer board without electronic components), thereby reducing the scrap cost of this multilayer board 100.
[0076] Specifically, low resistance measurement refers to measuring the resistance value at a specific point in a circuit using precision instruments (such as a micro-ohmmeter or a four-wire tester); for example, measuring the resistance value at a test point on a multilayer board assembly.
[0077] In some embodiments, the formula for calculating the resistance threshold is: R Th =R Avg +2.5×σ, where R Th R is the resistance threshold. Avg σ is the average resistance of the combined test points of at least 100 qualified multilayer boards, and σ is the standard deviation of the combined test points of at least 100 qualified multilayer boards.
[0078] To further explain, in obtaining R Avg When calculating σ, at least 100 qualified multilayer boards need to be collected to ensure the reliability of the σ estimation, because a small sample size will lead to large fluctuations in σ, thus affecting R. Th The accuracy of this information can affect the determination of whether the layer misalignment of a multilayer board is acceptable.
[0079] In summary, this multilayer board 100 uses the low resistance of the empty board (an empty board is a multilayer board without electronic components mounted) to determine the degree of interlayer alignment deviation (i.e., layer misalignment).
[0080] Figure 9 This is a schematic diagram of the material cutting process in the single-sided panel manufacturing process. Figure 10 This is a schematic diagram of the lamination process in the single-sided panel manufacturing process. Figure 11 This is a schematic diagram of the circuit fabrication process in a single-sided PCB manufacturing process. Figure 12 This is a schematic diagram of laser drilling in the single-sided panel manufacturing process. Figure 13 This is a schematic diagram of copper paste printing in the single-sided board manufacturing process. Figure 14 This is a schematic diagram of the baking and film removal process in the single-sided panel manufacturing process.
[0081] Figure 15 This is a schematic diagram of the material cutting process in the double-sided panel manufacturing process. Figure 16 This is a schematic diagram of the circuit fabrication process in the double-sided PCB manufacturing process. Figure 17 This is a schematic diagram of the lamination process in the double-sided panel manufacturing process. Figure 18 This is a schematic diagram of laser drilling in the double-sided panel manufacturing process. Figure 19 This is a schematic diagram of copper paste printing in the double-sided board manufacturing process. Figure 20 This is a schematic diagram of the baking and film removal process in the double-sided panel manufacturing process. Figure 21 This is a schematic diagram of the overlay of single-sided and double-sided panels. Figure 22 This is a schematic diagram of the lamination process for single-sided and double-sided panels.
[0082] In some embodiments, such as Figure 5 , Figure 7 as well as Figures 9-22 As shown, substrate 1 further includes: copper paste 11, at least one LCP layer 12 and at least one copper layer 13.
[0083] The LCP layer 12 is coated on the surface of the copper layer 13, and two adjacent copper layers 13 can be separated by an LCP layer 12.
[0084] In addition, the copper layers 13 can be connected by copper paste 11.
[0085] In some embodiments, combined with Figures 9-22 It can be seen that a blind hole 102 is formed on the substrate 1, and copper paste 11 is filled in the blind hole 102.
[0086] It should be noted that the blind hole 102 has a first depth in its axial direction 1021, and the copper paste 11 has a first height in the axial direction 1021 of the blind hole 102.
[0087] It is understandable that the first height is greater than the first depth.
[0088] In some embodiments, according to Figures 9-14 As can be seen, the substrate 1 is a single-sided panel 103, which includes an LCP layer 12 and a copper layer 13, and the LCP layer 12 is coated on the surface of the copper layer 13.
[0089] Specifically, the blind via 102 penetrates the LCP layer 12 until the copper layer 13 is exposed.
[0090] Combination Figures 9-14 Here is a detailed description of the process flow of the single-sided PCB 103: First, the LCP layer 12 is coated onto the surface of the copper layer 13; this process is called blanking. Then, the cover film 200 is placed on the surface of the LCP layer 12 away from the copper layer 13; this process is called lamination. Next, circuits are etched on the copper layer 13; this process is called circuit fabrication. Immediately afterward, blind vias 102 are laser-drilled on the cover film 200 and the LCP layer; this process is called laser drilling. Then, copper paste 11 is filled into the blind vias 102 using a scraper 300. At this time, the copper paste 11 is flush with the surface of the cover film 200 away from the LCP layer 12; this process is called copper paste printing. Finally, the copper paste 11, LCP layer 12, copper layer 13, and cover film 200 are baked, and the cover film 200 is peeled off after baking; this process is called baking and peeling.
[0091] In some embodiments, by Figures 15-20 It can be seen that the substrate 1 is a double-sided panel 104, which includes an LCP layer 12 and two copper layers 13. The two copper layers 13 are respectively disposed on the top and bottom surfaces of the LCP layer 12 opposite to each other in the axial direction 1021 of the blind hole 102.
[0092] In some embodiments, refer to Figures 15-20 It is known that the two copper layers 13 include a first copper layer 1041 and a second copper layer 1042. The first copper layer 1041 is located on the top surface of the LCP layer 12, and the second copper layer 1042 is located on the bottom surface of the LCP layer 12.
[0093] It should be noted that the blind via 102 penetrates the first copper layer 1041 and the LCP layer 12 until the second copper layer 1042 is exposed.
[0094] Combination Figures 15-20Here is a detailed description of the manufacturing process of the double-sided PCB 104: First, the first copper layer 1041 and the second copper layer 1042 are respectively disposed on the top and bottom surfaces of the LCP layer 12 opposite to each other on the axial direction 1021 of the blind via 102. This process is called blanking. Then, circuits are etched on the first copper layer 1041. This process is called circuit fabrication. Afterward, a cover film 200 is disposed on the top surface of the LCP layer 12 and covers the first copper layer 1041. This process is called lamination. Next, the cover film 200 and the first copper layer 1041 are laminated. Laser drilling is performed on the copper layer 1041 and the LCP layer 12 to create blind holes 102. This process is called laser drilling. Then, copper paste 11 is filled into the blind holes 102 using a scraper 300. At this time, the copper paste 11 is flush with the surface of the cover film 200 away from the first copper layer 1041. This process is called copper paste printing. Finally, the copper paste 11, LCP layer 12, first copper layer 1041, second copper layer 1042 and cover film 200 are baked. After baking, the cover film 200 is peeled off. This process is called baking and peeling.
[0095] Combination Figure 14 , Figures 20-22 It can be seen that single-sided panel 103 and double-sided panel 104 can form a multi-layer board structure after being laminated and pressed.
[0096] In some embodiments, please refer to Figures 9-20 The blind hole 102 has an open end 1022 and a closed end 1023 on its axial direction 1021.
[0097] The blind hole 102 has an open end 1022 with a first radial dimension and a closed end 1023 with a second radial dimension.
[0098] In addition, the first radial dimension is larger than the second radial dimension, and the generatrix 1024 of the blind hole 102 is inclined to the axis of the blind hole 102.
[0099] In some embodiments, such as Figures 1-8 As shown, layer offset test point 101 and / or combined test point 1011 are pads.
[0100] Please see Figures 1-22 The LCP antenna includes: an antenna body and the aforementioned multilayer board 100.
[0101] Among them, the multilayer board 100 can support the antenna body.
[0102] In summary, this utility model embodiment provides a multilayer board and an LCP antenna. The multilayer board includes at least two different substrates, each substrate having a layer offset test point at a preset position. The at least two different substrates are laminated and pressed together to form the multilayer board. At this time, the layer offset test points of each substrate are in contact with each other to form a combined test point. When the actual resistance value of the combined test point is not greater than a preset resistance threshold, the interlayer alignment deviation between the at least two different substrates is acceptable. When the interlayer alignment deviation between the at least two different substrates is acceptable, electronic components can be installed on the multilayer board. This design can effectively reduce the scrap cost of this multilayer board and is applicable to all multilayer board structures. Therefore, the multilayer board and LCP antenna provided by this utility model embodiment have certain novelty compared to traditional multilayer boards and LCP antennas.
[0103] The above description, in conjunction with specific / preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all of these fall within the protection scope of the present invention.
Claims
1. A multilayer board, characterized in that, include: At least two different substrates, each of which has a layer offset test point at a preset position; The multilayer board is formed by laminating and pressing at least two different substrates, at which time the layer offset test points of each substrate are in contact with each other to form a combined test point. When the actual resistance value of the combined test point is not greater than the preset resistance threshold, the interlayer alignment deviation between at least two different substrates is in a qualified state. Electronic components can be mounted on the multilayer board when the interlayer alignment deviation between at least two different substrates is acceptable.
2. The multilayer board according to claim 1, characterized in that, The formula for calculating the resistance threshold is: R Th =R Avg +2.5×σ, where R Th R is the resistance threshold. Avg σ is the average resistance of the combined test points of at least 100 qualified multilayer boards, and σ is the standard deviation of the combined test points of at least 100 qualified multilayer boards.
3. The multilayer board according to claim 1, characterized in that, The substrate further includes: Copper paste, at least one LCP layer and at least one copper layer; The LCP layer is coated on the surface of the copper layer, and two adjacent copper layers can be separated by one LCP layer; The copper layers can be made conductive through the copper paste.
4. The multilayer board according to claim 3, characterized in that, The substrate has blind holes, and the copper paste fills the blind holes; The blind hole has a first depth in its axial direction, and the copper paste has a first height in the axial direction of the blind hole; Wherein, the first height is greater than the first depth.
5. The multilayer board according to claim 4, characterized in that, The substrate is a single-sided panel, which includes an LCP layer and a copper layer, and the LCP layer is coated on the surface of the copper layer. The blind via penetrates the LCP layer until the copper layer is exposed.
6. The multilayer board according to claim 4, characterized in that, The substrate is a double-sided panel, which includes an LCP layer and two copper layers, and the two copper layers are respectively disposed on the top and bottom surfaces of the LCP layer opposite to each other in the axial direction of the blind via.
7. The multilayer board according to claim 6, characterized in that, The two copper layers include a first copper layer and a second copper layer, wherein the first copper layer is located on the top surface of the LCP layer and the second copper layer is located on the bottom surface of the LCP layer; The blind via penetrates the first copper layer and the LCP layer until the second copper layer is exposed.
8. The multilayer board according to any one of claims 4-7, characterized in that, The blind hole has an open end and a closed end opposite each other in its axial direction; The blind hole has a first radial dimension at its open end and a second radial dimension at its closed end; Wherein, the first radial dimension is greater than the second radial dimension, and the generatrix of the blind hole is inclined to the axis of the blind hole.
9. The multilayer board according to any one of claims 1-7, characterized in that, The layer offset test points and / or the combined test points are solder pads.
10. An LCP antenna, characterized in that, include: The antenna body and the multilayer board as described in any one of claims 1-9; The multilayer plate can support the antenna body.