A battery piece structure and a battery assembly
By setting staggered thinned and non-thinned regions on the silicon substrate of the solar cell, the passivation layer distribution is optimized, which solves the problems of series resistance loss and optical loss in the current transmission process of large-size solar cells, and improves the conversion efficiency of solar cells and the performance of modules.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HUAIAN JIETAI NEW ENERGY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-06-05
AI Technical Summary
While large-size solar cells increase module power, they also increase series resistance losses during current transmission, leading to reduced encapsulation efficiency. Existing slicing processes result in excessively thick passivation layers, causing problems such as optical parasitic absorption and current loss.
Interleaved thinning and non-thinning regions are set on the silicon substrate of the solar cell. The dielectric layer and doped polycrystalline silicon layer are thinned in some areas. By combining thinning methods in different directions, the distribution of the passivation layer is optimized to form contact areas and thinning areas to reduce optical losses.
By reducing optical losses in the passivation film, the conversion efficiency of the solar cells is improved, current transmission is optimized, and the performance of the solar module is enhanced.
Smart Images
Figure CN224329857U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of solar cells, and in particular to a cell structure and a cell module. Background Technology
[0002] Solar cells are the basic building blocks of solar cells, directly converting sunlight into electrical energy. With advancements in large-size silicon wafer technology, crystalline silicon solar cells are becoming increasingly larger, enabling higher output power for individual modules. However, since the current generated by a solar cell is related to its area, larger cells, while increasing module power, also increase the module current, significantly increasing series resistance loss (IR) during current transmission and reducing the module's encapsulation efficiency. To reduce IR loss, a common method is to cut a single solar cell into half-cells and then connect them in series or parallel to form the module.
[0003] For solar cells, the conventional slicing process involves cutting the entire cell into the required slices using a laser after cell fabrication, and then depositing a passivation layer on the cut surfaces for passivation treatment. Existing technologies also include a process of slicing before passivation; that is, before depositing the passivation layer during cell fabrication, the entire cell is first cut, and then the passivation layer is deposited, so that the passivation layer covers the front, back, sides, and cut surfaces of the silicon wafer.
[0004] However, for the battery cells obtained by the two cutting methods mentioned above, a dielectric layer and a relatively thick poly layer are constructed on the back of the battery. Although the relatively thick poly layer helps to improve the battery performance to some extent, it also brings problems such as excessive optical parasitic absorption and current loss. Utility Model Content
[0005] In order to reduce optical loss caused by a thick passivation film layer at the edge of the solar cell and improve the conversion efficiency of the solar cell, this application provides a solar cell structure and a solar cell module.
[0006] The technical solution adopted in this application is as follows:
[0007] A battery cell structure includes a silicon substrate, wherein the back side of the silicon substrate has alternating thinned regions and non-thinned regions along a first direction;
[0008] The non-thinning region is provided with a dielectric layer, a doped polysilicon layer and a passivation layer in sequence from the side closest to the silicon substrate to the side furthest from the silicon substrate. The thinning region is provided with a passivation layer on the silicon substrate. A back metal electrode is connected to a portion of the non-thinning region to form a contact area, and a thinning region is provided between two adjacent contact areas. A thinning region is provided between the contact area close to the side of the silicon substrate in the first direction and at least one side.
[0009] Optionally, the thinned region does not penetrate the first directional side of the silicon substrate.
[0010] Optionally, the thinning region is in communication with the first directional side of the silicon substrate.
[0011] Optionally, the thinning region does not extend through a third direction along the silicon substrate.
[0012] Optionally, the thinning region is continuous along a third direction of the silicon substrate.
[0013] Optionally, the thickness of the thinned region along the second direction is thinner than the thickness of the non-thinned region along the second direction.
[0014] Optionally, the dielectric layer has a thickness of 0.5~20nm along the second direction, the doped polysilicon layer has a thickness of 50~400nm along the second direction, and the passivation layer has a thickness of 5~100nm along the second direction.
[0015] Optionally, the doped polycrystalline silicon layer is in ohmic contact with the back metal electrode; the silicon substrate also has a front side opposite to the back side, and the front side of the silicon substrate is provided with an emitter and a passivation layer from the inside to the outside, and the front side of the silicon substrate is also provided with a front metal electrode, and the front metal electrode forms an ohmic contact with the emitter.
[0016] Optionally, the silicon substrate also has a front side opposite to the back side, and the front side of the silicon substrate is provided with a passivation layer;
[0017] The doped polysilicon layer includes P-type doped polysilicon layers and N-type doped polysilicon layers arranged alternately along a first direction; the back metal electrode includes a metal positive electrode and a metal negative electrode, the metal positive electrode and the P-type doped polysilicon layer forming an ohmic contact, and the metal negative electrode and the N-type doped polysilicon layer forming an ohmic contact.
[0018] Optionally, the passivation layer comprises aluminum oxide and / or silicon nitride, or an aluminum oxide-silicon nitride stack.
[0019] This application also provides a battery assembly including the above-described battery cell structure.
[0020] The battery cell structure of this application has the following beneficial effects:
[0021] By setting a thinning region, the doped polycrystalline silicon layer and dielectric layer on the silicon substrate that are not in contact with the metal electrode are thinned. Furthermore, a thinning region is set between the contact area and the side near the first direction side, which helps to reduce optical loss caused by a thick passivation film layer at the edge of the cell and improves the conversion efficiency of the cell. Attached Figure Description
[0022] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the battery cell structure in Embodiment 1 of this application;
[0024] Figure 2 This is a schematic diagram of the battery cell structure in Embodiment 2 of this application;
[0025] Figure 3 This is a schematic diagram of the battery cell structure in Embodiment 3 of this application;
[0026] Figure 4 This is a schematic diagram of the battery cell structure in Embodiment 4 of this application;
[0027] Figure 5 This is a schematic diagram of the battery cell structure of Comparative Example 1 of this application;
[0028] Figure 6 This is a schematic diagram of the battery cell structure of Comparative Example 2 of this application;
[0029] Figure 7 This is a schematic diagram of the battery cell structure of Comparative Example 3 of this application;
[0030] Explanation of reference numerals in the attached figures: 1. Silicon substrate; 11. Front side; 12. Back side; 13. Thinned region; 14. Non-thinned region; 2. Emitter; 3. Passivation layer; 4. Front metal electrode; 5. Dielectric layer; 6. Doped polysilicon layer; 61. P-type doped polysilicon layer; 62. N-type doped polysilicon layer; 7. Back metal electrode; 71. Positive metal electrode; 72. Negative metal electrode. Detailed Implementation
[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.
[0032] refer to Figure 1 In this application, the first direction is the horizontal direction, the second direction is the vertical direction, and the third direction is the direction that is perpendicular to the paper and perpendicular to both the first and second directions.
[0033] A solar cell structure includes a silicon substrate 1, wherein the back surface 12 of the silicon substrate 1 has alternating thinned regions 13 and non-thinned regions 14 along a first direction;
[0034] The non-thinning region 14 is provided with a dielectric layer 5, a doped polysilicon layer 6 and a passivation layer 3 sequentially from the side closest to the silicon substrate to the side furthest from the silicon substrate. The thinning region 13 is provided with a passivation layer 3 on the silicon substrate 1. A back metal electrode 7 is connected to a portion of the non-thinning region 14 to form a contact area, and a thinning region 13 is provided between two adjacent contact areas. A thinning region 13 is provided between the contact area close to the side of the silicon substrate 1 in the first direction and at least one side.
[0035] The battery cell structure of the present invention is referenced. Figure 1 The thinning region 13 includes a reduction in thickness along the second direction, namely, the removal of the doped polycrystalline silicon layer 6 and the dielectric layer 5, and a reduction in width along the first direction, namely, a non-contact region that does not contact the metal electrode. By defining the thinning region 13 between the contact region located at the end of the first direction and the side edge of the end of the first direction, the present invention helps to reduce optical losses caused by the thick passivation film at the edge of the solar cell.
[0036] Specifically, in one embodiment of this application, the thinning region 13 does not penetrate the first directional side edge of the silicon substrate 1. (See reference...) Figure 1 The first side of the silicon substrate is not thinned, and there is a thinned area between the side and the contact area, that is, the thinned area is not connected to the first side.
[0037] Specifically, in one embodiment of this application, the thinning region 13 penetrates the first directional side edge of the silicon substrate 1. (See reference...) Figure 2 The silicon substrate is thinned directly to the right along the left side region of the first direction, that is, the thinning is between the end contact area and the side, so as to achieve the connection between the thinned area and the side of the first direction.
[0038] Specifically, as one embodiment of this application, the thinning region 13 does not extend through the silicon substrate in a third direction.
[0039] Specifically, as one embodiment of this application, the thinning region 13 is connected in a third direction along the silicon substrate.
[0040] When thinning the portion that is not in contact with the metal electrode, it is possible to achieve full thinning (i.e., through-through) along a third direction, reducing the degradation of electrical performance caused by excessively thick polysilicon layers at the edges; alternatively, the portion in contact with the busbar can be left unthinned (i.e., not through-through), which can reduce the degradation effect to a certain extent and also reduce the problem of poor connection and conductivity caused by poor soldering in some locations.
[0041] Specifically, as one embodiment of this application, the thickness of the thinned region along the second direction is thinner than the thickness of the non-thinned region along the second direction.
[0042] Specifically, in one embodiment of this application, the dielectric layer 5 has a thickness of 0.5~20nm along the second direction, the doped polysilicon layer 6 has a thickness of 50~400nm along the second direction, and the passivation layer 3 has a thickness of 5~100nm along the second direction.
[0043] Specifically, as one embodiment of this application, the cell structure is a TOPCon solar cell, which further includes: the doped polycrystalline silicon layer 6 in ohmic contact with the back metal electrode 7; the silicon substrate 1 also has a front side 11 opposite to the back side 12, and the front side 11 of the silicon substrate 1 is provided with an emitter 2 and a passivation layer 3 from the inside to the outside, and the front side 11 of the silicon substrate 1 is also provided with a front metal electrode 4, and the front metal electrode 4 forms an ohmic contact with the emitter 2.
[0044] Specifically, as one embodiment of this application, the method for preparing the TOPCon solar cell includes the following steps:
[0045] (1) Silicon wafer cleaning and texturing;
[0046] (2) Boron doping is performed on the silicon wafer to form a front / back boron doped layer and a BSG layer;
[0047] (3) Remove the boron-doped layer and BSG layer on the back side, polish the back side, and form a dielectric layer, a phosphorus-doped polysilicon layer and a mask layer on the back side of the silicon wafer in sequence.
[0048] (4) Laser patterning removes the local mask layer, and then chemical etching is used to remove the doped polysilicon layer and tunnel oxide layer under the removed local mask layer to form a thinning area. The part that is not removed forms a non-thinning area. The back side of the silicon wafer has the thinning area and non-thinning area alternately arranged.
[0049] (5) Laser sectioning;
[0050] (6) Remove the mask layer and BSG from the sliced silicon wafer, and perform RCA cleaning on the exposed area of the silicon wafer;
[0051] (7) Form passivation layers on the front and back sides of the silicon wafer;
[0052] (8) Screen print metal electrodes on the front and back sides of the silicon wafer. The front metal electrode forms an ohmic contact with the front boron doped layer, and the back metal electrode forms an ohmic contact with the doped polycrystalline silicon layer.
[0053] Specifically, as one embodiment of this application, reference is made to... Figure 4The cell structure is a TBC solar cell, and its structure also includes: the silicon substrate 1 also has a front side 11 opposite to the back side 12, and the front side 11 of the silicon substrate 1 is provided with a passivation layer 3.
[0054] The doped polysilicon layer 6 includes P-type doped polysilicon layers 61 and N-type doped polysilicon layers 62 arranged alternately along a first direction; the back metal electrode 7 includes a metal positive electrode 71 and a metal negative electrode 72, the metal positive electrode 71 and the P-type doped polysilicon layer 61 forming an ohmic contact, and the metal negative electrode 72 and the N-type doped polysilicon layer 62 forming an ohmic contact.
[0055] Specifically, as one embodiment of this application, the method for preparing the TBC solar cell includes the following steps:
[0056] (1) Silicon wafer pretreatment: Double-sided polishing of the silicon wafer;
[0057] (2) First deposition and diffusion: A first tunneling oxide layer and a first polysilicon layer are deposited on the back side of the silicon wafer, and boron doping is performed to form a P-type doped polysilicon layer, and a BSG layer is formed on the surface of the P-type doped polysilicon layer.
[0058] (3) First laser treatment: Laser treatment is used to process a portion of the back side of the silicon wafer, including laser excavation of the phosphorus doped region, the PN region junction region, and removal of the BSG layer from the non-metallic contact area of the P-type doped polysilicon layer.
[0059] (4) Etching process: The back side of the silicon wafer is etched using an alkaline solution;
[0060] (5) Second deposition and diffusion: A second tunneling oxide layer and a second polysilicon layer are deposited on the back side of the silicon wafer, and phosphorus doping is performed to form an N-type doped polysilicon layer, and a PSG layer is formed on the surface of the N-type doped polysilicon layer.
[0061] (6) Second laser treatment: The area on the back of the silicon wafer that was not treated by the first laser treatment is treated by laser, including laser scanning of the boron doped area, the PN region junction area and the non-metallic contact area of the N-type doped polysilicon layer to remove the PSG layer.
[0062] (7) Pickling and texturing: Pickling is performed on the silicon wafer. After pickling, texturing is performed on the front side of the silicon wafer.
[0063] (8) Laser sectioning;
[0064] (9) Post-processing: deposit a passivation layer on the silicon wafer surface and screen print electrodes. The metal positive electrode and the P-type doped polysilicon layer form an ohmic contact, and the metal negative electrode and the N-type doped polysilicon layer form an ohmic contact.
[0065] Specifically, as one embodiment of this application, in the preparation method, the laser slicing position is either a thinning region or a non-thinning region.
[0066] Specifically, as one embodiment of this application, the preparation method can also adopt a passivation-then-cutting process, and after cutting, a passivation layer can be deposited on the cut surface.
[0067] Specifically, as one embodiment of this application, the passivation layer includes aluminum oxide and / or silicon nitride, or an aluminum oxide-silicon nitride stack.
[0068] This application also provides a battery assembly including the above-described battery cell structure.
[0069] The structure of the battery cell in this application will be further described below with reference to specific embodiments.
[0070] Example 1
[0071] Reference Figure 1 The silicon substrate 1 is cut along its length in a third direction. The silicon substrate 1 includes a front side 11 and a back side 12 disposed opposite to each other. From the inside out, the front side 11 of the silicon substrate 1 has an emitter 2 (i.e., a boron-doped layer) and a passivation layer 3 sequentially disposed. A front metal electrode 4 is also disposed on the front side 11, forming an ohmic contact with the emitter 2. The back side 12 of the silicon substrate 1 has staggered non-thinning regions 14 and thinning regions 13 along a first direction. The thickness of the thinning regions 13 in a second direction is less than the thickness of the non-thinning regions 14 in the second direction. The thinning regions 13 extend through the silicon substrate 1 in a third direction, meaning they are thinned along the entire third direction.
[0072] The non-thinned region 14 includes a dielectric layer 5, a doped polysilicon layer 6, and a passivation layer 3 sequentially disposed from the side closest to the silicon substrate 1 to the side furthest from the silicon substrate 1. The passivation layer 3 includes an aluminum oxide layer and a silicon nitride layer, with the silicon nitride layer located outside the aluminum oxide layer. The passivation layer 3 covers the front side 11, the back side 12, and the sides of the silicon substrate 1. A back metal electrode 7 is connected to a portion of the non-thinned region 14, and the back metal electrode 7 forms an ohmic contact with the doped polysilicon layer 6, thereby forming a contact region.
[0073] There is a thinning region 13 between two adjacent contact areas, and there is a thinning region 13 between the contact area near the first direction side of the silicon substrate 1 and one of the first direction sides of the silicon substrate 1. The thinning region 13 includes a passivation layer 3 disposed on the silicon substrate 1. The thinning region 13 and the first direction side of the silicon substrate 1 are kept at a certain distance, so that the thinning region 13 and the first direction side of the silicon substrate 1 are not connected.
[0074] The method for fabricating the TOPCon battery cell structure in this embodiment includes the following steps:
[0075] (1) Silicon wafer cleaning and texturing;
[0076] (2) The silicon wafer is placed in a boron doping tube to dope the silicon wafer with boron. The doping temperature is 900℃ and the doping time is 100min. The boron doping source is BBr3 to form a front boron doped layer and a front BSG layer, a back boron doped layer and a back BSG layer.
[0077] (3) Remove the boron doped layer and BSG layer on the back side, polish the back side, and then deposit a dielectric layer with a thickness of 15nm and a polysilicon layer with a thickness of 180nm using vapor phase chemical deposition; place the silicon wafer into a phosphorus doped tube to form a doped polysilicon layer, and at the same time form a PSG mask on the surface of the polysilicon layer.
[0078] (4) Laser patterning to remove local PSG mask, laser wavelength is 1064nm, power is 50W, scanning speed is 10m / s, frequency is 1000kHz; then put the silicon wafer into alkaline solution to remove the doped polysilicon layer and dielectric layer under the PSG mask to form a thinning area, and the part that is not removed forms a non-thinning area.
[0079] (5) Laser slicing: Determine the pre-slicing position along the third direction in the non-thinning area, and laser cut both ends of the pre-slicing position on the silicon wafer. The cutting length is 2.1 mm, the depth is 72.6 μm, the width is 39 μm, the laser power is 50 W, and the spot area is 1000 μm. 2 Then, the pre-sliced area of the silicon wafer is heated by laser, with a laser power of 300W and a spot area of 20mm. 2 The scanning speed is 1 m / s, which causes the silicon wafer to crack and complete the slicing.
[0080] (6) Remove the mask layer and BSG from the sliced silicon wafer, and perform RCA cleaning on the exposed area of the silicon wafer;
[0081] (7) A passivation layer was deposited using atomic layer deposition process. TMA was used as a precursor. A passivation layer with a thickness of 20 nm was deposited at 300 °C and then heated at 400 °C.
[0082] (8) Screen print metal electrodes on the front and back sides of the silicon wafer. The front metal electrode forms an ohmic contact with the front boron doped layer, and the back metal electrode forms an ohmic contact with the doped polycrystalline silicon layer.
[0083] Example 2
[0084] Reference Figure 2 A cell structure differs from Embodiment 1 in that a thinning region 13 is provided between the contact area near the first direction side of the silicon substrate 1 and one of the first direction sides of the silicon substrate 1, and the thinning region 13 is connected to the first direction side of the silicon substrate 1.
[0085] Example 3
[0086] Reference Figure 3 A cell structure differs from Embodiment 1 in that one of the thinning regions 13 is connected to one of the first-direction sides of the silicon substrate 1, while the other thinning region 13 is not connected to the other first-direction side of the silicon substrate 1.
[0087] Example 4
[0088] Reference Figure 4 A battery cell structure is provided with a passivation layer 3 on the front side 11 of a silicon substrate 1; the back side 12 of the silicon substrate 1 has non-thinning regions 14 and thinning regions 13 arranged alternately along a first direction, the thickness of the thinning region 13 in a second direction is less than the thickness of the non-thinning region 14 in the second direction, and the thinning region 13 extends through a third direction of the silicon substrate 1, that is, it is thinned in the third direction.
[0089] The non-thinned region 14 includes a dielectric layer 5, a doped polysilicon layer 6, and a passivation layer 3 sequentially disposed from the side closest to the silicon substrate 1 to the side furthest from the silicon substrate 1. The passivation layer 3 includes an aluminum oxide layer and a silicon nitride layer, with the silicon nitride layer located outside the aluminum oxide layer. The passivation layer 3 covers the front side 11, the back side 12, and the sides of the silicon substrate 1. A back metal electrode 7 is connected to a portion of the non-thinned region 14, and the back metal electrode 7 forms an ohmic contact with the doped polysilicon layer 6, thereby forming a contact region.
[0090] The doped polysilicon layer 6 includes a P-type doped polysilicon layer 61 and an N-type doped polysilicon layer 62 arranged alternately along a first direction; the back metal electrode 7 includes a metal positive electrode 71 and a metal negative electrode 72, the metal positive electrode 71 and the P-type doped polysilicon layer 61 forming an ohmic contact, and the metal negative electrode 72 and the N-type doped polysilicon layer 62 forming an ohmic contact.
[0091] There is a thinning region 13 between two adjacent contact areas, and there is a thinning region 13 between the contact area near the first direction side of the silicon substrate 1 and one of the first direction sides of the silicon substrate 1. The thinning region 13 includes a passivation layer 3 disposed on the silicon substrate 1. The thinning region 13 and the first direction side of the silicon substrate 1 are kept at a certain distance, so that the thinning region 13 and the first direction side of the silicon substrate 1 are not connected.
[0092] The method for preparing the TBC battery cell structure in this embodiment includes the following steps:
[0093] (1) Silicon wafer pretreatment: The silicon wafer is polished on both sides in an alkaline solution;
[0094] (2) First deposition and diffusion: A first tunneling oxide layer with a thickness of 1 nm and a first polycrystalline silicon layer with a thickness of 350 nm are sequentially deposited on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD). Boron doping is then performed on this basis to form a P-type doped polycrystalline silicon layer on the back side, and a borosilicate glass layer (BSG layer) is formed on the surface.
[0095] (3) First laser treatment: First, the phosphorus doped region and the junction region (GAP region) of the PN region are cut by laser in a part of the back of the silicon wafer. The wavelength is 300nm, the frequency is 500kHz, the scanning speed is 50m / s, and the power is 50W. Second, the BSG layer is removed from the non-metallic contact area of the P-type doped polycrystalline silicon layer. The laser wavelength is 200nm, the frequency is 200kHz, the scanning speed is 10m / s, and the power is 10W.
[0096] (4) Etching process: The back side of the silicon wafer is etched using an alkaline solution;
[0097] (5) Second deposition and diffusion: A second tunneling oxide layer with a thickness of 1 nm and a second polysilicon layer with a thickness of 250 nm are sequentially deposited on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD). On this basis, phosphorus doping is performed to form an N-type doped polysilicon layer, and a PSG layer is formed on the surface of the N-type doped polysilicon layer. The second tunneling oxide layer, the second polysilicon layer and the phosphorus-silicon glass layer (PSG layer) formed by phosphorus diffusion in this step are suspended on the P region above the BSG layer formed in step (2).
[0098] (6) Second laser treatment: The area on the back of the silicon wafer that was not treated by the first laser treatment is treated by laser, including laser scanning of the boron doped area and the PN region junction area (GAP area), with a wavelength of 300nm, a frequency of 200kHz, a scanning speed of 10m / s, and a power of 30W; then the PSG layer is removed from the non-metallic contact area of the N-type doped polycrystalline silicon layer, with a laser wavelength of 300nm, a frequency of 100kHz, a scanning speed of 5m / s, and a power of 10W;
[0099] (7) Pickling and texturing: HF is used to remove the PSG layer, BSG layer and oxide layer of the P region, N region and GAP region, and polysilicon layer of the non-metallic contact region to form a thinned region. The part that is not removed forms a non-thinned region. The HF concentration is 1%. The texturing process is used to obtain a textured surface on the front side of the silicon wafer.
[0100] (8) Laser slicing: Determine the pre-slicing position along the third direction in the non-thinning area, and laser cut both ends of the pre-slicing position on the silicon wafer. The cutting length is 2.1 mm, the depth is 72.6 μm, the width is 39 μm, the laser power is 50 W, and the spot area is 1000 μm. 2 Then, the pre-sliced area of the silicon wafer is heated by laser, with a laser power of 300W and a spot area of 20mm. 2The scanning speed of 1 m / s causes the silicon wafer to crack, completing the slicing process.
[0101] (9) Post-processing: Plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a passivation layer with a thickness of 1 nm on the silicon wafer surface; metal positive electrode and metal negative electrode are printed by screen printing respectively. The metal positive electrode and the P-type doped polysilicon layer form an ohmic contact, and the metal negative electrode and the N-type doped polysilicon layer form an ohmic contact.
[0102] Comparative Example 1
[0103] Reference Figure 5 One TOPCon cell structure differs from Example 1 in that it does not have a thinning zone.
[0104] Comparative Example 2
[0105] Reference Figure 6 One TOPCon cell structure differs from Embodiment 1 in that the contact area near the first direction side is not thinned between the contact area and the side.
[0106] Comparative Example 3
[0107] Reference Figure 7 A TBC cell structure differs from Embodiment 1 in that the contact area near the first direction side is not thinned between the contact area and the side.
[0108] The performance of the solar cells of Examples 1-4 and Comparative Examples 1-3 was tested, and the results are shown in Table 1.
[0109] Table 1
[0110]
[0111] As can be seen from the test results in Table 1, by partially thinning the area that is not in contact with the back metal electrode, and simultaneously setting a thinning region between the contact area near the silicon substrate and at least one side, the conversion efficiency of the solar cell can be effectively improved. Furthermore, when the thinning region extends through the side, the thinning effect at the side edge is even better, resulting in superior cell performance; compared to single-sided thinning, double-sided thinning yields superior cell performance. Moreover, as can be seen from the test results of Examples 1-3 and Comparative Examples 1-2, and Examples 4 and Comparative Example 3, the side-thinning structure of this application is applicable to both TOPCon solar cells and TBC solar cells.
[0112] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A battery cell structure, characterized in that: Includes a silicon substrate (1), the back side (12) of the silicon substrate (1) having alternating thinning regions (13) and non-thinning regions (14) along a first direction. The non-thinning region (14) is provided with a dielectric layer (5), a doped polysilicon layer (6) and a passivation layer (3) in sequence from the side close to the silicon substrate (1) to the side away from the silicon substrate (1). The thinning region (13) is provided with a passivation layer (3) on the silicon substrate (1). A back metal electrode (7) is connected to a portion of the non-thinning region (14) to form a contact area, and a thinning region (13) is provided between two adjacent contact areas. A thinning region (13) is provided between the contact area close to the side of the silicon substrate (1) in the first direction and at least one side.
2. The battery cell structure according to claim 1, characterized in that: The thinning region (13) is not connected to the first directional side of the silicon substrate (1).
3. The battery cell structure according to claim 1, characterized in that: The thinning region (13) is connected to the first directional side of the silicon substrate (1).
4. A battery cell structure according to claim 1, characterized in that: The thinning region (13) is not continuous along the third direction of the silicon substrate (1).
5. A battery cell structure according to claim 1, characterized in that: The thinning region (13) is connected in a third direction along the silicon substrate (1).
6. A battery cell structure according to any one of claims 1-5, characterized in that: The thickness of the thinned region (13) along the second direction is thinner than the thickness of the non-thinned region (14) along the second direction.
7. A battery cell structure according to claim 1, characterized in that: The dielectric layer (5) has a thickness of 0.5~20nm along the second direction, the doped polysilicon layer (6) has a thickness of 50~400nm along the second direction, and the passivation layer (3) has a thickness of 5~100nm along the second direction.
8. A battery cell structure according to claim 1, characterized in that: The doped polycrystalline silicon layer (6) is in ohmic contact with the back metal electrode (7); The silicon substrate (1) also has a front side (11) opposite to the back side (12). The front side (11) of the silicon substrate (1) is provided with an emitter (2) and a passivation layer (3) from the inside to the outside. The front side (11) of the silicon substrate (1) is also provided with a front metal electrode (4). The front metal electrode (4) forms an ohmic contact with the emitter (2).
9. A battery cell structure according to claim 1, characterized in that: The silicon substrate (1) also has a front side (11) opposite to the back side (12), and a passivation layer (3) is provided on the front side (11) of the silicon substrate (1). The doped polysilicon layer (6) includes a P-type doped polysilicon layer (61) and an N-type doped polysilicon layer (62) arranged alternately along a first direction; the back metal electrode (7) includes a metal positive electrode (71) and a metal negative electrode (72), the metal positive electrode (71) and the P-type doped polysilicon layer (61) form an ohmic contact, and the metal negative electrode (72) and the N-type doped polysilicon layer (62) form an ohmic contact.
10. A battery assembly, characterized in that, The battery cell structure includes any one of claims 1-9.