A battery equalization circuit based on bidirectional full-bridge resonance and a battery management system

Abstract

The utility model relates to battery equalization technical field, concretely is a kind of battery equalization circuit and battery management system based on bidirectional full-bridge resonance. Transformer T primary winding one end connects inductance L1r, inductance L1p, transformer T primary winding other end connects capacitor C1p, capacitor C1r1, capacitor C1r2, inductance L1p and capacitor C1p connection constitute Lp-Cp series network, capacitor C1r1 with capacitor C1r2 connection constitutes resonance capacitor, capacitor C1r1 connects the drain of MOS tube Q11, the drain of MOS tube Q13, battery V1 positive pole, capacitor C1r2 connects the source of MOS tube Q13, the drain of MOS tube Q14, inductance L1r connects the source of MOS tube Q11, the drain of MOS tube Q12, the source of MOS tube Q12 connects the source of MOS tube Q14, battery V1 negative pole. Compared with prior art, reduce energy loss, reduce circuit volume, improve energy transfer efficiency, enhance the anti-interference ability of circuit, strengthen multiplicity.

Description

Technical Field

[0001] This utility model relates to the field of battery balancing technology, specifically a battery balancing circuit and battery management system based on bidirectional full-bridge resonance. Background Technology

[0002] Currently, the main solutions to address the issue of inconsistent capacity in lithium battery cells leading to SOC imbalance are passive balancing and active balancing. Passive balancing primarily uses resistors to dissipate excess energy from high SOC cells; while active balancing transfers energy from high SOC cells to low SOC cells. The main research focus of active balancing is using DC-DC converters for battery charging balancing. However, this technology still suffers from drawbacks such as large circuit size, significant energy loss, and weak anti-interference capabilities. Utility Model Content

[0003] To address the problems mentioned in the background art, this utility model provides a battery equalization circuit based on bidirectional full-bridge resonance, including a transformer T. One end of the primary winding of the transformer T is connected to inductors L1r and L1p, and the other end is connected to capacitors C1p, C1r1, and C1r2. Inductor L1p and capacitor C1p are connected to form an Lp-Cp series network. Capacitors C1r1 and C1r2 are connected to form a resonant capacitor. Capacitor C1r1 is connected to the drain of MOSFET Q11, the drain of MOSFET Q13, and the positive terminal of battery cell V1. Capacitor C1r2 is connected to the source of MOSFET Q13 and the drain of MOSFET Q14. Inductor L1r is connected to the source of MOSFET Q11 and the drain of MOSFET Q12. The source of transistor 12 is connected to the source of MOSFET Q14 and the negative terminal of battery cell V1. One end of the secondary winding of transformer T is connected to inductors L2r and L2p, and the other end of the secondary winding of transformer T is connected to capacitors C2p, C2r1, and C2r2. Inductor L2p and capacitor C2p are connected to form an Lp-Cp series network. Capacitors C2r1 and C2r2 are connected to form a resonant capacitor. Capacitor C2r1 is connected to the drain of MOSFET Q21, the drain of MOSFET Q23, and the positive terminal of battery cell V2. Capacitor C2r2 is connected to the source of MOSFET Q23 and the drain of MOSFET Q24. Inductor L2r is connected to the source of MOSFET Q21 and the drain of MOSFET Q22. The source of MOSFET Q22 is connected to the source of MOSFET Q24 and the negative terminal of battery cell V2.

[0004] A battery management system includes the aforementioned battery balancing circuit, a battery pack, an AFE chip, an MCU chip, and a gate driving unit. The battery pack is connected to the AFE chip, the AFE chip is connected to the MCU chip, the MCU chip is connected to the gate driving unit, the gate driving unit is connected to the battery balancing circuit, and the battery balancing circuit is connected to the battery pack.

[0005] The AFE chip used is model ADBMS1818.

[0006] The MCU chip used is model GD32F307VET6.

[0007] The gate driving unit includes a chip U1. Chip U1 has enable pin A, enable pin B, output pin A, output pin B, input pin A, and input pin B. Enable pin A is connected to the drain of MOSFET Q2. The gate of MOSFET Q2 is connected to resistors R3 and R4. The other end of resistor R3 is connected to the source of MOSFET Q2 and grounded. Enable pin B is connected to the drain of MOSFET Q1. The gate of MOSFET Q1 is connected to resistors R1 and R2. Resistor R2 is connected to the source of MOSFET Q1 and grounded. Input pins A and B are connected to the output terminals of the MCU chip. The control signals from the U chip are transmitted to resistors R1 and R4 respectively. Output pin A is connected to transistors Q3 and Q4. One end of transistor Q3 is connected to the supply voltage, and one end of transistor Q4 is grounded. The other ends of transistors Q3 and Q4 are connected together to resistor R5. Resistor R5 is connected to capacitor C1. Capacitor C1 is connected to one end of the primary winding of transformer TA. The other end of the primary winding of transformer TA is grounded. One end of a secondary winding of transformer TA is connected to capacitor C2, and the other end is connected to diode D1, capacitor C3, resistor R6, and the source of MOSFET Q11. Diode D1, capacitor C3, and resistor R6 are connected together. 6. The gate of MOSFET Q11 is connected to capacitor C2. One end of the other secondary winding of transformer TA is connected to capacitor C4, and the other end is connected to diode D2, capacitor C5, resistor R7, and the source of MOSFET Q14. Diode D2, capacitor C5, resistor R7, and the gate of MOSFET Q14 are connected to capacitor C4. Output pin B is connected to transistors Q5 and Q6. One end of transistor Q5 is connected to the supply voltage, and one end of transistor Q6 is grounded. The other ends of transistors Q5 and Q6 are connected to resistor R8. Resistor R8 is connected to capacitor C6, and capacitor C6 is connected to the primary winding of transformer TB. One end of the primary winding of transformer TB is grounded. One end of one secondary winding of transformer TB is connected to capacitor C7, and the other end is connected to diode D3, capacitor C8, resistor R9, and the source of MOSFET Q12. Diode D3, capacitor C8, resistor R9, and the gate of MOSFET Q12 are connected together to capacitor C7. One end of the other secondary winding of transformer TB is connected to capacitor C9, and the other end is connected to diode D4, capacitor C10, resistor R10, and the source of MOSFET Q13. Diode D4, capacitor C10, resistor R10, and the gate of MOSFET Q13 are connected together to capacitor C9.

[0008] Compared with the prior art, this invention reduces energy loss, decreases circuit size, improves energy transfer efficiency, enhances circuit anti-interference ability, and strengthens reusability. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a battery balancing circuit.

[0010] Figure 2 This is a schematic diagram of a battery management system;

[0011] Figure 3 This is a schematic diagram of the gate driving unit;

[0012] Figure 4 A schematic diagram of the ideal waveform of the battery equalization circuit;

[0013] Figure 5 This is a schematic diagram of energy flow in mode 1 (t0~t1);

[0014] Figure 6 This is a schematic diagram of energy flow in mode 2 (t1~t2);

[0015] Figure 7 This is a schematic diagram of energy flow through mode 3 (t2~t3);

[0016] Figure 8 This is a schematic diagram of energy flow through mode 4 (t3~t4). Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings.

[0018] like Figure 1A battery equalization circuit based on bidirectional full-bridge resonance includes a transformer T. One end of the primary winding of transformer T is connected to inductors L1r and L1p. The other end of the primary winding of transformer T is connected to capacitors C1p, C1r1, and C1r2. Inductor L1p and capacitor C1p are connected to form an Lp-Cp series network. Capacitors C1r1 and C1r2 are connected to form a resonant capacitor. Capacitor C1r1 is connected to the drain of MOSFET Q11, the drain of MOSFET Q13, and the positive terminal of cell V1. Capacitor C1r2 is connected to the source of MOSFET Q13 and the drain of MOSFET Q14. Inductor L1r is connected to the source of MOSFET Q11 and the drain of MOSFET Q12. The source of MOSFET Q12 is connected to the drain of MOSFET Q14. The source of cell V1 is connected to the source of cell V1. One end of the secondary winding of transformer T is connected to inductors L2r and L2p. The other end of the secondary winding of transformer T is connected to capacitors C2p, C2r1, and C2r2. Inductor L2p and capacitor C2p are connected to form an Lp-Cp series network. Capacitors C2r1 and C2r2 are connected to form a resonant capacitor. Capacitor C2r1 is connected to the drain of MOSFET Q21, the drain of MOSFET Q23, and the positive terminal of cell V2. Capacitor C2r2 is connected to the source of MOSFET Q23 and the drain of MOSFET Q24. Inductor L2r is connected to the source of MOSFET Q21 and the drain of MOSFET Q22. The source of MOSFET Q22 is connected to the source of MOSFET Q24 and the negative terminal of cell V2. Based on the CLLLC topology, the resonant capacitor Cr is divided into two identical resonant capacitors. An Lp-Cp series network is used to replace the inherent magnetizing inductance Lm of the transformer. To reduce the circuit size, a nanocrystalline alloy core can be used, integrating all inductors in a single core. Replacing the magnetizing inductance Lm with an Lp-Cp series network allows for flexible impedance adjustment to suit the operating frequency. The equivalent magnetizing inductance Lmeq is expressed as:

[0019]

[0020]

[0021] The resonant capacitor Cr is divided into two identical capacitors, and their expression is:

[0022] .

[0023] like Figure 2A battery management system includes a battery balancing circuit, a battery pack, an AFE chip, an MCU chip, a gate drive unit, a fuse, a Hall sensor, a charging MOSFET, a discharging MOSFET, a drive processing unit, a communication unit, and an alarm unit. The battery pack is connected to the AFE chip, the AFE chip is connected to the MCU chip, the MCU chip is connected to the gate drive unit, the gate drive unit is connected to the battery balancing circuit, the battery balancing circuit is connected to the battery pack, the negative terminal of the battery pack is connected to the fuse, the fuse is connected to the Hall sensor, the Hall sensor is connected to the MCU chip and the charging MOSFET, the charging MOSFET is connected to the discharging MOSFET and the drive processing unit, the discharging MOSFET is connected to the drive processing unit, the MCU chip is connected to the drive processing unit and the communication unit, and the communication unit is connected to the alarm unit. The Hall sensor is used to detect the battery current and convert the current signal into a voltage signal for the MCU chip to monitor and control the current. The MCU, based on the battery status and control logic, controls the opening and closing of the charging and discharging MOSFETs through the drive control unit, thereby realizing the charging and discharging control of the battery. When an abnormal situation occurs in the battery system, the MCU triggers the alarm unit to issue an alarm signal.

[0024] The AFE chip used is model ADBMS1818.

[0025] The MCU chip used is model GD32F307VET6.

[0026] like Figure 3The gate drive unit includes chip U1. Chip U1 has enable pin A, enable pin B, output pin A, output pin B, input pin A, and input pin B. Enable pin A is connected to the drain of MOSFET Q2. The gate of MOSFET Q2 is connected to resistors R3 and R4. The other end of resistor R3 is connected to the source of MOSFET Q2 and grounded. Enable pin B is connected to the drain of MOSFET Q1. The gate of MOSFET Q1 is connected to resistors R1 and R2. The other end of resistor R2 is connected to the source of MOSFET Q1 and grounded. Input pins A and B are connected to the output terminals of the MCU chip. The control signals of the CU chip are transmitted to resistors R1 and R4 respectively. Output pin A is connected to transistors Q3 and Q4. One end of transistor Q3 is connected to the supply voltage, and one end of transistor Q4 is grounded. The other ends of transistors Q3 and Q4 are connected together to resistor R5. Resistor R5 is connected to capacitor C1. Capacitor C1 is connected to one end of the primary winding of transformer TA. The other end of the primary winding of transformer TA is grounded. One end of a secondary winding of transformer TA is connected to capacitor C2, and the other end is connected to diode D1, capacitor C3, resistor R6, and the source of MOSFET Q11. Diode D1, capacitor C3, and resistor R6... The gates of R6 and MOSFET Q11 are connected together to capacitor C2. One end of the other secondary winding of transformer TA is connected to capacitor C4, and the other end is connected to diode D2, capacitor C5, resistor R7, and the source of MOSFET Q14. The gates of diode D2, capacitor C5, resistor R7, and MOSFET Q14 are connected together to capacitor C4. Output pin B is connected to transistors Q5 and Q6. One end of transistor Q5 is connected to the supply voltage, and one end of transistor Q6 is grounded. The other ends of transistors Q5 and Q6 are connected together to resistor R8. Resistor R8 is connected to capacitor C6, and capacitor C6 is connected to the primary winding of transformer TB. One end of the primary winding of transformer TB is grounded. One end of one secondary winding of transformer TB is connected to capacitor C7, and the other end is connected to diode D3, capacitor C8, resistor R9, and the source of MOSFET Q12. Diode D3, capacitor C8, resistor R9, and the gate of MOSFET Q12 are connected together to capacitor C7. One end of the other secondary winding of transformer TB is connected to capacitor C9, and the other end is connected to diode D4, capacitor C10, resistor R10, and the source of MOSFET Q13. Diode D4, capacitor C10, resistor R10, and the gate of MOSFET Q13 are connected together to capacitor C9.

[0027] During battery charging, when the AFE chip detects that the voltage of a single cell has reached a set threshold, it triggers equalization. The analog front-end AFE chip sends information to the MCU chip, which then outputs control signals CON1 and CON2 to the gate drive unit. The gate drive unit outputs pulse signals VgA or VgB to the battery equalization circuit, which in turn turns on the MOSFET through a transformer. Control signals CON1 and CON2 control the output signals VgA and VgB. When control signals CON1 and CON2 are high, there is no output of pulse signals VgA and VgB; when control signals CON1 and CON2 are low, pulse signals VgA and VgB are output normally.

[0028] Within one switching cycle, the battery balancing circuit operates in four modes, from mode 1 to mode 4. Modes 1 and 2 correspond to the operating stages of one set of MOSFETs (Q11, Q14, Q21, Q24), while modes 3 and 4 correspond to the operating stages of another set of MOSFETs (Q12, Q13, Q22, Q23). Furthermore, modes 1 and 3 are dead-time stages, while modes 2 and 4 are resonance and energy transfer stages. A schematic diagram of the ideal waveform of the bidirectional full-bridge circuit is shown below. Figure 4 As shown.

[0029] like Figure 5 In mode 1, the dead zone occurs before MOSFETs Q11 and Q14 are turned on. During this dead zone, the gate drive unit has no output, all switches are not turned on, and the high-voltage side cell does not transfer energy to the low-voltage side cell. The only current on the high-voltage side is the reverse resonant current. This resonant current discharges the parallel capacitance of MOSFETs Q11 and Q14 and simultaneously charges the parallel capacitance of MOSFETs Q12 and Q13. When the resonant energy is large enough, it discharges the parallel capacitance of MOSFETs Q11 and Q14 until zero voltage. Then, the resonant current flows through the parallel body diode of MOSFETs Q11 and Q14, creating conditions for the subsequent ZVS of MOSFETs Q11 and Q14.

[0030] like Figure 6 In mode 2, the dead zone has ended, and the gate drive unit outputs VgA. MOSFETs Q11 and Q14 achieve ZVS conduction. Since the channel on-resistance of the MOSFET power device is less than the equivalent on-resistance of its parallel diode, the current flowing through the parallel diode is redirected to the channels of MOSFETs Q11 and Q14. The high-voltage side cell applies energy positively to the resonant network, causing the resonant current to rise linearly. The parallel diodes of low-voltage side MOSFETs Q21 and Q24 naturally conduct. Under synchronous rectification, energy is transferred to the low-voltage side cell through the transformer, achieving charging equalization between the cells.

[0031] like Figure 7 Mode 3 is the dead zone before MOSFETs Q12 and Q13 are turned on. Similar to Mode 1, the gate drive unit has no output. However, the charging and discharging of the parallel capacitor is reversed compared to Mode 1. At this time, the parallel capacitor of MOSFETs Q12 and Q13 is discharged, and the parallel capacitor of MOSFETs Q11 and Q14 is charged. Similarly, when the resonant energy is large enough, the parallel capacitor of MOSFETs Q12 and Q13 is discharged until the voltage is zero. Then the resonant current will flow through the parallel body diode of MOSFETs Q12 and Q13, creating conditions for the subsequent ZVS of MOSFETs Q12 and Q13.

[0032] like Figure 8 In Mode 4, the dead zone phase has ended, the gate drive unit outputs VgB, and MOSFETs Q12 and Q13 achieve ZVS conduction. Similarly, Mode 4 operates with the same characteristics as Mode 2, with the resonant current flowing into the channels of MOSFETs Q12 and Q13. The high-voltage side cell applies energy in reverse to the resonant network, causing the resonant current to rise linearly. The parallel diode of the low-voltage side MOSFETs Q22 and Q23 naturally conducts, and energy is transferred to the low-voltage side cell through the transformer, again achieving charging equalization between the cells.

[0033] Two resonant frequencies, fr and fr1, exist throughout the energy transfer process. When charging equalization is in modes 2 and 4, resonance occurs at the primary resonant frequency fr; when charging equalization is in modes 1 and 3, resonance occurs at the secondary resonant frequency fr1. The expressions for the two operating frequencies are as follows:

[0034]

[0035] ,

[0036] Lr is the resonant inductance value, Cr is the resonant capacitance value, and Lm is the magnetizing inductance value.

[0037] This circuit is based on a bidirectional DC-DC circuit, and by implementing ZVS of the MOSFET, the conduction loss and switching loss during the equalization process can be reduced. By changing the resonant capacitor, its current ripple and effective current value are reduced, while the voltage stress of the capacitor is reduced, thus improving the electromagnetic interference characteristics of the equalization circuit. By using an Lp-Cp series network to replace the inherent magnetizing inductance of the transformer, the circulating current loss of the resonant circuit can be effectively reduced. Furthermore, the energy transfer efficiency of this equalization circuit can reach up to 93%.

Claims

1. A battery equalization circuit based on bidirectional full-bridge resonance, comprising a transformer T, characterized in that: One end of the primary winding of the transformer T is connected to inductors L1r and L1p, and the other end is connected to capacitors C1p, C1r1, and C1r2. Inductor L1p and capacitor C1p are connected to form an Lp-Cp series network. Capacitors C1r1 and C1r2 are connected to form a resonant capacitor. Capacitor C1r1 is connected to the drain of MOSFET Q11, the drain of MOSFET Q13, and the positive terminal of battery V1. Capacitor C1r2 is connected to the source of MOSFET Q13 and the drain of MOSFET Q14. Inductor L1r is connected to the source of MOSFET Q11 and the drain of MOSFET Q12. The source of MOSFET Q12 is connected to the source of MOSFET Q14 and the negative terminal of battery V1. One end of the secondary winding of transformer T is connected to inductors L2r and L2p, and the other end of the secondary winding of transformer T is connected to capacitors C2p, C2r1, and C2r2. Inductor L2p and capacitor C2p are connected to form an Lp-Cp series network. Capacitors C2r1 and C2r2 are connected to form a resonant capacitor. Capacitor C2r1 is connected to the drain of MOSFET Q21, the drain of MOSFET Q23, and the positive terminal of cell V2. Capacitor C2r2 is connected to the source of MOSFET Q23 and the drain of MOSFET Q24. Inductor L2r is connected to the source of MOSFET Q21 and the drain of MOSFET Q22. The source of MOSFET Q22 is connected to the source of MOSFET Q24 and the negative terminal of cell V2.

2. A battery management system, comprising the battery balancing circuit, battery pack, AFE chip, MCU chip, and gate drive unit as described in claim 1, characterized in that: The battery pack is connected to an AFE chip, the AFE chip is connected to an MCU chip, the MCU chip is connected to a gate drive unit, the gate drive unit is connected to a battery balancing circuit, and the battery balancing circuit is connected to the battery pack.

3. A battery management system according to claim 2, characterized in that: The AFE chip used is model ADBMS1818.

4. A battery management system according to claim 2, characterized in that: The MCU chip used is model GD32F307VET6.

5. A battery management system according to claim 2, characterized in that: The gate driving unit includes a chip U1. Chip U1 has enable pin A, enable pin B, output pin A, output pin B, input pin A, and input pin B. Enable pin A is connected to the drain of MOSFET Q2. The gate of MOSFET Q2 is connected to resistors R3 and R4. The other end of resistor R3 is connected to the source of MOSFET Q2 and grounded. Enable pin B is connected to the drain of MOSFET Q1. The gate of MOSFET Q1 is connected to resistors R1 and R2. Resistor R2 is connected to the source of MOSFET Q1 and grounded. Input pins A and B are connected to the output terminals of the MCU chip. The control signals from the U chip are transmitted to resistors R1 and R4 respectively. Output pin A is connected to transistors Q3 and Q4. One end of transistor Q3 is connected to the supply voltage, and one end of transistor Q4 is grounded. The other ends of transistors Q3 and Q4 are connected together to resistor R5. Resistor R5 is connected to capacitor C1. Capacitor C1 is connected to one end of the primary winding of transformer TA. The other end of the primary winding of transformer TA is grounded. One end of a secondary winding of transformer TA is connected to capacitor C2, and the other end is connected to diode D1, capacitor C3, resistor R6, and the source of MOSFET Q11. Diode D1, capacitor C3, and resistor R6 are connected together.

6. The gate of MOSFET Q11 is connected to capacitor C2. One end of the other secondary winding of transformer TA is connected to capacitor C4, and the other end is connected to diode D2, capacitor C5, resistor R7, and the source of MOSFET Q14. Diode D2, capacitor C5, resistor R7, and the gate of MOSFET Q14 are connected to capacitor C4. Output pin B is connected to transistors Q5 and Q6. One end of transistor Q5 is connected to the supply voltage, and one end of transistor Q6 is grounded. The other ends of transistors Q5 and Q6 are connected to resistor R8. Resistor R8 is connected to capacitor C6, and capacitor C6 is connected to the primary winding of transformer TB. One end of the primary winding of transformer TB is grounded. One end of one secondary winding of transformer TB is connected to capacitor C7, and the other end is connected to diode D3, capacitor C8, resistor R9, and the source of MOSFET Q12. Diode D3, capacitor C8, resistor R9, and the gate of MOSFET Q12 are connected together to capacitor C7. One end of the other secondary winding of transformer TB is connected to capacitor C9, and the other end is connected to diode D4, capacitor C10, resistor R10, and the source of MOSFET Q13. Diode D4, capacitor C10, resistor R10, and the gate of MOSFET Q13 are connected together to capacitor C9.

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