Application circuit of a multimedia video splitter and multimedia server

Abstract

The utility model discloses a kind of application circuit and multimedia server of multimedia video segmenter, the application circuit of multimedia video segmenter includes: FPGA, the MCU connected with FPGA, GSV1016 LVDS input turns HDMI output conversion chip, GSV2011 LVDS input turns HDMI output conversion chip, GSV2011 HDMI2.0 input turns LVDS output and HDMI2.0 ring output conversion chip;MCU is also connected with computer mainboard USB communication, computer mainboard is also connected with GSV2011 HDMI2.0 input turns LVDS output and HDMI2.0 ring output conversion chip.The utility model solves the problem that current exhibition display solution cannot realize picture segmentation, EDID locking, non-standard resolution support, intelligent cluster control with the problem of high cost of scheme.

Description

Technical Field

[0001] This utility model relates to the field of multimedia server technology, and in particular to an application circuit for a multimedia video splitter and a multimedia server. Background Technology

[0002] Current multimedia servers generally only support video interfaces such as HDMI and DP integrated into the graphics card. Each interface outputs an independent video frame, without supporting screen splitting. Multimedia servers are primarily used in exhibition halls, where LED or LCD screens of varying sizes and resolutions are typically placed on different walls. Based on current applications, each screen displays both different themes and identical content. According to current solutions combining multimedia with LED video processors / LCD commercial display motherboards, each screen requires a separate multimedia server and LED video processor / LCD commercial display motherboard. Combining the content from several screens into a single image and controlling multiple screens in tandem is complex. Due to the large number of devices, desynchronization occurs at the start of the exhibition, resulting in a poor user experience. Furthermore, if the multimedia server uses integrated graphics, there is a resolution jump upon initial power-on, requiring manual adjustment of resolution and image order. It also does not support non-standard resolutions. Supporting EDID locking and non-standard resolutions requires a higher-end dedicated graphics card. Existing solutions do not support screen splitting, are costly, and have complex cluster control and operation, failing to achieve one-click synchronized display upon opening. Utility Model Content

[0003] The main purpose of this utility model is to propose an application circuit and a multimedia server for a multimedia video splitter, which aims to solve the problems of existing exhibition and display solutions being unable to achieve screen splitting, EDID locking, non-standard resolution support, and intelligent cluster control, as well as the high cost of the solutions.

[0004] To achieve the above objectives, this utility model provides an application circuit for a multimedia video splitter, comprising: an FPGA, an MCU, a GSV1016 LVDS input to HDMI output converter chip, a GSV2011 LVDS input to HDMI output converter chip, a GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip;

[0005] The GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, and the GSV2011 HDMI 2.0 input to LVDS output and HDMI 2.0 loop-out converter chip are connected to the FPGA via an I2S audio communication interface. The MCU is connected to the FPGA via an SPI communication interface or a UART communication interface. The MCU is also connected to the computer motherboard via USB communication. The computer motherboard is also connected to the GSV2011 HDMI 2.0 input to LVDS output and HDMI 2.0 loop-out converter chip.

[0006] A further technical solution of this utility model is that the FPGA is used to divide the 4K signal output from the GSV2011 HDMI 2.0 input to LVDS output and HDMI 2.0 loop-out conversion chip into 4 2K signals, which are then output to 3 GSV1016 parts and 1 GSV2011 part through LVDS, thereby realizing 3 2K and 1 4K output, or 4 2K output.

[0007] A further technical solution of this utility model is that the MCU communicates with the FPGA and the computer motherboard to control the registers of the GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, the GSV2011 HDMI2.0 input to LVDS output and HDMI 2.0 loop-out converter chip.

[0008] A further technical solution of this utility model is that the GSV1016 LVDS input to HDMI output converter chip is used to convert the LVDS image signal from the FPGA into HDMI 1.3 output.

[0009] A further technical solution of this utility model is that the GSV2011 LVDS input to HDMI output converter chip is used to convert the LVDS image signal from the FPGA into HDMI 2.0 or HDMI 1.3 output.

[0010] A further technical solution of this utility model is that the GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out conversion chip is used to convert the HDMI2.0 image signal from the computer motherboard into LVDS output and HDMI 2.0 loop-out.

[0011] A further technical solution of this utility model is that it also includes DDR3*2 storage connected to the FPGA.

[0012] A further technical solution of this utility model is that it also includes a GSV conversion chip control connected to the MCU.

[0013] A further technical solution of this utility model is that the FPGA adopts the PH1A90SBG464 programmable logic processing chip, and the MCU adopts the GD32F207VCT6 chip.

[0014] To achieve the above objectives, this utility model also proposes a multimedia server, which includes the application circuit of the multimedia video splitter as described above.

[0015] The beneficial effects of the application circuit of this utility model multimedia video splitter are:

[0016] This invention utilizes the protocol conversion function of GSV1016 and GSV2011 to convert LVDS image signals to HDMI / LVDS signals for output, along with the flexible image processing capabilities of FPGA and the central control function of a microcontroller. It not only supports screen splitting, EDID locking, non-standard resolution support, and intelligent cluster control, but also reduces the number of multimedia devices required for exhibition solutions. Only one multimedia server with screen splitting functionality is needed to support multiple LED screens / LCDs displaying arbitrary content, eliminating the need for multiple multimedia servers or high-end computer hosts. This improves the functionality and stability of the multimedia server and saves costs on exhibition solutions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the circuit structure of the multimedia video splitter of this utility model.

[0019] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Please refer to Figure 1 This utility model proposes an application circuit for a multimedia video splitter. A preferred embodiment of the application circuit for the multimedia video splitter of this utility model includes: FPGA, MCU, GSV1016 LVDS input to HDMI output converter chip, GSV2011 LVDS input to HDMI output converter chip, GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip.

[0022] The GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, and the GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip are connected to the FPGA via an I2S audio communication interface. The MCU is connected to the FPGA via an SPI communication interface or a UART communication interface. The MCU is also connected to the computer motherboard via USB communication. The computer motherboard is also connected to the GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip.

[0023] In this embodiment, the audio signals from the GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, the GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip are all transmitted to the FPGA via I2S, and the FPGA performs audio data packaging and distribution.

[0024] The GSV1016 and GSV2011 chips support both LVDS and TTL signals. This embodiment uses LVDS signals. Compared with the commonly used TTL signals, LVDS signals have stronger anti-interference capabilities, more efficient data transmission, and occupy less I / O. In the case of multi-conversion chip applications, using the LVDS interface can greatly save FPGA I / O resources.

[0025] In this embodiment, the FPGAPH1A90SBG464 programmable logic processing chip is used to split the 4K signal output from the GSV2011 HDMI2.0 input to LVDS output and the HDMI2.0 loop-out conversion chip into four 2K signals, which are then output to three GSV1016 sections and one GSV2011 section via LVDS, thereby achieving three 2K and one 4K output, or four 2K outputs.

[0026] The MCU uses a GD32F207VCT6 chip microcontroller, which is mainly responsible for control and communication with the FPGA and computer motherboard. It controls the registers of the GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, the GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip.

[0027] In this embodiment, the GSV1016 LVDS input to HDMI output converter chip is used to convert the LVDS image signal from the FPGA into HDMI 1.3 output.

[0028] The GSV2011 LVDS input to HDMI output converter chip is used to convert LVDS image signals from the FPGA into HDMI 2.0 or HDMI 1.3 output.

[0029] The GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip is used to convert HDMI2.0 image signals from the computer motherboard into LVDS output and HDMI2.0 loop-out.

[0030] The working principle of the application circuit of this multimedia video splitter is as follows:

[0031] The application circuit of this multimedia video splitter is mainly installed in a multimedia server and used in conjunction with a computer motherboard. It can also be used as a standalone video splitter box with an LED video processor / LCD smart commercial display motherboard. The HDMI 2.0 4K image signal output from the computer motherboard is converted to one LVDS output via GSV2011 and sent to the FPGA. Another HDMI 2.0 loop-out can be used to connect to a monitor as a human-computer interaction window. The FPGA processes the 4K image signal from the GSV2011 according to the user-set resolution and splitting settings, then splits it into different frames and distributes them to three GSV1016s. The GSV1016 converts the LVDS input image signal to an HDMI 1.3 output signal, which can be connected to the LED video processor or LCD smart commercial display motherboard as an image signal source. Simultaneously, it can also output an image signal via LVDS to another GSV2011. This GSV2011 can convert the 2K / 4K signal from the FPGA to an HDMI output. The 1.3 / HDMI 2.0 output can be used as an image signal source on LED video processors or LCD smart commercial display motherboards, or it can be directly connected to a monitor. The microcontroller (MCU) part mainly communicates with the FPGA and computer motherboard via serial port and USB respectively. Users can open image processing software on the computer system and send image parameters such as resolution and window information to the splitter motherboard to realize the screen splitting function. The microcontroller (MCU) also controls the GSV1016 and GSV2011 through I2C and GPIO, including register configuration and EDID information exchange, so that the parameters set by the user can be transmitted to the GSV1016 and GSV2011.

[0032] As one implementation scheme, in this embodiment, the application circuit of the multimedia video splitter further includes DDR3*2 storage connected to the FPGA and GSV conversion chip control connected to the MCU.

[0033] The beneficial effects of the application circuit of this utility model multimedia video splitter are:

[0034] This invention utilizes the protocol conversion function of GSV1016 and GSV2011 to convert LVDS image signals to HDMI / LVDS signals for output, along with the flexible image processing capabilities of FPGA and the central control function of a microcontroller. It not only supports screen splitting, EDID locking, non-standard resolution support, and intelligent cluster control, but also reduces the number of multimedia devices required for exhibition solutions. Only one multimedia server with screen splitting functionality is needed to support multiple LED screens / LCDs displaying arbitrary content, eliminating the need for multiple multimedia servers or high-end computer hosts. This improves the functionality and stability of the multimedia server and saves costs on exhibition solutions.

[0035] To achieve the above objectives, this utility model also proposes a multimedia server, which includes the application circuit of the multimedia video splitter as described in the above embodiment. The structure and working principle of the application circuit of the multimedia video splitter have been described in detail above and will not be repeated here.

[0036] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the concept of the present utility model and using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present utility model.

Claims

1. An application circuit for a multimedia video splitter, characterized in that, include: FPGA, MCU, GSV1016 LVDS input to HDMI output converter chip, GSV2011 LVDS input to HDMI output converter chip, GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip; The GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, and the GSV2011 HDMI 2.0 input to LVDS output and HDMI 2.0 loop-out converter chip are connected to the FPGA via an I2S audio communication interface. The MCU is connected to the FPGA via an SPI communication interface or a UART communication interface. The MCU is also connected to the computer motherboard via USB communication. The computer motherboard is also connected to the GSV2011 HDMI 2.0 input to LVDS output and HDMI 2.0 loop-out converter chip.

2. The application circuit of the multimedia video splitter according to claim 1, characterized in that, The FPGA is used to split the 4K signal from the GSV2011 HDMI2.0 input to LVDS output and the HDMI 2.0 loop-out conversion chip into four 2K signals, which are then output to three GSV1016 sections and one GSV2011 section via LVDS, thereby achieving three 2K and one 4K output, or four 2K outputs.

3. The application circuit of the multimedia video splitter according to claim 2, characterized in that, The MCU communicates with the FPGA and the computer motherboard to control the registers of the GSV1016 LVDS input to HDMI output converter chip, the GSV2011 LVDS input to HDMI output converter chip, the GSV2011 HDMI2.0 input to LVDS output and HDMI2.0 loop-out converter chip.

4. The application circuit of the multimedia video splitter according to claim 3, characterized in that, The GSV1016LVDS input to HDMI output converter chip is used to convert the LVDS image signal from the FPGA into HDMI 1.3 output.

5. The application circuit of the multimedia video splitter according to claim 4, characterized in that, The GSV2011LVDS input to HDMI output converter chip is used to convert LVDS image signals from the FPGA into HDMI 2.0 or HDMI 1.3 output.

6. The application circuit of the multimedia video splitter according to claim 5, characterized in that, The GSV2011 HDMI 2.0 input to LVDS output and HDMI 2.0 loop-out conversion chip is used to convert HDMI 2.0 image signals from the computer motherboard into LVDS output and HDMI 2.0 loop-out.

7. The application circuit of the multimedia video splitter according to any one of claims 1 to 6, characterized in that, It also includes DDR3*2 memory connected to the FPGA.

8. The application circuit of the multimedia video splitter according to any one of claims 1 to 6, characterized in that, It also includes GSV conversion chip control connected to the MCU.

9. The application circuit of the multimedia video splitter according to claim 1, characterized in that, The FPGA uses the PH1A90SBG464 programmable logic processing chip, and the MCU uses the GD32F207VCT6 chip.

10. A multimedia server, characterized in that, The multimedia server includes the application circuitry of the multimedia video splitter as described in any one of claims 1 to 9.

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