A packaging structure for improving system packaging reliability

Abstract

The application relates to the technical field of semiconductor packaging, and relates to a packaging structure for improving the reliability of system packaging, which comprises a PCB and packaging bodies on the PCB. Interlaced cutting channels are arranged between the packaging bodies, the cutting channels divide the PCB into a plurality of packaging bodies with uniform sizes, and soldering pad pins are arranged around the packaging bodies. The soldering pad pins are covered on the top surface, the bottom surface and the side surface of the edges of the packaging bodies. The application improves product stability, simplifies the layout of the PCB, can quickly separate digital signals from simulation signals, and reduces the production difficulty in subsequent processes.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging structure that improves the reliability of system packaging. Background Technology

[0002] System-in-a-Package (SIP) is the best solution for integrating electronic circuits into a single package. All integrated circuits contain power simulation circuits and digital processing circuits. The power simulation circuits require large pads to provide sufficient current. In order to increase the pads and reduce the risk of poor contact, more power supply pads can be added, resulting in more pins and difficulties in subsequent surface mount assembly.

[0003] Existing SIP packaging technologies, including BGA and LGA packages, all have their pads located at the bottom, regardless of whether they are square, round, single-path, or array-based. However, when some pins require higher current or larger heat dissipation areas, two or more pads are needed, leading to the following problems:

[0004] 1. The simulation signal and digital signal have significant interference, requiring additional shielding pins;

[0005] 2. The increase in solder pads leads to a reduction in the spacing between solder pads, which increases the risk of soldering failure.

[0006] 3. The increased number of solder pads leads to increased solder consumption and higher costs. Utility Model Content

[0007] In order to overcome the problems existing in the prior art, this application provides a packaging structure that improves the reliability of system packaging.

[0008] The packaging structure provided in this application to improve the reliability of system packaging adopts the following technical solution:

[0009] A packaging structure for improving system packaging reliability includes a PCB board and packages on the PCB board. The packages are provided with staggered cutting channels that divide the PCB board into several packages of uniform size. The packages are provided with pads and pins around their perimeter, and the pads and pins cover the top, bottom and side surfaces of the package edges.

[0010] By adopting the above technical solution, the PCB board is divided into uniformly sized packages by setting staggered cutting channels, making each package independent and facilitating package cutting and assembly. Simultaneously, the pads and leads are covered on the top, bottom, and sides of the package edge, changing the traditional layout where pads are only at the bottom. When some pins require larger current or a larger heat dissipation area, multiple pads in different locations can be used for transmission and heat dissipation, eliminating the need to simply increase the number of pads at the bottom. This satisfies the power simulation circuit's requirements for large pads and sufficient current, while avoiding problems such as increased pin count and placement difficulties caused by excessive pads at the bottom. It also reduces interference between simulation and digital signals, increases pad spacing, reduces the risk of soldering failure, reduces solder usage and cost, thereby improving the reliability of the system package.

[0011] Preferably, the pad pins include top layer lines and bottom layer lines located on the upper and lower surfaces of the package, wherein the outer side of the pad pins is flush with the edge of the cut track.

[0012] Preferably, a through hole is provided on the side of the PCB board near the pad pin of the cut track, and the inner wall of the through hole is filled with a conductive layer, and the conductive layer connects the top layer circuit and the bottom layer circuit.

[0013] Preferably, the through hole is an elongated hole, and the internal length of the elongated hole is equal to the edge length of the pad pin.

[0014] Preferably, the pad pins are square or rectangular, and the widths of the top layer, bottom layer, and side conductive layer are the same.

[0015] By adopting the above technical solution, the pad pins include the top and bottom layer circuits on both sides of the package, and the outer side is flush with the edge of the cut track. This layout makes the pad pin distribution more regular, which facilitates soldering operations and circuit connection. In the PCB board, a through hole is opened on the side of the cut track near the pad pin, and a conductive layer is filled on its inner wall. The conductive layer connects the top and bottom layer circuits, so that the current can be transmitted efficiently between the circuits on different layers, which enhances the stability of the circuit connection. The through hole is designed as a long hole, which is convenient to be cut through the PCB board through-hole process. The pad pins adopt square or rectangular feet, while ensuring that the width of the top layer circuit, the bottom layer circuit and the side conductive layer are the same. This unified and standardized design not only optimizes the current distribution, but also reduces signal transmission loss and improves electrical performance. The combined effect of multiple designs effectively improves the reliability and stability of the system package.

[0016] Preferably, the PCB board thickness is 0.1-0.3mm.

[0017] In summary, this application includes at least one of the following beneficial technical effects:

[0018] 1. This application adds pads of the same thickness as the PCB side, and uses PCB stamp hole technology and semiconductor packaging cutting technology in combination to increase the size of the pads, ensuring more reliable placement of components in subsequent processes.

[0019] 2. In this application, auxiliary pads are added to the four sides of the BGA or LGA package of semiconductor SIP packaging technology, so that it has the same side pins as DFN or QFN package, thereby improving product reliability.

[0020] 3. The package in this application has pads and pins on all four sides, which improves product stability, simplifies PCB design layout, and can quickly separate digital and simulation signals, reducing the difficulty of subsequent production processes. Attached Figure Description

[0021] Figure 1 This is a magnified view of the bottom of a packaging structure that improves the reliability of system packaging.

[0022] Figure 2 This is a bottom view of the via after processing at the junction of the pad pin and the cut track;

[0023] Figure 3 This is a side view of the through hole at the junction of the pad pin and the cut track;

[0024] Figure 4 This is a schematic diagram of the bottom of the cut surface at the junction of the pad pin and the cut surface;

[0025] Figure 5 This is a side view of the area where the pad pins meet the cut surface after cutting.

[0026] Explanation of reference numerals in the attached diagram: 1. PCB board; 2. Package; 3. Cutout; 4. Pad pin; 41. Top layer circuit; 42. Bottom layer circuit; 5. Through hole; 51. Conductive layer. Detailed Implementation

[0027] The following is in conjunction with the appendix Figure 1-5 This application will be described in further detail.

[0028] This application discloses a packaging structure that improves the reliability of system packaging.

[0029] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5A packaging structure for improving system packaging reliability includes a 0.2mm thick PCB board 1 and packages 2 on the PCB board 1. The packages 2 have staggered cutting channels 3 that divide the PCB board 1 into several uniformly sized packages 2. Each package 2 has pads and pins 4 around its perimeter, covering the top, bottom, and side surfaces of the package 2's edges. By providing staggered cutting channels 3 on the PCB board 1, the PCB board 1 is divided into uniformly sized packages 2, making each package 2 independent and facilitating the cutting and assembly of the packages 2. Meanwhile, the pad pins 4 are covered on the top, bottom and side surfaces of the package body 2, changing the traditional layout where the pads are only on the bottom. When some pins require a large current or a large heat dissipation area, multiple pads in different positions can be used for transmission and heat dissipation, without simply increasing the number of pads at the bottom. This satisfies the power simulation circuit's requirements for large pads and sufficient current, while avoiding problems such as increased pin count and difficulty in surface mount due to excessive pads at the bottom. It also reduces interference between simulation signals and digital signals, increases pad gaps, reduces the risk of soldering failure, reduces solder usage and cost, thereby improving the reliability of the system package.

[0030] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The pad pins 4 include top layer traces 41 and bottom layer traces 42 located on the upper and lower surfaces of the package 2, with the outer side of the pad pins 4 flush with the edge of the cut track 3. A through-hole 5 is formed on the side of the cut track 3 near the pad pins 4 in the PCB board 1. The inner wall of the through-hole 5 is filled with a conductive layer 51, which connects the top layer traces 41 and the bottom layer traces 42. The through-hole 5 is an elongated hole, and its internal length is equal to the edge length of the pad pins 4. The pad pins 4 are square or rectangular, and the widths of the top layer traces 41, the bottom layer traces 42, and the side conductive layer 51 are the same. The pad pins 4 include the top layer lines 41 and bottom layer lines 42 on the upper and lower sides of the package 2, and their outer sides are flush with the edge of the cut channel 3. This layout makes the pad pins 4 more regularly distributed, which is convenient for soldering operations and circuit connection. In the PCB board 1, a through hole 5 is opened on the side of the cut channel 3 near the pad pins 4, and a conductive layer 51 is filled on its inner wall. The conductive layer 51 connects the top layer lines 41 and the bottom layer lines 42, so that the current can be efficiently transmitted between lines on different layers, which enhances the stability of the circuit connection. The through hole 5 is designed as a long hole, which is convenient to be cut through the ink ticket hole process of the PCB board 1. The pad pins 4 adopt square or rectangular feet, while ensuring that the width of the top layer lines 41, the bottom layer lines 42 and the side conductive layer 51 are the same. This unified and standardized design not only optimizes the current distribution, but also reduces signal transmission loss and improves electrical performance. The combined effect of multiple designs effectively improves the reliability and stability of the system package.

[0031] Working Process: First, using a 0.2mm thick PCB board 1 as a base, a package 2 is formed on the PCB board 1. Interleaved cuts 3 are arranged between the packages 2, dividing the PCB board 1 into several uniformly sized packages 2. Each package 2 has pads 4 arranged around its perimeter. These pads 4 cover the top, bottom, and side surfaces of the package 2's edge. The top layer circuitry 41 and bottom layer circuitry 42 located on the top and bottom surfaces of the package 2 constitute the main part of the pads 4, and the outer edges of the pads 4 are flush with the edges of the cuts 3. In the PCB board 1, a through-hole 5 is formed on the side of the cuts 3 near the pads 4. The inner wall of the through-hole 5 is filled with a conductive layer 51, which connects the top layer circuitry 41 and the bottom layer circuitry 42. To ensure conductivity, the through-hole 5 is an elongated hole, with its internal length equal to the edge length of the pads 4. The pads 4 are square-shaped, and the widths of the top layer circuitry 41, the bottom layer circuitry 42, and the side conductive layer 51 are the same, thus forming a complete conductive path. This structure increases the pad placement space and reduces the density of bottom pads by distributing the pad pins 4 on the top, bottom, and side surfaces of the package 2. At the same time, it utilizes the conductive layer 51 of the through-hole 5 to achieve multi-layer circuit connectivity, which not only meets the requirements of high current and heat dissipation, but also reduces the interference between simulation signals and digital signals through the separation of the cut-out track 3 and the optimization of the pad distribution, reduces the risk of soldering failure caused by excessively narrow pad gaps, reduces solder usage, and improves package reliability.

[0032] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A packaging structure for improving system packaging reliability, characterized in that: The package includes a PCB board (1) and a package (2) on the PCB board (1). The package (2) is provided with staggered cutting channels (3). The cutting channels (3) divide the PCB board (1) into several packages (2) of uniform size. The package (2) is provided with pad pins (4) around its perimeter. The pad pins (4) cover the top, bottom and side surfaces of the edge of the package (2).

2. The packaging structure for improving system packaging reliability according to claim 1, characterized in that: The pad pins (4) include top layer lines (41) and bottom layer lines (42) located on the upper and lower sides of the package (2), wherein the outer side of the pad pins (4) is flush with the edge of the cut channel (3).

3. The packaging structure for improving system packaging reliability according to claim 2, characterized in that: A through hole (5) is provided on the side of the cut channel (3) near the pad pin (4) in the PCB board (1). The inner wall of the through hole (5) is filled with a conductive layer (51), and the conductive layer (51) connects the top layer circuit (41) and the bottom layer circuit (42).

4. The packaging structure for improving system packaging reliability according to claim 3, characterized in that: The through hole (5) is an elongated hole, and the internal length of the elongated hole is equal to the edge length of the pad pin (4).

5. The packaging structure for improving system packaging reliability according to claim 4, characterized in that: The pad pins (4) are square or rectangular, and the widths of the top layer line (41), bottom layer line (42) and side conductive layer (51) are the same.

6. The packaging structure for improving system packaging reliability according to claim 1, characterized in that: The thickness of the PCB board (1) is 0.1-0.3mm.

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