Transient voltage suppression diode assembly

Abstract

The utility model transient voltage suppression diode assembly, including lower cushion, a plurality of surfaces of lower cushion are provided with conductive surface layer A, the conductive surface layer A of corresponding one is provided with transient voltage suppression diode chip, transient voltage suppression diode chip is provided with upper cushion, a plurality of surfaces of upper cushion are provided with conductive surface layer B, form transient voltage suppression diode chip upper and lower conduction structure.

Description

Technical Field

[0001] This invention relates to a technology for fabricating optical devices and the equipment for using them, specifically a transient voltage suppression diode assembly. Background Technology

[0002] Transient voltage suppressor diodes are components that protect circuits from voltage surges and transient overvoltages. They are mainly used to protect electronic circuits from damage caused by transient voltage spikes, such as lightning strikes, electrical noise, and electromagnetic interference.

[0003] Transient voltage suppressor diodes are based on their "transient response" characteristic, which means that they can quickly react to transient overvoltages in a circuit and absorb or guide the overvoltage to ground through their own conductivity within a short time, thereby protecting other electronic components.

[0004] Under normal operating conditions, a transient voltage suppressor diode (TVS) is almost non-conductive. It is reverse-biased, with a voltage below its breakdown voltage, also known as the peak reverse working voltage, typically ranging from a few volts to tens of volts. In this state, the TVS diode has virtually no impact on circuit operation.

[0005] When a transient voltage surge or spike occurs in a circuit, the reverse voltage of the transient voltage suppressor diode exceeds its breakdown voltage (i.e., reverse breakdown voltage). At this point, the transient voltage suppressor diode quickly enters the conducting state and begins to conduct electricity through itself. The conductivity of the transient voltage suppressor diode is greatly enhanced at this time, and current flows through it, thus guiding the overvoltage to ground or the power supply, thereby protecting sensitive components in subsequent circuits from overvoltage damage.

[0006] Transient voltage suppressor diodes (VTRS) can absorb large amounts of transient energy in a short time and release it as heat. Their main characteristics are rapid response and high energy absorption capacity. Depending on the specifications, a VTRS diode can absorb hundreds to thousands of kilowatts of transient power, and this process typically takes only a few nanoseconds to a few microseconds.

[0007] Once the transient voltage disappears, the transient voltage suppressor diode quickly returns to a non-conductive state, continuing to protect the circuit. This gives the transient voltage suppressor diode a self-recovery function, effectively protecting the circuit for a short time without requiring replacement.

[0008] In high-reliability applications such as aerospace and military electronics, TVS diodes must meet the hermetically sealed requirements specified in the MIL-STD-883 standard. While traditional metal-cased packages can achieve 1×10⁻⁶... -8 Pa·m 3 It achieves a helium leakage rate of / s, but faces the following systemic technical contradictions when compatible with surface mount technology.

[0009] 1. Thermal compatibility challenges: Traditional airtight tube shells mostly use low-temperature brazing processes (<200℃), which has a significant thermal mismatch with the peak temperature of SMT reflow soldering (240-260℃), leading to tube seal failure and interface thermal stress problems.

[0010] 2. Insufficient compatibility of gold-tin interconnect process: The thickness of the surface metallization layer of the current TVS chip is usually <0.5μm, which is difficult to meet the requirements of gold wire bonding process. In addition, improper control of the Au / Sn intermetallic compound ratio can easily lead to increased brittleness of the bonding interface, affecting long-term reliability.

[0011] Therefore, it is necessary to provide a transient voltage suppression diode assembly to solve the above problems. Utility Model Content

[0012] The purpose of this invention is to provide a transient voltage suppression diode assembly.

[0013] The technical solution is as follows:

[0014] A transient voltage suppression diode assembly includes a lower pad, on which conductive surface layers A are disposed on multiple surfaces. A transient voltage suppression diode chip is disposed on one of the conductive surface layers A. An upper pad is disposed on the transient voltage suppression diode chip, on which conductive surface layers B are disposed on multiple surfaces, forming an upper and lower conductive structure of the transient voltage suppression diode chip.

[0015] Furthermore, the lower pad includes at least four surfaces with conductive surface layers A, and the four conductive surface layers A are interconnected.

[0016] Furthermore, the upper pad includes at least four surfaces with conductive surface layers B, and the four conductive surface layers B are interconnected.

[0017] Furthermore, both conductive surface layer A and conductive surface layer B are gold-plated.

[0018] Furthermore, connecting reinforcement sheets are provided between the lower pad and the transient voltage suppression diode chip, and between the transient voltage suppression diode chip and the upper pad.

[0019] Furthermore, the connecting reinforcement sheet is a gold-tin solder sheet.

[0020] Furthermore, a gold-tin eutectic bonding method is used to weld the lower pad, transient voltage suppressor diode chip, and upper pad to form a rapid fabrication structure for the transient voltage suppressor diode assembly.

[0021] Furthermore, both the lower and upper pads are ceramic substrates.

[0022] Compared with the prior art, this utility model uses a three-dimensional interconnect structure of TVS devices with gold-tin eutectic bonding and a gradient gold-tin composite solder system to achieve the upper and lower circuit leads of the transient voltage suppression diode chip. This allows the gold layer thickness on the surface of the transient voltage suppression diode chip, which is originally incompatible with gold wire bonding, to form a reliable metallurgical bond with the gold plating layer thickness of the ceramic substrate, which is ≥1μm. The welding void rate is <5%, and the shear strength is ≥25MPa, meeting the hermetically sealed packaging requirements of microelectronic devices in GJB548B-2005. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of this utility model;

[0024] Figure 2 This is an exploded view of this utility model. Detailed Implementation

[0025] Example:

[0026] Please see Figure 1-2 This embodiment illustrates a transient voltage suppression diode assembly, including a lower pad 1. A conductive surface layer A11 is disposed on multiple surfaces of the lower pad 1. A transient voltage suppression diode chip 2 is disposed on one of the conductive surface layers A11. An upper pad 3 is disposed on the transient voltage suppression diode chip 2. A conductive surface layer B31 is disposed on multiple surfaces of the upper pad 3, forming an upper and lower conductive structure of the transient voltage suppression diode chip.

[0027] Transient voltage suppression diode chip 2 has a chip conductive layer on the conductive surface layer A11 and conductive surface layer B31, and the chip conductive layer is a gold-plated layer.

[0028] The lower pad 1 includes at least four surfaces with conductive surface layers A11, and the four conductive surface layers A11 are interconnected.

[0029] The upper pad 3 includes at least four surfaces with conductive surface layers B31, and the four conductive surface layers B31 are interconnected.

[0030] Both conductive surface layer A11 and conductive surface layer B31 are gold-plated.

[0031] Connecting reinforcement sheets 4 are provided between the lower pad 1 and the transient voltage suppression diode chip 2, and between the transient voltage suppression diode chip 2 and the upper pad 3.

[0032] The connecting reinforcement sheet 4 is a gold-tin solder sheet.

[0033] The lower pad 1, transient voltage suppressor diode chip 2, and upper pad 3 are welded using a gold-tin eutectic bonding method to form a rapid fabrication structure for the transient voltage suppressor diode assembly.

[0034] Both the lower pad 1 and the upper pad 3 are ceramic substrates.

[0035] Compared with the prior art, this utility model uses a three-dimensional interconnect structure of TVS devices with gold-tin eutectic bonding and a gradient gold-tin composite solder system to achieve the upper and lower circuit leads of the transient voltage suppression diode chip. This allows the gold layer thickness on the surface of the transient voltage suppression diode chip, which is originally incompatible with gold wire bonding, to form a reliable metallurgical bond with the gold plating layer thickness of the ceramic substrate, which is ≥1μm. The welding void rate is <5%, and the shear strength is ≥25MPa, meeting the hermetically sealed packaging requirements of microelectronic devices in GJB548B-2005.

[0036] For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of this utility model, and these all fall within the protection scope of this utility model.

Claims

1. A transient voltage suppression diode assembly, characterized in that: The device includes a lower pad, on which conductive surface layers A are disposed on multiple surfaces. A transient voltage suppression diode chip is disposed on one of the conductive surface layers A. An upper pad is disposed on the transient voltage suppression diode chip, on which conductive surface layers B are disposed on multiple surfaces, forming an upper and lower conductive structure for the transient voltage suppression diode chip.

2. The transient voltage suppression diode assembly according to claim 1, characterized in that: The lower pad includes at least four surfaces with conductive surface layers A, and the four conductive surface layers A are interconnected.

3. A transient voltage suppression diode assembly according to claim 2, characterized in that: The pad includes at least four surfaces with conductive surface layers B, and the four conductive surface layers B are interconnected.

4. A transient voltage suppression diode assembly according to claim 3, characterized in that: Both conductive surface layer A and conductive surface layer B are gold-plated.

5. A transient voltage suppression diode assembly according to claim 1, characterized in that: Connecting reinforcement sheets are provided between the lower pad and the transient voltage suppression diode chip, and between the transient voltage suppression diode chip and the upper pad.

6. A transient voltage suppression diode assembly according to claim 5, characterized in that: The connecting reinforcement sheet is a gold-tin solder sheet.

7. A transient voltage suppression diode assembly according to claim 6, characterized in that: The lower pad, transient voltage suppressor diode chip, and upper pad are soldered using a gold-tin eutectic bonding method to form a rapid fabrication structure for the transient voltage suppressor diode assembly.

8. A transient voltage suppression diode assembly according to any one of claims 1-7, characterized in that: Both the lower and upper pads are ceramic substrates.

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