Co-packaged optical engine and networking
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG EAGLE SEMICON TECH CO LTD
- Filing Date
- 2025-06-10
- Publication Date
- 2026-06-26
Smart Images
Figure CN224417074U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of optical module technology, and in particular to a co-packaged optical engine and networking. Background Technology
[0002] Optical communication is a communication method that uses light waves as carriers and optical fibers or the atmosphere as transmission media to transmit information. The basic principle of optical communication is to convert electrical signals into optical signals, transmit them through the transmission medium, and then convert the optical signals back into electrical signals at the receiving end. Therefore, optical communication has extremely high transmission bandwidth, which can meet the needs of transmitting large amounts of data. However, there is still considerable room for improvement in the size and transmission rate of existing optical modules used to support optical communication. Utility Model Content
[0003] The main objective of this invention is to provide a co-packaged optical engine, comprising a data processing die and an optical chip stacked on top of the data processing die.
[0004] The optical chip is configured to transmit and receive data in the form of optical signals;
[0005] The data processing bare chip is configured to process the data.
[0006] In one embodiment, the optical chip includes an optical receiver array, an optical transmitter array, a first coupling fiber array, and a second coupling fiber array; the first coupling fiber array is coupled to the optical receiver end of the optical receiver array, and the second coupling fiber array is coupled to the optical transmitter end of the optical transmitter array; and / or
[0007] The coupled fiber array is a multi-core fiber array.
[0008] In one embodiment, the optical receiving array further includes a first metal bonding end disposed opposite to the optical receiving end, and the optical emitting array further includes a second metal bonding end disposed opposite to the optical emitting end. The first metal bonding end and the second metal bonding end are respectively bonded to the data processing bare chip through a ball array.
[0009] In one embodiment, the optical receiving array and the optical transmitting array are flip-chip structures.
[0010] In one embodiment, the co-packaged optical engine further includes:
[0011] Electrically processed bare core, including a first electrically processed bare core and a second electrically processed bare core;
[0012] The first electrical processing bare core is disposed between the optical receiving array and the data processing bare core; the second electrical processing bare core is disposed between the optical transmitting array and the data processing bare core.
[0013] In one embodiment, the electrical processing bare die is selected from at least one of transimpedance amplifier, clock restorer, high-speed memory, electrical drive chip, modulator drive chip, and digital signal processing chip.
[0014] In one embodiment, the optical emitting array includes a plurality of VCSEL units arranged in an array, and the optical receiving array includes a plurality of photodetector units arranged in an array.
[0015] In one embodiment, the co-packaged optical engine further includes:
[0016] A coupled fiber optic array, comprising a first coupled fiber optic array and a second coupled fiber optic array, wherein the first coupled fiber optic array is coupled to the optical receiving end of the optical receiving array, and the second coupled fiber optic array is coupled to the optical transmitting end of the optical transmitting array; and / or
[0017] The coupled fiber array is a multi-core fiber array.
[0018] In one embodiment, the data processing bare chip integrates at least one of an electric drive unit, an optical drive unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit; and / or
[0019] The optical chip integrates at least one of the following: an electric drive unit, an optical drive unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit.
[0020] The devices integrated in the data processing bare chip are different from or complementary to the devices integrated in the optical chip.
[0021] In one embodiment, the data processing bare die is selected from any one of a graphics processing unit (GPU), a custom AI accelerator (XPU), or an application-specific integrated circuit (ASIC) chip.
[0022] In one embodiment, when the data processing bare die is an application-specific integrated circuit (ASIC) chip, the ASIC chip includes an integrated modulation driver and a microcontroller, and the integrated modulation driver is configured to drive optical signal modulation using pulse amplitude modulation (PAM-4), pulse amplitude modulation (PAM-6), or pulse amplitude modulation (PAM-8) formats.
[0023] Secondly, this application also provides a co-packaged optical engine network, including a plurality of co-packaged optical engines as described above, wherein each co-packaged optical engine is optically coupled to the others.
[0024] In one embodiment, the co-packaged optical engines are optically coupled to their respective optical chips using an optical fiber array.
[0025] In one embodiment, the co-packaged optical engine network further includes several switching chips, one of which is optically coupled between any two co-packaged optical engines.
[0026] This utility model has at least the following beneficial effects:
[0027] The co-packaged optical engine and network provided by this utility model directly encapsulates the optical chip on top of the data processing bare chip. The optical signal transceiver end of the optical chip is perpendicular to the upper surface of the data processing bare chip, and is used to transmit and receive high-speed communication data via optical signals. The data processing bare chip is responsible for processing the high-speed communication data transmitted and received by the optical chip. Since the intermediate substrate between the traditional data processing bare chip and the optical chip is eliminated, the transmission path between data processing and data transmission and reception is further shortened, and the data transmission efficiency is further improved. In addition, this tight coupling can also significantly reduce signal loss and improve the integrity of high-speed signals. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the structure of a co-packaged optical engine in one embodiment of this application;
[0029] Figure 2 A schematic diagram of the structure of a co-packaged optical engine according to another embodiment of this application;
[0030] Figure 3 A schematic diagram of the structure of a co-packaged optical engine according to another embodiment of the present invention;
[0031] Figure 4 A schematic diagram of the co-packaged optical engine network structure in one embodiment of this utility model;
[0032] Figure 5 A schematic diagram of the co-packaged optical engine network structure in another embodiment of this utility model.
[0033] The purpose, features, and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0035] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first client may be referred to as a second client, and similarly, a second client may be referred to as a first client.
[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "Multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Several" means at least one, such as one, two, etc., unless otherwise explicitly specified.
[0037] With the development of the AI industry, cloud data companies, represented by supercomputing companies and data centers, are placing higher bandwidth and speed requirements, as well as lower energy efficiency requirements on optical transmission relay modules. Traditional pluggable optical modules used in data centers are gradually evolving towards higher modulation rate optical transmitters and advanced process modulation chips. For short-distance transmission scenarios, LPO (Linear-drive Pluggable Optics) and CPO (Co-Packaged Optics) optical engine architectures have been introduced. These architectures eliminate the need for traditional DSP or CDR devices used for long-distance signal recovery, saving approximately 50% of module power consumption. The CPO co-packaged solution eliminates the pluggable connection between the PCB gold fingers and the switch side, encapsulating the optical engine and ASIC chip on the same substrate, thereby achieving increased bandwidth and reduced losses on both electrical and optical I / O sides.
[0038] However, taking the more mainstream CPO packaging as an example, its main packaging method requires multiple dielectric substrates to transfer data signals between the electro-optical chip EIC, PIC and GPU (such as organic package, TSMC interposer, PCB). Although this has greatly reduced signal transmission loss compared to traditional solutions, the presence of multiple dielectric substrates still increases the signal transmission path, resulting in a certain amount of signal transmission loss.
[0039] Based on this, such as Figures 1-5 As shown, this application provides a co-packaged optical engine designed to solve the aforementioned technical problems, aiming to further reduce signal transmission loss and improve data transmission efficiency. Figure 1 As shown, a co-packaged optical engine may include an optical chip 10 and a data processing bare die 20. The optical chip 10 is stacked on top of the data processing bare die 20 and electrically connected to it. The optical chip 10 is configured to transmit and receive data in the form of optical signals, and the optical signal transceiver of the optical chip 10 is located on the side away from the data processing bare die 20. The data processing bare die 20 is configured to process the data. Specifically, the data transmitted and received by the optical chip 10 is high-speed communication data, which is modulated into optical signals for transmission. Compared with traditional copper wire transmission, optical signals have a larger transmission bandwidth and transmission speed, and are gradually becoming the mainstream communication method in the future. Optical communication is a technology in which light waves are used as signal carriers and transmitted between two nodes via optical fibers. An optical communication system mainly includes an optical transmitter and an optical receiver. Through an optical transceiver, the received optical signal can be converted into an electrical signal that can be processed by an integrated circuit (IC), or the processed electrical signal can be converted into an optical signal to be transmitted via optical fiber. Therefore, the purpose of communication can be achieved.
[0040] In one example, the optical chip 10 of this application can be stacked on top of the data processing bare die 20 via flip bonding, in which case the data processing bare die 20 and the optical chip 10 are electrically connected. For details, please refer to [further details omitted]. Figure 1 The optical chip 10 may include a flip-chip optical receiver array 110 and a flip-chip optical transmitter array 120. The optical receiver array 110 may include a first metal bonding terminal (not shown) and an optical receiver terminal (not shown) arranged opposite to each other. The optical transmitter array 120 may include a second metal bonding terminal (not shown) and an optical transmitter terminal (not shown) arranged opposite to each other. The first metal bonding terminal and the second metal bonding terminal are respectively bonded to the data processing bare chip 20 through a ball array (132, 134). That is to say, it can be referred to for further information. Figure 2The upper surface of the data processing bare die 20 has an area for bonding with the optical chip 10. Compared to traditional optical chips that require electrical connection to the data processing bare die via a silicon dielectric substrate and a TMSC interposer, this application reduces signal transmission loss and saves on material costs such as silicon dielectric substrates and TMSC interposers. Regarding the size of the optical chip 10, the ball arrays 132 and 134 can be selected as metal solder ball arrays (BGA Ball), bump arrays, or microbump arrays. It can be understood that the ball arrays 132 and 134 are used to achieve electrical connection and mechanical fixation, and are key components to ensure the normal operation of the optical interconnect structure, enabling signal transmission and physical support. The diameter of the metal solder balls typically ranges from 0.25 mm to 0.76 mm, the diameter of the bumps typically ranges from 100 μm to 150 μm, and the microbumps are the smallest, typically ranging from a few micrometers to tens of micrometers in diameter, and sometimes less than 2 μm. Based on different sizes, the fabrication difficulty of the solder balls, bumps, and microbumps gradually increases. In this specific embodiment, the ball arrays 132 and 134 are selected as micro-bump arrays.
[0041] Furthermore, to ensure that the optical signal transceiver of the optical chip 10 is perpendicular to the upper surface of the data processing bare chip 10, the optical receiving array 110 of this application can employ photodiodes (PDs), and the number of photodiodes can be multiple, arranged in an array. For example, the multiple photodiodes can be arranged in a regular hexagon, a regular square, or a regular pentagon, and this application does not impose any limitation on this arrangement. The photosensitive surface of the photodiode is flush with the upper surface of the data processing bare chip 20. The optical emitting array 120 can employ vertical-cavity surface-emitting lasers (VCSELs), and the number of VCSELs can be multiple, arranged in an array. Each laser includes multiple emission channels, and the multiple emission channels can be arranged in a regular hexagon, a regular square, or a regular pentagon, and this application does not impose any limitation on this arrangement. Furthermore, this application may employ four vertical-cavity surface-emitting lasers (VCSELs), and these four CCSELs may be configured to emit lasers with at least four wavelengths, which are modulated to convert N electrical data into optical signals in N optical channels. Optionally, the four wavelengths may be selected from a group of 1270nm, 1280nm, 1290nm, and 1300nm, or from a group of 1300nm, 1310nm, 1320nm, and 1330nm with smaller channel spacing. Optionally, each wavelength may be selected within the range of 1270nm to 1330nm as a CWDM channel to support optical signal transmission in high-speed (e.g., 100 Gbit / s or higher) data communication. In other embodiments, the optical chip 10 with a similar configuration may be formed with more than four wavelengths. Optionally, four or more wavelengths may be selected to have half the spacing compared to a nominal CWDM channel.
[0042] Vertical-cavity surface-emitting lasers (VCSELs) offer advantages such as low power consumption, ease of integration, low cost, and high reliability, making them widely used in optical communication, optical interconnects, and optical sensing. Compared to edge-emitting lasers (EELs), they offer unique advantages in optical communication and interconnects. For instance, more VCSELs can be placed within the same area, thereby increasing signal transmission density.
[0043] In one example, see Figures 1-3The co-packaged optical engine may further include a coupling fiber array (not shown), which may include a first coupling fiber array 510 and a second coupling fiber array 520. The first coupling fiber array 510 is coupled to the optical receiver of the optical receiver array 110, and the second coupling fiber array 520 is coupled to the optical transmitter of the optical transmitter array 120. Further, to match the aforementioned optical receiver array 110 and optical transmitter array 120, the first coupling fiber array 110 and the second coupling fiber array 120 may be selected as multi-core fiber arrays. The number of fibers in each fiber array matches the number of devices in the optical transmitter array 120 or the optical receiver array 110; for example, one photodiode corresponds to one coupled fiber, and one vertical-cavity surface-emitting laser corresponds to one coupled fiber. Using a multi-core fiber array can improve data transmission density.
[0044] In one example, in addition to the modules described above, the co-packaged optical engine may also include a host interface (not shown) configured to receive host data input via N 25G (NRZ) or 56G (PAM4) or 100G (PAM4) channels; and a digital processor (not shown) that processes the data signals via a clock restorer chip having N to N channels. Optionally, the digital processor processes the data signals via N to M channels of a gearbox, where N is a multiple of M. Optionally, the host interface is configured in one or more chips, the host interface including forward error correction (FEC) channel coding for controlling errors in data transmission over unreliable or noisy communication channels.
[0045] In one example, see Figure 3The co-packaged optical engine may further include an electrical processing die (not shown), which may include a first electrical processing die 310 and a second electrical processing die 320. The first electrical processing die 310 is disposed between the optical receiving array 110 and the data processing die 20; the second electrical processing die 320 is disposed between the optical emitting array 120 and the data processing die 20. Taking the first electrical processing die 310 and the optical receiving array 110 as an example, the first electrical processing die 310 is disposed below the optical receiving array 110, so it will not block the detection light path of the optical emitting array 110, thereby improving the light utilization rate of the optical emitting array 110, reducing losses, and improving heat dissipation. Specifically, the first electrical processing bare die 310 may have TSV vias, and the size of the ball array used on the side where the first electrical processing bare die 310 is soldered to the data processing bare die 20 is larger than the size of the ball array used between the first electrical processing bare die 310 and the optical receiving array 110; for example, the first electrical processing bare die 310 and the data processing bare die 20 are soldered using a bump array, and the first electrical processing bare die 310 and the optical receiving array 110 are soldered using a micro-bump array. The first electrical processing bare die 310 is used to provide modulation drive signals. Further, the first electrical processing bare die 310 can be selected from at least one of a transimpedance amplifier (TIA), a clock restorer, a high-speed memory (HBM), an electrical driver chip, a modulator driver chip, and a digital signal processing chip (DSP). For example, the first electrical processing bare die 310 is a traditional EIC chip, or it can be based on a traditional EIC chip with additional components such as a high-speed memory (HBM). Taking a traditional EIC chip as an example, a photodiode in the optical receiver array 110 individually detects each optical signal and converts it into a current signal that is passed to a transimpedance amplifier (TIA) and processed by the TIA module to generate a voltage signal. A digital signal processing (DSP) chip is configured to provide the module control and power required to operate the co-packaged optical engine. Optionally, the DSP chip includes a gearbox or retimer chip for converting analog signals to digital signals via N-to-N channel electrical data transmission, a digital processor for processing the digital signals, one or more interface devices for communicating with an external power supply, and a current driver for driving four laser chips.
[0046] Optionally, the modulator driver chip can use a PAM-N (N is an integer) modulation protocol or an NRZ modulation protocol to modulate the optical signal.
[0047] In one embodiment, reference may be made to Figure 2To achieve signal control between the data processing bare die 20 and the optical chip 10, the data processing bare die 20 integrates at least one of the following: an electric drive unit, an optical drive unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit. Figure 2 As shown, Unit 1, Unit 2, Unit 3, Unit 4...Unit N are integrated in the data processing bare die 20. Unit 1 can be selected as a transimpedance amplifier unit, and Unit 4 can be selected as a modulator driver unit, an electrical driver unit, or an optical driver unit. Unit 1 can be selected as a modulator driver unit (PHY), and Unit 3 can be selected as a clock recovery unit (CDR). Unit N can be selected and adjusted from the remaining units, such as selecting a digital signal processing unit (DSP), a memory unit, or a microcontroller. The main purpose is to integrate the main functional devices of the original EIC chip into the data processing bare die 20, thereby eliminating the intermediate EIC chip stage. The microcontroller is connected to a corresponding unit or device and is configured to control the operation of the digital signal processing DSP chip, the modulator driver unit, the transimpedance amplifier (TIA), and the interfaces therein.
[0048] In one embodiment, in addition to integrating the main functions of the original EIC chip into the data processing bare die 20, the main functional components of the EIC chip can also be integrated into the optical chip 10, making the optical chip 10 different from the traditional PIC chip and thus an EPIC chip. The EPIC chip can be fabricated based on CMOS technology. Similar to the previous embodiment, the optical chip 10 can integrate at least one of the following: an electrical drive unit, an optical drive unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit.
[0049] Furthermore, to better allocate components and achieve optimal transmission efficiency, the components integrated in the data processing die 20 can be configured to be different from or complementary to those integrated in the optical chip 10. For example, the electrical drive unit, optical drive unit, transimpedance amplifier unit, clock recovery unit, and modulator drive unit can be integrated into the optical chip 10, while the remaining memory units, microcontrollers, and digital signal processing units can be integrated into the data processing die 20, with corresponding electrical connections implemented. As another example, the electrical drive unit, optical drive unit, and modulator drive unit can be integrated into the optical chip 10, while the remaining transimpedance amplifier units, clock recovery units, modulator drive units, memory units, microcontrollers, and digital signal processing units can be integrated into the data processing die 20.
[0050] In one example, the data processing die 20 can be selected from any of a graphics processing unit (GPU), a custom AI accelerator (XPU), or an application-specific integrated circuit (ASIC) chip. The custom AI accelerator (XPU) is not a single chip, but a strategic concept for heterogeneous computing, designed to address complex computing needs through diverse hardware combinations. Its essence is "Right Tool for the Right Job," meaning using the most suitable hardware to handle a specific task, thereby improving overall system efficiency. The custom AI accelerator (XPU) can be, for example, at least one of a CPU, NPU, FPGA, or AI accelerator. For example, the XPU can be a CPU+GPU+NPU to accelerate the training of large-scale models. The ASIC chip includes a SerDes chip for encoding and decoding data via a DSP interface. Further, when the data processing die 20 is an ASIC chip, the ASIC chip can include an integrated modulation driver and a microcontroller. The integrated modulation driver is configured to drive optical signal modulation using PAM-4, PAM-6, or PAM-8 pulse amplitude modulation formats. The microcontroller is configured to control the operation of the integrated modulation driver.
[0051] Furthermore, as the computing power of a single optical engine module gradually approaches its physical limits, the collaborative operation of multiple optical engine modules has become an inevitable trend in order to meet the ever-increasing computing demands.
[0052] Based on this, such as Figure 4-5 This application also provides a co-packaged optical engine network, which may include several co-packaged optical engines 20a, 20b... as described above, with optical coupling connections between the co-packaged optical engines. Further, as... Figure 4As shown, the co-packaged optical engine 20a and co-packaged optical engine 20b can be optically coupled to their respective optical chips 10 using a fiber optic array. In this specific embodiment, when connecting the co-packaged optical engine module 20a and co-packaged optical engine module 20b via a fiber optic array, the optical transmitting array 120 in the co-packaged optical engine module 20a is optically coupled to the optical receiving array 110 in the co-packaged optical engine module 20b. The optical receiving array 120 of the co-packaged optical engine module 20a is then optically coupled to the optical transmitting array 110 of the previous co-packaged optical engine module, and the optical transmitting array 110 of the co-packaged optical engine module 20b is optically coupled to the optical receiving array 120 of the next co-packaged optical engine module, thereby achieving networking of the co-packaged optical modules. It is understandable that, in order to achieve optical interconnection between different optical engine modules, the functional device or protocol interface of the SWITCH chip can be further integrated into the co-packaged optical engine 20, or the SWITCH chip can be directly eliminated. In the configuration without the SWITCH chip, the connection between the co-packaged optical engine modules 20a and 20b is usually achieved by aggregating NVLinks modules into multiple groups, and transmitting and exchanging optical signals through the transceiver arrays of the respective optical engine modules.
[0053] Furthermore, such as Figure 5 As shown, if the switching chip (SWITCH) is not omitted, the co-packaged optical engine network can also include several switching chips (40), each of which is optically coupled between any two co-packaged optical engines (20a, 20b). Figure 5 As shown, the switching chip 40 also has an optical transmitter array 120 and an optical receiver array 110. The optical receiver array 110 on the switching chip 40 is optically coupled to the optical transmitter array 120 of the co-packaged optical engine 20a, and the optical transmitter array 120 on the switching chip 40 is optically coupled to the optical receiver array 110 of the co-packaged optical engine 20a. In this way, data access and interaction between different co-packaged optical engines can be realized.
[0054] In this specific embodiment, the transceiver arrays in different optical engine modules are connected via fiber optic arrays, allowing direct data exchange between different optical engine modules and memory data access between the high-speed storage units (HBMs) of different optical engine modules. This design not only reduces data transmission latency but also significantly improves the overall system throughput.
[0055] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be derived from practice of the embodiments. Furthermore, any embodiments described herein may be combined unless the foregoing disclosure expressly provides for reasons why one or more embodiments may not be combined.
[0056] Even though specific combinations of features are listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features can be combined in ways not specifically listed in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of the various embodiments includes each dependent claim combined with each other claim in the claim set. As used herein, the phrase “at least one of” in the list of items refers to any combination of these items, including a single member. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiple identical items.
[0057] When a component or one or more components (e.g., a laser emitter or one or more laser emitters) is described or required (within a single claim or across multiple claims) to perform or be configured to perform multiple operations, this language is intended to broadly cover a wide range of architectures and environments. For example, unless explicitly required otherwise (e.g., by using “first component” and “second component” or other language distinguishing components in the claims), this language is intended to cover a single component performing or configured to perform all operations, a group of components jointly performing or configured to perform all operations, a first component performing or configured to perform a first operation and a second component performing or configured to perform a second operation, or any combination of components performing or configured to perform operations. For example, when a claim takes the form “one or more components are configured to: perform X; perform Y; and perform Z,” the claim should be interpreted as meaning “one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (possibly different) components are configured to perform Z.”
[0058] The elements, actions, or instructions used herein should not be construed as critical or necessary unless explicitly stated otherwise. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and may be used interchangeably with “one or more.” Further, as used herein, the article “the” is intended to include one or more items referenced in combination with the article “the” and may be used interchangeably with “the one or more.” Additionally, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and may be used interchangeably with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Furthermore, as used herein, the terms “having,” “containing,” “with,” etc., are intended to be open-ended terms. Further, unless explicitly stated otherwise, the phrase “based on” is intended to mean “at least partially based on.” Furthermore, as used herein, unless otherwise expressly stated (e.g., when used in combination with “any one” or “only one of”), the term “or” is intended to be inclusive when used in series and can be used interchangeably with “and / or”. Further, for ease of description, spatially relative terms such as “below,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature to another element(s) or feature(s) illustrated in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of devices, apparatuses, and / or elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein shall be interpreted accordingly.
Claims
1. A co-packaged optical engine, characterized in that, Includes a data processing die and an optical chip stacked on top of the data processing die; The optical chip is configured to transmit and receive data in the form of optical signals; The data processing bare chip is configured to process the data; The data processing die is selected from any one of a graphics processing unit (GPU), a custom AI accelerator (XPU), or an application-specific integrated circuit (ASIC) chip; the data processing die is configured to perform calculations and training on the data; The optical chip includes an optical receiving array and an optical emitting array. The optical emitting array includes several VCSEL units arranged in an array, and the optical receiving array includes several photodetector units arranged in an array.
2. The co-packaged optical engine according to claim 1, characterized in that, The optical chip includes an optical receiver array, an optical transmitter array, a first coupling fiber array, and a second coupling fiber array; the first coupling fiber array is coupled to the optical receiver end of the optical receiver array, and the second coupling fiber array is coupled to the optical transmitter end of the optical transmitter array. and / or The coupled fiber array is a multi-core fiber array.
3. The co-packaged optical engine according to claim 2, characterized in that, The optical receiving array further includes a first metal bonding end disposed opposite to the optical receiving end, and the optical emitting array further includes a second metal bonding end disposed opposite to the optical emitting end. The first metal bonding end and the second metal bonding end are respectively bonded to the data processing bare chip through a ball array.
4. The co-packaged optical engine according to claim 2, characterized in that, The optical receiving array and the optical transmitting array are flip-chip structures.
5. The co-packaged optical engine according to claim 2, characterized in that, Also includes: Electrically processed bare core, including a first electrically processed bare core and a second electrically processed bare core; The first electrical processing bare chip is disposed between the optical receiving array and the data processing bare chip; The second electrical processing bare core is disposed between the optical emitting array and the data processing bare core.
6. The co-packaged optical engine according to claim 5, characterized in that, The electrical processing bare chip is selected from at least one of the following: transimpedance amplifier, clock restorer, high-speed memory, electric drive chip, modulator drive chip, and digital signal processing chip.
7. The co-packaged optical engine according to claim 1, characterized in that, The data processing bare chip integrates at least one of the following: an electric drive unit, an optical drive unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit; and / or The optical chip integrates at least one of the following: an electric drive unit, an optical drive unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit. Furthermore, the devices integrated in the data processing bare chip are different from or complementary to the devices integrated in the optical chip.
8. The co-packaged optical engine according to claim 1, characterized in that, When the data processing bare chip is an application-specific integrated circuit (ASIC) chip, the ASIC chip includes an integrated modulation driver and a microcontroller. The integrated modulation driver is configured to drive optical signal modulation using pulse amplitude modulation (PAM-4), pulse amplitude modulation (PAM-6), or pulse amplitude modulation (PAM-8) formats.
9. A co-packaged optical engine networking system, characterized in that, It includes several co-packaged optical engines as described in any one of claims 1-8, wherein each of the co-packaged optical engines is optically coupled to the others.
10. The co-packaged optical engine networking according to claim 9, characterized in that, Each of the co-packaged optical engines is optically coupled to its respective optical chip using an optical fiber array.
11. The co-packaged optical engine networking according to claim 9, characterized in that, It also includes several switching chips, one of which is optically coupled between any two co-packaged optical engines.