A back contact solar cell and photovoltaic module

Abstract

The embodiment of the present disclosure relates to the technical field of solar cells, and provides a main-grid-free back contact cell and a photovoltaic module. The main-grid-free back contact cell comprises a substrate, a first semiconductor doped layer, a second semiconductor doped layer, a first electrode group and a second electrode group. The first electrode group is in electrical contact with the corresponding first semiconductor doped layer, and the first electrode group comprises a plurality of first sub-grid groups, each of which comprises a plurality of first sub-grids arranged at intervals along a first direction. The second electrode group is in electrical contact with the corresponding second semiconductor doped layer, and the second electrode group comprises a plurality of second sub-grid groups, each of which comprises a plurality of second sub-grids arranged at intervals along the first direction. The first sub-grid groups and the second sub-grid groups are alternately arranged at intervals along a second direction, and the first sub-grids and the second sub-grids extend along the first direction. Compared with a conventional main-grid back contact cell, the main-grid-free back contact cell provided by the embodiment of the present disclosure not only reduces the production cost, but also improves the yield of the back contact cell.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, and in particular to a gridless back-contact solar cell and photovoltaic module. Background Technology

[0002] In the manufacturing process of crystalline silicon solar cells, silicon materials and silver paste constitute the main cost components. Silicon materials account for approximately 60-70% of the cost, while silver paste accounts for approximately 20-30%. Back-contact solar cells, with all electrodes arranged on the back side, also face the problem of high silver paste usage and excessive cost. Furthermore, the cross-arrangement of positive and negative electrodes increases the risk of short circuits. Traditional back-contact solar cells with a main grid have a main grid welding point, and a secondary grid with opposite polarity exists near the main grid, making them prone to short circuits during manufacturing. Additionally, insulating adhesive must be applied before welding the back-contact solar cells, which not only increases process complexity but may also reduce cell efficiency and yield.

[0003] Therefore, how to reduce the amount of silver paste used and improve battery efficiency and yield has become an urgent technical problem to be solved in the field of back contact battery technology. Summary of the Invention

[0004] This disclosure provides a gridless back-contact cell and photovoltaic module, aiming to reduce the cost of silver paste at the cell end while improving the yield of the back-contact cell.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a gridless back contact battery, comprising: a substrate, the substrate including a first surface and a second surface opposite to each other; a first semiconductor doped layer and a second semiconductor doped layer located on the second surface, wherein the first doping element in the first semiconductor doped layer and the second doping element in the second semiconductor doped layer have different conductivity types; a first electrode group, the first electrode group being electrically contacted with a corresponding first semiconductor doped layer, the first electrode group including a plurality of first sub-gate groups, the first sub-gate groups including a plurality of first sub-gates spaced apart along a first direction; and a second electrode group, the second electrode group being electrically contacted with a corresponding second semiconductor doped layer, the second electrode group including a plurality of second sub-gate groups, the second sub-gate groups including a plurality of second sub-gates spaced apart along the first direction; wherein the first sub-gate groups and the second sub-gate groups are alternately spaced along a second direction, and both the first sub-gates and the second sub-gates extend along the first direction.

[0006] In some embodiments, the first electrode group further includes a first edge sub-gate, which makes electrical contact with the first first sub-gate arranged along the first direction in the first sub-gate group; the second electrode group further includes a second edge sub-gate, which makes electrical contact with the last second sub-gate arranged along the first direction in the second sub-gate group; wherein the first edge sub-gate and the second edge sub-gate both extend along the second direction.

[0007] In some embodiments, the first direction and the second direction are perpendicular to each other.

[0008] In some embodiments, the substrate corresponding to the first edge subgate has a first edge doped region extending along the second direction; the substrate corresponding to the second edge subgate has a second edge doped region extending along the second direction.

[0009] In some embodiments, the spacing between adjacent first sub-gate groups and second sub-gate groups is 0.8 mm to 2 mm.

[0010] In some embodiments, in the first sub-gate group, the spacing between adjacent first sub-gates is 0.5mm to 1mm, and in the second sub-gate group, the spacing between adjacent second sub-gates is 0.5mm to 1mm.

[0011] In some embodiments, in the second sub-gate group, the distance between the second sub-gate closest to the first edge sub-gate in the first direction and the first edge sub-gate is 0.5mm to 1mm, and in the first sub-gate group, the distance between the first sub-gate closest to the second edge sub-gate in the first direction and the second edge sub-gate is 0.5mm to 1mm.

[0012] In some embodiments, the substrate is an N-type silicon wafer or a P-type silicon wafer.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, including: a plurality of gridless back contact cells as described in the above embodiments, adjacent back contact cells being interconnected via a solder ribbon structure, the solder ribbon structure including a first solder ribbon group and a second solder ribbon group, the first solder ribbon group including a plurality of first solder ribbons, the second solder ribbon group including a plurality of second solder ribbons, the first solder ribbons and the second solder ribbons being alternately spaced along a first direction; the first solder ribbons being electrically connected to a plurality of first sub-gates of the first sub-gate group through gaps between adjacent second sub-gates in the second sub-gate group, and the second solder ribbons being electrically connected to a plurality of second sub-gates of the second sub-gate group through gaps between adjacent first sub-gates in the first sub-gate group; an encapsulating film covering the surface of the gridless back contact cells; and a cover plate located on the surface of the encapsulating film away from the gridless back contact cells.

[0014] In some embodiments, in the first solder strip group, the first solder strip closest to the first edge subgate in the first direction is electrically connected to the first edge subgate, and in the second solder strip group, the second solder strip closest to the second edge subgate in the first direction is electrically connected to the second edge subgate.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] This disclosure provides a gridless back-contact battery, comprising a first electrode group and a second electrode group. Both the first and second electrode groups are composed of fine grid lines extending along a first direction and alternately spaced along a second direction, eliminating the need for a main grid. This simplifies the manufacturing process and reduces material usage. The absence of a main grid reduces the light-blocking area and increases the effective light absorption area, thereby improving photoelectric conversion efficiency. Furthermore, the gridless design eliminates stress concentration caused by the main grid, resulting in a more uniform overall stress distribution within the battery cell. Additionally, the use of insulating gaps between sub-grids effectively mitigates short-circuit risks. This disclosure not only reduces production costs but also improves the yield of back-contact batteries. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a secondary grid of a back-contact battery without a main grid, provided in an embodiment of this disclosure;

[0019] Figure 2 This is a schematic diagram of a gridless back contact battery provided in an embodiment of the present disclosure;

[0020] Figure 3 A schematic diagram of the structure of a secondary grid of a back-contact battery without a main grid, provided in an embodiment of this disclosure;

[0021] Figure 4 This is a schematic diagram of another gridless back contact battery provided in an embodiment of the present disclosure;

[0022] Figure 5 This is a schematic diagram of a sub-gate with a solder strip connection provided in an embodiment of the present disclosure;

[0023] Figure 6 A top view of the structure of a photovoltaic module provided in an embodiment of this application;

[0024] Figure 7 This is a cross-sectional schematic diagram of the structure of a photovoltaic module provided in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] A gridless back contact cell 100, a substrate 110, a first semiconductor doped layer 120, a second semiconductor doped layer 130, a first electrode group 140, a second electrode group 150, a first edge doped region 160, and a second edge doped region 170.

[0027] The first electrode group 140 includes a first sub-gate group 141 and a first edge sub-gate 142, the first sub-gate group 141 including a first sub-gate 1411; the second electrode group 150 includes a second sub-gate group 151 and a second edge sub-gate 152, the second sub-gate group 151 including a second sub-gate 1511.

[0028] The solder ribbon structure 200, the encapsulating film 300, and the cover plate 400; the solder ribbon structure 200 includes a first solder ribbon group 210 and a second solder ribbon group 220; the first solder ribbon group 210 includes a first solder ribbon 211, and the second solder ribbon group 220 includes a second solder ribbon 221. Detailed Implementation

[0029] As the background technology shows, existing back-contact batteries with main grids not only use a large amount of electrode silver paste, leading to excessively high costs, but also have main grid PAD points with opposite polarity near them. This makes them prone to short circuits during manufacturing, requiring the application of insulating adhesive before soldering the back contact cells. This not only increases process complexity but may also reduce battery efficiency and yield. Furthermore, the cross-arrangement of positive and negative electrodes increases the risk of short circuits.

[0030] This disclosure provides a gridless back contact battery, which, compared to conventional grid-connected back contact batteries, eliminates the grid structure and achieves electrode functionality through optimized sub-grid arrangement and connection, thereby reducing silver paste usage. Furthermore, by setting insulating gaps between sub-grids, the risk of short circuits is mitigated. This disclosure not only reduces production costs but also improves the yield of back contact batteries.

[0031] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0034] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may cover both above and below orientation depending on the context in which the term is used, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0035] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0036] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. Furthermore, when describing a component as "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0037] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. The formation or provision of a second component above or on a first component, or on the surface of a first component, or on one side of a first component, may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be present between the first and second components, thereby preventing direct contact between the first and second components. For simplicity and clarity, various components may be drawn at different scales. In the drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, the formation or provision of a second component on the surface of a first component refers to direct contact between the first and second components. The term "component" may refer to a layer, film, region, portion, structure, etc.

[0038] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0039] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0040] Figure 1 This is a schematic diagram of the structure of a secondary grid of a back-contact battery without a main grid, provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a gridless back contact battery provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of a secondary grid of a back-contact battery without a main grid, provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another gridless back contact battery provided in an embodiment of this disclosure.

[0041] refer to Figures 1 to 4 A gridless back contact battery 100 includes:

[0042] The substrate 110 includes a first surface and a second surface that are opposite each other.

[0043] The first semiconductor doped layer 120 and the second semiconductor doped layer 130 are located on the second surface. The first doped element in the first semiconductor doped layer 120 and the second doped element in the second semiconductor doped layer 130 have different conductivity types.

[0044] The first electrode group 140 is electrically contacted with the corresponding first semiconductor doped layer 120. The first electrode group 140 includes a plurality of first sub-gate groups 141, and the first sub-gate groups 141 include a plurality of first sub-gates 1411 spaced apart along a first direction.

[0045] The second electrode group 150 is electrically contacted with the corresponding second semiconductor doped layer 130. The second electrode group 150 includes a plurality of second sub-gate groups 151, and the second sub-gate groups 151 include a plurality of second sub-gates 1511 spaced apart along a first direction.

[0046] The first sub-gate group 141 and the second sub-gate group 151 are arranged alternately along the second direction, and both the first sub-gate 1411 and the second sub-gate 1511 extend along the first direction.

[0047] Specifically, substrate 110 is the core component of the solar cell, used to absorb light energy and generate photogenerated carriers (electrons and holes). In some embodiments, the material of substrate 110 can be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material can be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing monocrystalline and amorphous states is called microcrystalline). For example, silicon can be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon, then the material of substrate 110 can include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In some embodiments, the material of substrate 110 can also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, copper indium selenide, etc. Materials can also be silicon carbide, organic materials, or multi-component compounds. Multi-component compounds can include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenide, etc.

[0048] The substrate 110 can also be a sapphire substrate, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0049] In a back-contact battery, the first surface is typically the illuminated surface, used to receive incident light, while the second surface, serving as the backlight surface, is used to arrange electrodes and other functional layers. The second surface includes alternating first semiconductor doped layers 120 and second semiconductor doped layers 130. The first semiconductor doped layer 120 and the second semiconductor doped layer 130 correspond to different doping types, forming a highly efficient pn junction, which promotes the efficient separation and transport of electrons and holes.

[0050] The first sub-gate group 141 consists of several first sub-gates 1411, each of which is in direct contact with the first semiconductor doped layer 120 and is responsible for collecting photogenerated carriers generated in that region. The second sub-gate group 151 consists of several second sub-gates 1511, each of which is in direct contact with the second semiconductor doped layer 130 and is responsible for collecting photogenerated carriers generated in that region. These sub-gates are distributed on the back of the battery for efficiently collecting current and transferring it to external circuitry. Figure 1 As can be seen, the first and second sub-grids are arranged in an alternating pattern on the back of the battery, forming a two-dimensional grid structure. This alternating arrangement ensures a uniform current distribution between the first and second semiconductor doped layers, reducing energy loss caused by excessively high local current density. Furthermore, this alternating arrangement maximizes the use of space on the back of the battery, improving current collection efficiency.

[0051] In traditional solar cell designs, the main grid line is responsible for collecting the current gathered by the sub-grid and directing it to the external circuitry. However, the main grid line blocks some incident light, reducing the cell's light absorption efficiency. This embodiment eliminates the main grid line and, by optimizing the sub-grid layout, directly achieves current collection and dissipation, thereby improving both light absorption efficiency and current collection efficiency, while simultaneously reducing production costs.

[0052] The embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0053] In one possible implementation, the first electrode group 140 further includes a first edge sub-gate 142, which is in electrical contact with the first first sub-gate 1411 arranged along a first direction in the first sub-gate group 141.

[0054] The second electrode group 150 also includes a second edge sub-gate 152, which is in electrical contact with the last second sub-gate 1511 of the second sub-gate group 151 arranged along the first direction.

[0055] The first edge sub-gate 142 and the second edge sub-gate 152 both extend along the second direction.

[0056] For example, the edge sub-grids are typically located around the perimeter of the back of the battery for easy connection to external electrodes. The first edge sub-grid 142 is electrically contacted with the leftmost first sub-grid 1411 of all first sub-grid groups 141, converging the current in the first sub-grid group 141 and directing it to an external circuit. The second edge sub-grid 152 is electrically contacted with the rightmost second sub-grid 1511 of all second sub-grid groups 151, converging the current in the second sub-grid group 151 and directing it to an external circuit. The presence of the edge sub-grids allows the current from all sub-grid groups to be effectively converged, reducing resistance loss and improving current output efficiency.

[0057] In one possible implementation, the first direction and the second direction are perpendicular to each other.

[0058] Optionally, the first edge sub-gate 142 is perpendicular to the first first sub-gate 1411 arranged along the first direction in the first sub-gate group 141; the second edge sub-gate 152 is perpendicular to the last second sub-gate 1511 arranged along the first direction in the second sub-gate group 151.

[0059] It should be understood that by using a vertical connection, the edge sub-gate can better distribute the current on the sub-gate group evenly to the external circuit, avoiding hot spot effects or energy loss caused by excessive local current density.

[0060] In one possible implementation, the substrate 110 corresponding to the first edge subgate 142 has a first edge doped region 160, which extends along a second direction.

[0061] The substrate 110 corresponding to the second edge subgate 152 has a second edge doped region 170, which extends along a second direction.

[0062] The first edge sub-gate 142 is in direct contact with the first edge doped region 160, and the second edge sub-gate 152 is in direct contact with the second edge doped region 170. The doping type of the first edge doped region 160 is the same as that of the first semiconductor doped layer 120, and the doping type of the second edge doped region is the same as that of the second semiconductor doped layer 130.

[0063] In one possible implementation, the spacing L1 between adjacent first sub-gate group 141 and second sub-gate group 151 is 0.8mm to 2mm.

[0064] When the spacing is less than 0.8 mm, the physical gap between the first sub-gate group 141 and the second sub-gate group 151 may increase the risk of local contact due to manufacturing tolerances or material properties, potentially leading to a short circuit. When the spacing is greater than 2 mm, the path length for photogenerated carriers to transport from the semiconductor doped layer to the sub-gate increases significantly, resulting in increased lateral resistance and reduced carrier collection efficiency. Within the range of 0.8 mm to 2 mm, sufficient physical spacing can ensure insulation between the first sub-gate group 141 and the second sub-gate group 151 while avoiding current transmission losses caused by excessive spacing, thus achieving an optimal balance between insulation safety and electrical performance.

[0065] For example, the spacing between adjacent first sub-gate group 141 and second sub-gate group 151 can be 0.85mm. The first sub-gate 1411 and the second sub-gate 1511 are respectively responsible for collecting photogenerated carriers from the first semiconductor doped layer 120 and the second semiconductor doped layer 130 of the substrate. The two are physically separated to avoid the risk of short circuit caused by direct contact. The 0.85mm spacing can ensure insulation and avoid the decrease in current collection efficiency caused by excessive spacing.

[0066] In one possible implementation, in the first sub-gate group 141, the spacing L2 between adjacent first sub-gates 1411 is 0.5mm~1mm, and in the second sub-gate group 151, the spacing L3 between adjacent second sub-gates 1511 is 0.5mm~1mm.

[0067] When the spacing is less than 0.5 mm, bridging may occur between adjacent sub-gates during the silver paste printing process due to process errors or material flowability, leading to short circuits between sub-gates with different potentials. When the spacing is greater than 1 mm, the path length for carriers to travel from the semiconductor doped layer to the sub-gate increases, significantly raising the lateral resistance. Carriers in some areas cannot be collected in time, resulting in increased resistance loss. Within the range of 0.5 mm to 1 mm, a reasonable spacing can avoid the risk of short circuits while ensuring efficient carrier collection, and simultaneously reduce the number of sub-gates to lower material costs.

[0068] For example, the spacing between adjacent first sub-gates 1411 in the first sub-gate group 141 can be 0.75 mm, and the spacing between adjacent second sub-gates 1511 in the second sub-gate group 151 is 0.75 mm. On the one hand, the 0.75 mm spacing can effectively prevent silver paste bridging short circuits, while reducing the number of sub-gates to control costs; on the other hand, this spacing shortens the path for carriers to transfer from the first semiconductor doped layer 120 and the second semiconductor doped layer 130 to the sub-gate, reducing lateral resistance loss and thus improving current collection efficiency.

[0069] In one possible implementation, in the second sub-gate group 151, the distance L4 between the second sub-gate 1511, which is closest to the first edge sub-gate 142 in the first direction, and the first edge sub-gate 142 is 0.5mm to 1mm, and in the first sub-gate group 141, the distance L5 between the first sub-gate 1411, which is closest to the second edge sub-gate 152 in the first direction, and the second edge sub-gate 152 is 0.5mm to 1mm.

[0070] When the spacing is less than 0.5 mm, local contact may occur between the edge sub-gate (first edge sub-gate 142 or second edge sub-gate 152) and the adjacent sub-gate group (second sub-gate group 151 or first sub-gate group 141) due to manufacturing tolerances or material defects, causing short circuits between sub-gates of different polarities. When the spacing is greater than 1 mm, the path for photogenerated carriers to travel from the sub-gate to the edge sub-gate is significantly prolonged, resulting in increased lateral resistance and decreased current collection efficiency. Within the range of 0.5 mm to 1 mm, sufficient spacing can ensure electrical isolation between the edge sub-gate and the adjacent sub-gate group while maintaining an efficient current transport path.

[0071] For example, assuming the first direction is a horizontal direction from left to right, the spacing between the second edge sub-gate 152 and the last first sub-gate 1411 at the left end of the first sub-gate group 141 can be 0.75 mm. This 0.75 mm spacing effectively avoids accidental contact between the edge sub-gate and adjacent sub-gate groups or indirect conduction through minor defects, preventing short circuits. Furthermore, this spacing shortens the carrier transport distance from the first sub-gate 1411 and the second sub-gate 1511 to the edge sub-gate, reducing lateral resistance loss and improving current collection efficiency.

[0072] In one possible implementation, the substrate is an N-type silicon wafer or a P-type silicon wafer.

[0073] Specifically, the substrate 110 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which can be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be any one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0074] It should be noted that the choice between an N-type silicon wafer and a P-type silicon wafer for the substrate 110 depends on the specific application requirements and design goals, and this disclosure does not limit this.

[0075] It should be understood that the role of doped regions is to alter the conductivity of the substrate by introducing impurity atoms, thus forming n-type or p-type semiconductor materials. The n-type region is rich in electrons (negative charge carriers), while the p-type region is rich in holes (positive charge carriers). When the n-type and p-type regions combine, a pn junction is formed between them. The pn junction effectively separates the current generated by photogenerated charge carriers (electron-hole pairs) and directs it as electrical output.

[0076] In this embodiment, the doped region is constructed in the following two possible ways:

[0077] Method 1: The first semiconductor doped layer 120 is an N-type doped region, and the second semiconductor doped layer 130 is a P-type doped region.

[0078] For example, in this implementation, a portion of the substrate 110 is doped into n-type and another portion into p-type. When sunlight shines on the battery, electron-hole pairs are generated in both the n-type and p-type regions. Under the action of the pn junction, electrons are pushed towards the n-type region, and holes are pushed towards the p-type region. The first sub-gate 1411 and the first edge sub-gate 142 connect to the n-type region and are responsible for collecting and exporting electrons; the second sub-gate 1511 and the second edge sub-gate 152 connect to the p-type region and are responsible for collecting and exporting holes.

[0079] Method 2: The first semiconductor doping layer 120 is a P-type doped region, and the second semiconductor doping layer 130 is an N-type doped region.

[0080] In this implementation, a portion of the substrate 110 is doped into p-type and another portion into n-type. Similarly, when sunlight shines on the battery, electron-hole pairs are generated in both the p-type and n-type regions. Under the influence of the pn junction, holes are pushed towards the p-type region, and electrons are pushed towards the n-type region. The first sub-gate 1411 and the first edge sub-gate 142 connect to the p-type region, responsible for collecting and exporting holes; the second sub-gate 1511 and the second edge sub-gate 152 connect to the n-type region, responsible for collecting and exporting electrons. Specifically, the choice of doping method depends primarily on the specific process requirements and technical parameters, and this disclosure does not limit this aspect.

[0081] This disclosure provides a gridless back-contact battery, comprising a first electrode group and a second electrode group. Both the first and second electrode groups are composed of fine grid lines extending along a first direction and alternately spaced along a second direction, eliminating the need for a main grid. This simplifies the manufacturing process and reduces material usage. The absence of a main grid reduces the light-blocking area and increases the effective light absorption area, thereby improving photoelectric conversion efficiency. Furthermore, the gridless design eliminates stress concentration caused by the main grid, resulting in a more uniform overall stress distribution within the battery cell. Additionally, the use of insulating gaps between sub-grids effectively mitigates short-circuit risks. This disclosure not only reduces production costs but also improves the yield of back-contact batteries.

[0082] Accordingly, another embodiment of this disclosure also provides a photovoltaic module, including:

[0083] Multiple gridless back contact batteries 100 as described in the above embodiments are interconnected via a solder ribbon structure 200. The solder ribbon structure 200 includes a first solder ribbon group 210 and a second solder ribbon group 220. The first solder ribbon group 210 includes a plurality of first solder ribbons 211, and the second solder ribbon group 220 includes a plurality of second solder ribbons 221. The first solder ribbons 211 and the second solder ribbons 221 are staggered along a first direction. The first solder ribbons 211 are electrically connected to a plurality of first sub-gates 1411 of the first sub-gate group 141 through the gaps between adjacent second sub-gates 1511 in the second sub-gate group 151, and the second solder ribbons 221 are electrically connected to a plurality of second sub-gates 1511 of the second sub-gate group 151 through the gaps between adjacent first sub-gates 1411 in the first sub-gate group 141.

[0084] The encapsulating film 300 covers the surface of the gridless back contact battery 100.

[0085] Cover plate 400 is located on the surface of the encapsulating film 300 away from the back contact battery 100 without main grid.

[0086] refer to Figure 6 Adjacent gridless back contact cells 100 can be connected by a first solder strip 211 and a second solder strip 221.

[0087] refer to Figure 7 The encapsulating film 300 is used to cover the surface of the gridless back contact battery 100.

[0088] The encapsulating film 300 can be made of organic encapsulating films such as ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyvinyl butyral (PVB) film.

[0089] In some embodiments, the encapsulating film 300 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the gridless back contact battery 100, and the second encapsulating layer covers the other of the front or back sides of the gridless back contact battery 100. Specifically, at least one of the first encapsulating layer or the second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film; or, at least one of the first encapsulating layer or the second encapsulating layer can also be an EP film, EPE film, or PVP film. Among them, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film, POE film, and EVA film; and PVP film refers to a co-extruded film formed by stacking POE film, EVA film, and POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0090] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module no longer has the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 300.

[0091] refer to Figure 7 The cover plate 400 is used to cover the encapsulating film 300 away from the surface of the gridless back contact battery 100.

[0092] The cover plate 400 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. In some embodiments, the surface of the cover plate 400 facing the encapsulating film 300 can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate 400 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0093] In one possible implementation, in the first solder strip group 210, the first solder strip 211, which is closest to the first edge subgate 142 in the first direction, is electrically connected to the first edge subgate 142; and in the second solder strip group 220, the second solder strip 221, which is closest to the second edge subgate 152 in the first direction, is electrically connected to the second edge subgate 152.

[0094] For example, see Figure 5As shown, the first solder strip 211 passes through the gap between adjacent second sub-gates 1511 in the second sub-gate group 151, intersects perpendicularly with a plurality of first sub-gates 1411 in the first sub-gate group 141, and covers and connects with the first edge sub-gate 142.

[0095] The second solder strip 221 passes through the gap between adjacent first sub-gates 1411 in the first sub-gate group 141, intersects perpendicularly with a plurality of second sub-gates 1511 in the second sub-gate group 151, and covers and connects with the second edge sub-gate 152.

[0096] Specifically, the solder ribbon is a key component used to connect the sub-gates and conduct current to the external circuitry. It is typically made of a material with good conductivity, such as silver or copper. For example, the first solder ribbon 211 is perpendicularly connected to several first sub-gates 1411 of the first sub-gate group 141 through the gaps between adjacent second sub-gates 1511 in the second sub-gate group 151. This means that the first solder ribbon 211 spans the gaps in the second sub-gate groups 151 and is directly connected to the first sub-gates 1411, ensuring that the current in all the first sub-gate groups 141 can be effectively collected and conducted. The first solder ribbon 211 is used to draw out the first polarity of the gateless back contact battery 100. If the first semiconductor doped layer 120 is an n-type region, the first solder ribbon 211 is responsible for drawing out electrons; if the first semiconductor doped layer 120 is a p-type region, the first solder ribbon 211 is responsible for drawing out holes. Similarly, the second solder ribbon 221 is perpendicularly connected to several second sub-gates 1511 of the second sub-gate group 151 through the gaps between adjacent first sub-gates 1411 in the first sub-gate group 141, to ensure that the current in all second sub-gate groups 151 can be effectively collected and discharged. The second solder ribbon 221 is used to lead out the second polarity of the gateless back contact cell. If the second semiconductor doped layer 130 is a p-type region, the second solder ribbon 221 is responsible for leading out holes; if the second semiconductor doped layer 130 is an n-type region, the second solder ribbon 221 is responsible for leading out electrons.

[0097] By efficiently collecting and discharging the current from the sub-grid using solder ribbons, the current transmission path length is reduced, thus lowering resistance loss. Properly designing the path and spacing of the solder ribbons ensures sufficient electrical isolation between ribbons of different polarities, preventing short circuits and other electrical faults, thereby significantly improving the overall performance of the solar cell.

[0098] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A gridless back contact battery, characterized in that, include: A substrate, the substrate comprising opposing first and second surfaces; The first semiconductor doped layer and the second semiconductor doped layer are located on the second surface, wherein the first doping element in the first semiconductor doped layer and the second doping element in the second semiconductor doped layer have different conductivity types. A first electrode group, the first electrode group being electrically contacted with the corresponding first semiconductor doped layer, the first electrode group including a plurality of first sub-gate groups, the first sub-gate group including a plurality of first sub-gates spaced apart along a first direction; The second electrode group is electrically contacted with the corresponding second semiconductor doped layer. The second electrode group includes a plurality of second sub-gate groups, and the second sub-gate groups include a plurality of second sub-gates spaced apart along the first direction. The first sub-gate group and the second sub-gate group are arranged alternately along the second direction, and both the first sub-gate and the second sub-gate extend along the first direction.

2. The gridless back contact battery according to claim 1, characterized in that: The first electrode group further includes a first edge sub-gate, which is electrically connected to the first first sub-gate arranged along the first direction in the first sub-gate group; The second electrode group further includes a second edge sub-gate, which is electrically connected to the last second sub-gate of the second sub-gate group arranged along the first direction; Both the first edge sub-gate and the second edge sub-gate extend along the second direction.

3. The gridless back contact battery according to claim 2, characterized in that: The first direction and the second direction are perpendicular to each other.

4. The gridless back contact battery according to claim 2, characterized in that: The substrate corresponding to the first edge subgate has a first edge doped region, which extends along the second direction; The substrate corresponding to the second edge subgate has a second edge doped region, which extends along the second direction.

5. The gridless back contact battery according to any one of claims 1 to 4, characterized in that: The spacing between adjacent first sub-gate groups and second sub-gate groups is 0.8mm to 2mm.

6. The gridless back contact battery according to any one of claims 1 to 4, characterized in that: In the first sub-gate group, the spacing between adjacent first sub-gates is 0.5mm to 1mm, and in the second sub-gate group, the spacing between adjacent second sub-gates is 0.5mm to 1mm.

7. The gridless back contact battery according to claim 4, characterized in that: In the second sub-gate group, the distance between the second sub-gate closest to the first edge sub-gate in the first direction and the first edge sub-gate is 0.5mm~1mm. In the first sub-gate group, the distance between the first sub-gate closest to the second edge sub-gate in the first direction and the second edge sub-gate is 0.5mm~1mm.

8. The gridless back contact battery according to any one of claims 1 to 4, characterized in that: The substrate is an N-type silicon wafer or a P-type silicon wafer.

9. A photovoltaic module, characterized in that, include: Multiple gridless back contact cells as described in any one of claims 1 to 8, wherein adjacent back contact cells are interconnected via a solder ribbon structure, the solder ribbon structure comprising a first solder ribbon group and a second solder ribbon group, the first solder ribbon group comprising a plurality of first solder ribbons, the second solder ribbon group comprising a plurality of second solder ribbons, the first solder ribbons and the second solder ribbons being alternately spaced along a first direction; The first solder strip is electrically connected to a plurality of first sub-gates of the first sub-gate group through the gap between adjacent second sub-gates in the second sub-gate group, and the second solder strip is electrically connected to a plurality of second sub-gates of the second sub-gate group through the gap between adjacent first sub-gates in the first sub-gate group; An encapsulating film that covers the surface of the gridless back contact battery; A cover plate located on the surface of the encapsulating film away from the gridless back contact battery.

10. The photovoltaic module according to claim 9, characterized in that: In the first solder strip group, the first solder strip closest to the first edge sub-gate in the first direction is electrically connected to the first edge sub-gate, and in the second solder strip group, the second solder strip closest to the second edge sub-gate in the first direction is electrically connected to the second edge sub-gate.

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