Back contact solar cells, battery modules and photovoltaic systems

Abstract

This application relates to the field of solar cell technology, and provides a back-contact solar cell, a cell module, and a photovoltaic system. In the back-contact solar cell, a first doped structure and a second doped structure are alternately arranged in a first direction. The first doped structure includes a plurality of first doped portions spaced apart along a second direction, with a first gap between adjacent first doped portions. The second doped structure includes a plurality of second doped portions spaced apart along the second direction, with a second gap between adjacent second doped portions. This can reduce parasitic absorption on the back side, improve the bifaciality of the back-contact solar cell, and effectively reduce metallization recombination, thereby improving the efficiency of the back-contact solar cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a back-contact solar cell, a cell module, and a photovoltaic system. Background Technology

[0002] Currently, in solar cells, back-contact solar cells are cells in which both the emitter and base contact electrodes are placed on the back of the cell (the non-light-receiving surface). The light-receiving surface of this cell is not blocked by any metal electrodes, thereby effectively increasing the short-circuit current of the cell.

[0003] In related technologies, in back-contact solar cells, both the doped layer and the electrode are designed on the back side. On the back side of the silicon wafer, P-type doped layers and N-type doped layers are arranged alternately in one direction. However, existing back-contact solar cells have low bifaciality. At the same time, in existing technologies, the electrodes of the fine grid on the back side usually completely penetrate the passivation layer and contact the doped layer. The area of ​​its metallized region is large, resulting in high metallization recombination and thus low efficiency of the back-contact solar cell. Utility Model Content

[0004] This application provides a back-contact solar cell, a battery module, and a photovoltaic system.

[0005] This application is implemented as follows: the back-contact solar cell of this application embodiment includes:

[0006] Silicon wafers;

[0007] A plurality of first doped structures and a plurality of second doped structures are stacked on the back side of the silicon wafer. The first doped structures and the second doped structures are arranged alternately along a first direction and all extend along a second direction, which intersects the first direction. Each first doped structure includes a plurality of first doped portions spaced apart along the second direction, with a first gap between adjacent first doped portions. Each second doped structure includes a plurality of second doped portions spaced apart along the second direction, with a second gap between adjacent second doped portions.

[0008] A back passivation film layer, the back passivation film layer covering the back side;

[0009] A plurality of first fine gates are disposed on the back passivation film layer, the first fine gates being located on the first doped structure, the first fine gates penetrating at least a portion of the back passivation film layer corresponding to the first doped portion to make conductive contact with the first doped portion, and the first fine gates being continuous at least a portion of the first gap; and

[0010] A plurality of second fine gates are disposed on the back passivation film layer, the second fine gates are located on the second doped structure, the second fine gates penetrate at least a portion of the back passivation film layer corresponding to the second doped portion to make conductive contact with the second doped portion, and the first fine gates are continuous at at least a portion of the second gap.

[0011] In some embodiments, the first fine gate does not penetrate the back passivation film layer at least partially in the first gap; and / or

[0012] At least in part of the second gap, the second fine gate does not penetrate the back passivation film layer.

[0013] In some embodiments, within the same first fine gate, the contact area between the first fine gate and a single first doped portion is greater than the contact area between the first fine gate and the silicon wafer at a single first gap; and / or

[0014] In the same second fine gate, the contact area between the second fine gate and a single second doped portion is greater than the contact area between the second fine gate and the silicon wafer at a single second gap.

[0015] In some embodiments, the unit length contact area between the first fine gate and a single first doped portion is greater than the unit length contact area between the first fine gate and the silicon wafer at a single first gap; and / or

[0016] The contact area per unit length between the second fine gate and a single second doped portion is greater than the contact area per unit length between the second fine gate and the silicon wafer at a single second gap.

[0017] In some embodiments, a first doped region is formed within the silicon wafer at the first gap, the doping type of the first doped region being the same as the doping type of the first doped portion; and / or

[0018] At the second gap, a second doped region is formed within the silicon wafer, and the doping type of the second doped region is the same as the doping type of the second doped portion.

[0019] In some embodiments, the length of a single first doped portion in the second direction is 5µm-5000µm; and / or

[0020] The length of a single second doped portion in the second direction is 5µm-5000µm.

[0021] In some embodiments, the length of the first gap in the second direction is 10µm-2000µm; and / or

[0022] The length of the second gap in the second direction is 10um-2000um.

[0023] In some embodiments, the first doped portion is P-type doped, the second doped portion is N-type doped, the silicon wafer is an N-type silicon wafer, and the length of the first gap in the second direction is less than the length of the second gap in the second direction.

[0024] In some embodiments, the doping type of the first doped portion is opposite to the doping type of the silicon wafer, the doping type of the second doped portion is the same as the doping type of the silicon wafer, and the sum of the orthogonal projection areas of all the first doped portions on the back surface is greater than the sum of the orthogonal projection areas of all the second doped portions on the back surface.

[0025] In some embodiments, the first doped portion is P-type doped, the second doped portion is N-type doped, and the silicon wafer is an N-type silicon wafer;

[0026] In the adjacent first doped structure and second doped structure, the distribution density of the first doped portion in the first doped structure in the second direction is greater than the distribution density of the second doped portion in the second doped structure in the second direction.

[0027] In some embodiments, in the first doped structure, the distribution density of the first doped portion in the second direction is 3-60 per mm;

[0028] In the second doped structure, the distribution density of the second doped portion in the second direction is 2-50 per mm.

[0029] In some embodiments, the back side of the silicon wafer has a plurality of first interconnect regions and a plurality of second interconnect regions, the plurality of first interconnect regions and the plurality of second interconnect regions being alternately arranged along the second direction and all extending along the first direction. The first interconnect regions are used to provide a first conductive connector electrically connected to the first fine gate and insulated from the second fine gate. The second interconnect regions are used to provide a second conductive connector electrically connected to the second fine gate and insulated from the first fine gate. The number of first interconnect regions is less than the number of second gaps, and the number of second interconnect regions is less than the number of first gaps.

[0030] In some embodiments, in the first direction, the first gap corresponds to the second doped portion, the second gap corresponds to the first doped portion, the first serial region corresponds to one second gap, the second serial region corresponds to one first gap, the first fine gate is disconnected at the first gap corresponding to the second serial region, and the second fine gate is disconnected at the second gap corresponding to the first serial region.

[0031] In some embodiments, the length of the second gap corresponding to the first serial connection area in the second direction is greater than the length of the remaining second gaps in the second direction;

[0032] The length of the first gap corresponding to the second serial connection area in the second direction is greater than the length of the remaining first gaps in the second direction.

[0033] In some embodiments, a plurality of first holes penetrating the back passivation film are formed on the portion of the back passivation film corresponding to the first doped portion, and the first fine gate penetrates the first holes and makes conductive contact with the first doped portion; and / or

[0034] A plurality of second holes are formed on the portion of the back passivation film corresponding to the second doped portion, and the second fine gate is conductively contacted by penetrating the second holes.

[0035] In some embodiments, in the back-contact solar cell, the ratio of the sum of the areas of all the first apertures to the area of ​​the back surface is 0.2%-1%; and / or

[0036] In the back-contact solar cell, the sum of the areas of all the second apertures is 0.2%-0.5% of the area of ​​the back surface.

[0037] In some embodiments, in at least one of the first doped structures, a plurality of the first doped portions include at least one first test portion, the length of the first test portion in the second direction being greater than the length of the remaining first doped portions in the second direction; and / or

[0038] In at least one of the second doped structures, a plurality of the second doped portions include at least one second test portion, the length of the second test portion in the second direction being greater than the length of the remaining second doped portions in the second direction.

[0039] This application also provides a battery assembly comprising a plurality of back-contact solar cells as described in any of the preceding claims.

[0040] This application also provides a photovoltaic system, which includes the above-described battery components.

[0041] In the back-contact solar cell, cell module, and photovoltaic system of this application embodiment, the first doped structure and the second doped structure are alternately arranged in a first direction. The first doped structure includes a plurality of first doped portions spaced apart along a second direction, with a first gap between adjacent first doped portions. Simultaneously, the second doped structure includes a plurality of second doped portions spaced apart along the second direction, with a second gap between adjacent second doped portions. This reduces parasitic absorption on the back side, improves the bifaciality of the back-contact solar cell, and effectively reduces metallization recombination, thereby improving the efficiency of the back-contact solar cell.

[0042] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a photovoltaic system module provided in an embodiment of this application;

[0044] Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of the planar structure of a back-contact solar cell provided in an embodiment of this application;

[0046] Figure 4 This is a cross-sectional schematic diagram of a back-contact solar cell provided in an embodiment of this application;

[0047] Figure 5 This is another cross-sectional schematic diagram of the back-contact solar cell provided in the embodiments of this application.

[0048] Figure 6 This is another cross-sectional schematic diagram of the back-contact solar cell provided in the embodiments of this application;

[0049] Figure 7 This is another cross-sectional schematic diagram of the back-contact solar cell provided in the embodiments of this application;

[0050] Figure 8 This is another planar structure schematic diagram of the back-contact solar cell provided in the embodiments of this application;

[0051] Figure 9 This is a schematic diagram of the first and second doped structures of the back-contact solar cell provided in the embodiments of this application.

[0052] Explanation of key component symbols:

[0053] Photovoltaic system 1000, battery module 200, back contact solar cell 100, silicon wafer 10, front side 11, back side 12, first doped structure 20, first doped part 22, first gap 21, second doped structure 30, second doped part 31, second gap 32, back passivation film layer 50, first hole 51, second hole 52, first fine grid 60, second fine grid 70. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0055] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0057] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0058] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0059] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0060] Please see Figures 1-2 The photovoltaic system 1000 in this application embodiment may include the battery module 200 in this application embodiment, and the battery module 200 in this application embodiment may include a plurality of back contact solar cells 100 in this application embodiment.

[0061] In embodiments of this application, multiple back-contact solar cells 100 in the battery assembly 200 can be connected in series to form multiple battery strings. These battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between individual cells can be achieved by welding conductive connectors, or the connection between battery strings can be achieved by busbars. In some embodiments, the battery strings can form a cell array, and then be encapsulated together by a front panel, a front encapsulant film, a rear encapsulant film, and a back panel to form the battery assembly 200.

[0062] Please see Figures 3-6 The back-contact solar cell 100 in this embodiment may include a silicon wafer 10, a plurality of first doped structures 20, a plurality of second doped structures 30, a back passivation film layer 50, a first fine grid 60, and a second fine grid 70.

[0063] The silicon wafer 10 has a front side 11 and a back side 12. A first doped structure 20 and a second doped structure 30 are both stacked on the back side 12. A plurality of first doped structures 20 and second doped structures 30 are arranged alternately along a first direction, and a second direction intersects the first direction.

[0064] The first doped structure 20 may include a plurality of first doped portions 22 spaced apart along a second direction, with a first gap 21 between adjacent first doped portions 22. The second doped structure 30 includes a plurality of second doped portions 31 spaced apart, with a second gap 32 between adjacent second doped portions 31.

[0065] Specifically, such as Figure 3 As shown, the first doped structure 20 and the second doped structure 30 can be arranged alternately along the longitudinal direction of the silicon wafer 10. The first doped portions 22 in the same first doped structure 20 are all arranged at intervals along the transverse direction, and the second doped portions 31 in the same second doped structure 30 are all arranged at intervals along the transverse direction.

[0066] That is, the first direction can be the longitudinal direction of the back-contact solar cell 100, and the second direction can be the transverse direction of the back-contact solar cell 100, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon wafer 10, and there is no specific limitation here.

[0067] The back passivation film 50 can cover the entire back surface 12 and is located above the first doped structure 20, the second doped structure, and the portion not covered by the first doped structure 20 and the second doped structure 30.

[0068] Specifically, the back passivation film 50 is the outermost film layer on the back surface 12, and it covers both the first doped structure 20 and the second doped structure 30. In some embodiments, the first doped structure 20 and the second doped structure 30 may be alternately arranged, and the back passivation film 50 is also covered in the interval between them. In general, the back passivation film 50 covers the entire back surface 12.

[0069] A first fine gate 60 is disposed on the back passivation film layer 50 and above the first doped structure 20. The first fine gate 60 penetrates at least a portion of the back passivation film layer 50 corresponding to the first doped portion 22 to make conductive contact with the first doped portion 22. That is, the first fine gate 60 penetrates at least a portion of the back passivation film layer 50 above the first doped portion 22 to make conductive contact with the first doped portion 22 to achieve carrier collection. Simultaneously, the first fine gate 60 is continuous at at least a portion of the first gaps 21. That is, the first fine gate 60 may be continuous at all the first gaps 21, or the first fine gate 60 may be continuous at a portion of the first gaps 21 and discontinuous at the remaining first gaps 21.

[0070] The second fine gate 70 is disposed on the back passivation film layer 50 and located above the second doped structure 30. The second fine gate 70 penetrates at least a portion of the back passivation film layer 50 corresponding to the second doped portion 31 to make conductive contact with the second doped portion 31. That is, the second fine gate 70 penetrates at least a portion of the back passivation film layer 50 located above the second doped portion 31 to make conductive contact with the second doped portion 31 to achieve carrier collection. Simultaneously, the second fine gate 70 is continuous at at least a portion of the second gaps 32. That is, the second fine gate 70 may be continuous at all the second gaps 32, or the second fine gate 70 may be continuous at some of the second gaps 32 and discontinuous at the remaining second gaps 32.

[0071] It should be noted that in this article, when a certain membrane layer is stacked or covered on a certain surface or a certain area of ​​a certain membrane layer, it can mean that the membrane layer is directly stacked on the surface or a certain membrane layer, or that other membrane layers are disposed between the membrane layer and the surface or membrane layer. Covering is only used to define the specific setting range of the membrane layer.

[0072] In the back-contact solar cell 100, cell module 200, and photovoltaic system 1000 of this application embodiment, the first doped structure 20 and the second doped structure 30 are alternately arranged in a first direction. The first doped structure 20 includes a plurality of first doped portions 22 spaced apart along a second direction, with a first gap 21 between adjacent first doped portions 22. The second doped structure 30 includes a plurality of second doped portions 31 spaced apart along the second direction, with a second gap 32 between adjacent second doped portions 31. The first fine grid 60 is in conductive contact with the first doped portion 22, and the second fine grid 70 is in conductive contact with the second doped portion 31. In this way, by setting the doped structure on the back side 12 as a discontinuous structure, the parasitic absorption of light by the doped structure located on the back side 12 can be reduced, thereby improving the bifaciality of the back-contact solar cell 100. At the same time, there are no doped portions at the first gap 21 and the second gap 32, which can reduce the metallization contact area between the fine grid and the doped layer, effectively reducing metallization recombination and improving the efficiency of the back-contact solar cell 100.

[0073] Specifically, in the embodiments of this application, the first doped structure 20 refers to a doped structure with a specific conductivity type, which can be formed by phosphorus diffusion or boron diffusion to form a P-type or N-type semiconductor structure, used to form a carrier transport channel. The second doped structure 30 is a doped structure with the opposite conductivity type to the first doped structure 20, forming a complementary carrier collection path. The silicon wafer 10 can be an N-type silicon wafer 10 or a P-type silicon wafer 10, that is, the doping type of the silicon wafer 10 can be P-type doping or N-type doping, and there is no specific limitation here.

[0074] In some possible embodiments, the first doped portion 22 may be an emitter doped layer, and its doping type may be opposite to that of the silicon wafer 10. The second doped portion 31 may be a base region doped layer, and its doping type may be the same as that of the silicon wafer 10. For example, when the silicon wafer 10 is an N-type silicon wafer, the first doped portion 22 is a P-type doped layer and the second doped portion 31 is an N-type doped layer; when the silicon wafer 10 is a P-type silicon wafer, the first doped portion 22 is an N-type doped layer and the second doped portion 31 is a P-type doped layer.

[0075] The back passivation film 50 is an insulating dielectric layer covering the back surface 12 of the silicon wafer 10, such as silicon oxide, silicon nitride, or aluminum oxide. The first fine gate 60 and the second fine gate 70 are metal conductive electrodes, which can be formed by printing or vapor deposition using metal materials such as silver paste, copper, or aluminum. The first gap 21 and the second gap 32 refer to the absence of additional doped layers between adjacent doped regions.

[0076] Specifically, on the back surface 12 of the silicon wafer 10, first doped structures 20 and second doped structures 30 are alternately arranged along a first direction, both of which extend continuously along a second direction. Each first doped structure 20 consists of a plurality of separate first doped portions 22, with a first gap 21 between adjacent first doped portions 22.

[0077] The first fine gate 60 can form point or line contact with the first doped portion 22 through a partial opening in the region directly above the first doped portion 22. At the first gap 21 region, the first fine gate 60 may not penetrate the back passivation film layer 50. However, in some possible embodiments, a small portion of the first fine gate 60 may penetrate the back passivation film layer 50 and contact the silicon wafer 10 at a portion of the first gap 21. Therefore, since the first doped portion 22 is not present at the first gap 21, the area of ​​the metallization region can be reduced, thus reducing metallization recombination.

[0078] Similarly, the second fine gate 70 can form point or line contact with the second doped portion 31 through a local opening in the region directly above the second doped portion 31. In the region of the second gap 32, the second fine gate 70 may not penetrate the back passivation film layer 50. Of course, in some possible embodiments, in a portion of the second gap 32, a small portion of the second fine gate 70 may penetrate the back passivation film layer 50 and contact the silicon wafer 10. Therefore, since the second gap 32 does not have the second doped portion 31, the area of ​​the metallization region can be reduced, thus reducing metallization recombination.

[0079] In other words, with this layout, the first doped portions 22 in the first doped structure 20 have a first gap 21 between them, and the second doped portions 31 in the second doped structure 30 have a second gap 32. This reduces parasitic absorption of light on the back surface 12 and improves the bifaciality. Simultaneously, by appropriately arranging the first fine gate 60 and the second fine gate 70, the integrity of the passivation layer can be preserved to the maximum extent while maintaining the electrode conductivity, thus reducing recombination losses caused by metal contacts.

[0080] In some embodiments, at least a portion of the first gap 21, the first fine gate 60 does not penetrate the back passivation film layer 50.

[0081] Thus, the first fine gate 60 does not penetrate the back passivation film layer 50 at the first gap 21, or only has points penetrating the back passivation film layer 50 at a small portion of the first gap 21. This can reduce the contact area between the first fine gate 60 and the silicon wafer 10 at the first gap 21 and reduce recombination.

[0082] In the embodiments of this application, it is preferable that the first fine gate 60 does not penetrate the back passivation film layer 50 at all the first gaps 21. That is, the first fine gate 60 only penetrates the back passivation film layer 50 and makes conductive contact with the first doped portion 22 in at least a part of the area corresponding to the first doped portion 22, and keeps the back passivation film layer 50 intact and not penetrated at the first gaps 21.

[0083] Of course, it is understandable that in the actual manufacturing process, there may be a phenomenon where the first fine gate 60 penetrates the back passivation film layer 50 at some of the first gaps 21. In such cases, the first fine gate 60 only has a few points of burn-through at the first gaps 21.

[0084] In this case, within the same first fine gate 60, the contact area between the first fine gate 60 and a single first doped portion 22 is greater than the contact area between the first fine gate 60 and the silicon wafer 10 at a single first gap 21.

[0085] In other words, in the adjacent first doped portion 22 and first gap 21, the contact area between the first fine gate 60 and the first doped portion 22 is greater than the contact area between the first fine gate 60 and the silicon wafer 10 through the back passivation film layer 50 at the first gap 21.

[0086] In this way, the contact area between the first fine gate 60 and the silicon wafer 10 at the first gap 21 can be controlled to be small, thereby avoiding excessive recombination.

[0087] In some embodiments, the unit length contact area between the first fine gate 60 and a single first doped portion 22 is greater than the unit length contact area between the first fine gate 60 and the silicon wafer 10 at a single first gap 21.

[0088] It should be noted that "the contact area per unit length between the first fine gate 60 and the single first doped portion 22" refers to the ratio between the total contact area between the first fine gate 60 and the single first doped portion 22 and the length (in mm) of the single first doped portion 22 in the second direction. "The contact area per unit length between the first fine gate 60 and the silicon wafer 10 at the single first gap 21" refers to the ratio between the total contact area between the first fine gate 60 and the silicon wafer 10 at the single first gap 21 and the length (in mm) of the single first gap 21 in the second direction.

[0089] In this way, excessive recombination can be avoided due to an excessively large contact area between the first fine gate 60 and the silicon wafer 10 in the first gap 21.

[0090] In some embodiments, the second fine gate 70 does not penetrate the back passivation film layer 50 at at least a portion of the second gap 32.

[0091] Thus, the second fine gate 70 does not penetrate the back passivation film layer 50 at the second gap 32, or only has points penetrating the back passivation film layer 50 at a small portion of the second gap 32. This can reduce the contact area between the second fine gate 70 and the silicon wafer 10 at the second gap 32 and reduce recombination.

[0092] In the embodiments of this application, it is preferable that the second fine gate 70 does not penetrate the back passivation film layer 50 at all the second gaps 32. That is, the second fine gate 70 only penetrates the back passivation film layer 50 and makes conductive contact with the second doped portion 31 in at least a part of the area corresponding to the second doped portion 31, and keeps the back passivation film layer 50 intact and not penetrated at the second gaps 32.

[0093] Of course, it is understandable that in the actual manufacturing process, there may be a phenomenon where the second fine gate 70 penetrates the back passivation film layer 50 at some of the second gaps 32. In such cases, the second fine gate 70 only has a few burn-through points at the second gaps 32.

[0094] In this case, within the same second fine gate 70, the contact area between the second fine gate 70 and a single second doped portion 31 is greater than the contact area between the second fine gate 70 and the silicon wafer 10 at a single second gap 32.

[0095] That is to say, in the adjacent second doped portion 31 and second gap 32, the contact area between the second fine gate 70 and the second doped portion 31 is greater than the contact area between the second fine gate 70 and the silicon wafer 10 through the back passivation film layer 50 at the second gap 32.

[0096] In this way, the contact area between the second fine gate 70 and the silicon wafer 10 at the second gap 32 can be controlled to be small, thereby avoiding excessive recombination.

[0097] In some embodiments, the unit length contact area between the second fine gate 70 and a single second doped portion 31 is greater than the unit length contact area between the second fine gate 70 and the silicon wafer 10 at a single second gap 32.

[0098] It should be noted that "the contact area per unit length between the second fine gate 70 and the single second doped portion 31" refers to the ratio between the total contact area between the second fine gate 70 and the single second doped portion 31 and the length (in mm) of the single second doped portion 31 in the second direction. "The contact area per unit length between the second fine gate 70 and the silicon wafer 10 at the single second gap 32" refers to the ratio between the total contact area between the second fine gate 70 and the silicon wafer 10 at the single second gap 32 and the length (in mm) of the single second gap 32 in the second direction.

[0099] In this way, excessive recombination can be avoided due to an excessively large contact area between the second fine gate 70 and the silicon wafer 10 in the second gap 32.

[0100] Please see Figure 5 In some embodiments, a first doped region 13 is formed in the silicon wafer 10 at the first gap 21, and the doping type of the first doped region 13 is the same as the doping type of the first doped portion 22.

[0101] For example, when the first doped portion 22 is a P-type doped layer, the first doped region 13 can be a P-type doped region; when the first doped portion 22 is an N-type doped layer, the first doped region 13 can be an N-type doped region.

[0102] Thus, by forming a first doped region 13 at the position corresponding to the first gap 21 on the silicon wafer 10, the efficiency of the back contact solar cell 100 can be improved.

[0103] In addition, please see Figure 7 In some embodiments, a second doped region 14 is formed within the silicon wafer 10 at the second gap 32, and the doping type of the second doped region 14 is the same as the doping type of the second doped portion 31.

[0104] For example, when the second doped portion 31 is a P-type doped layer, the second doped region 14 can be a P-type doped region; when the second doped portion 31 is an N-type doped layer, the second doped region 14 can be an N-type doped region.

[0105] Thus, by forming a second doped region 14 at the position corresponding to the second gap 32 on the silicon wafer 10, the efficiency of the back contact solar cell 100 can be improved.

[0106] In some embodiments, the length of a single first doped portion 22 in the second direction is 5um-5000um; and / or, the length of a single second doped portion 31 in the second direction is 5um-5000um.

[0107] Wherein, the length of a single first doped part 22 in the second direction refers to the dimension of the first doped part 22 extending along the second direction, and the length of a single second doped part 31 in the second direction refers to the dimension of the second doped part 31 extending along the second direction. By limiting the size range of the first doped part 22 and the second doped part 31, the carrier collection efficiency and surface recombination loss can be balanced.

[0108] In this embodiment, by controlling the lengths of the first doped portion 22 and the second doped portion 31 within the range of 5µm-5000µm, sufficient carrier collection paths are ensured while avoiding excessively large passivation layer openings that would increase recombination. When the first fine gate 60 and the second fine gate 70 penetrate the passivation layer and contact the doped portion, this length range allows the fine gates to form local contact points in the corresponding regions of the doped portion, rather than continuously penetrating the entire second direction, thus reducing metallization recombination.

[0109] Specifically, in such embodiments, the length of a single first doped portion 22 can be, for example, any value between 5um, 10um, 20um, 30um, 40um, 50um, 100um, 200um, 300um, 400um, 500um, 1000um, 2000um, 3000um, 4000um, 5000um, or 5um-5000um. The length of a single second doped portion 31 can be, for example, any value between 5um, 10um, 20um, 30um, 40um, 50um, 100um, 200um, 300um, 400um, 500um, 1000um, 2000um, 3000um, 4000um, 5000um, or 5um-5000um.

[0110] In this application, in order to balance carrier collection efficiency and surface recombination loss as much as possible and ensure conversion efficiency, the length of the first doped part 22 is preferably 10um-1000um, and the length of the second doped part 31 is preferably 10um-1000um.

[0111] In some embodiments, the length of the first gap 21 in the second direction is 10um-2000um; and / or, the length of the second gap 32 in the second direction is 10um-2000um.

[0112] Thus, by limiting the length range of the first gap 21 to 10um-2000um and the length range of the second gap 32 to 10um-2000um, the area of ​​the passivation layer not covered can be reduced while ensuring effective carrier transport, thereby reducing surface recombination.

[0113] Specifically, when the length of the first gap 21 is controlled within the range of 10µm-2000µm, the back passivation film layer 50 can form a continuous coverage in the gap region, preventing the gap region between the first doped portions 22 from being too large, which would result in an excessively long carrier collection path and affect the carrier collection efficiency. Similarly, by limiting the length range of the second gap 32, the gap region between the second doped portions 31 can also be prevented from being too large, which would result in an excessively long carrier collection path and affect the carrier collection efficiency.

[0114] Specifically, in such an embodiment, the length of the first gap 21 in the second direction can be, for example, 10um, 20um, 30um, 40um, 50um, 100um, 200um, 300um, 400um, 500um, 1000um, 2000um, or any value between 10um and 2000um.

[0115] In some embodiments, the length of the first gap 21 in the second direction is preferably 50µm-200µm, and the length of the second gap 22 in the second direction is preferably 50µm-500µm. Thus, by optimizing the length of the gaps, the bifaciality can be improved while minimizing the impact on carrier collection efficiency due to excessively long carrier collection paths.

[0116] Specifically, in such an embodiment, the length of the first gap 21 can be, for example, 50 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 180 μm, or 200 μm, with 70 μm-90 μm being the most preferred. The length of the second gap 32 can be, for example, 50 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 180 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm, with 110 μm-120 μm being the most preferred.

[0117] In some embodiments, the first doping portion 22 is P-type doped, the second doping portion 31 is N-type doped, the silicon wafer 10 is an N-type silicon wafer, and the length of the first gap 21 in the second direction is less than the length of the second gap 32 in the second direction.

[0118] Thus, when silicon wafer 10 is an N-type silicon wafer, the first doped portion 22 is a P-type doped layer, and the second doped portion 31 is an N-type doped layer, the first doped portion 22 is an emitter doped layer. The P-type doped layer has a poor ability to collect carriers. By making the length of the first gap 21 smaller than the length of the second gap 32, the carrier collection path of the first doped portion 22 can be shortened, thereby improving the carrier collection efficiency of the first doped portion 22 and avoiding excessive carrier loss due to the excessive length of the first gap 21.

[0119] In some embodiments, the doping type of the first doped portion 22 is opposite to that of the silicon wafer 10, and the doping type of the second doped portion 31 is the same as that of the silicon wafer 10. The sum of the projected areas of all the first doped portions 22 on the back surface 11 is greater than the sum of the projected areas of all the second doped portions 31 on the back surface 11. That is, the first doped portions 22 serve as the emitter doped layer, the second doped portions 31 serve as the base region doped layer, and the total area of ​​the emitter doped layer is greater than the total area of ​​the base region doped layer.

[0120] Thus, the emitter doped layer has a larger area, which can improve the efficiency of the back contact solar cell 100.

[0121] Specifically, in such an embodiment, when the silicon wafer 10 is an N-type silicon wafer, the first doped portion 22 is a P-type doped layer and the second doped portion 31 is an N-type doped layer; when the silicon wafer 10 is a P-type silicon wafer, the first doped portion 22 is an N-type doped layer and the second doped portion 31 is a P-type doped layer.

[0122] In some embodiments, the doping type of the first doping portion 22 is P-type doping, the doping type of the second doping portion 31 is N-type doping, and the silicon wafer 10 is an N-type silicon wafer.

[0123] In the adjacent first doped structure 20 and second doped structure 30, the distribution density of the first doped portion 22 in the first doped structure 20 in the second direction is greater than the distribution density of the second doped portion 31 in the second doped structure 30 in the second direction.

[0124] It should be noted that "distribution density in the second direction" refers to the number of second doped portions 31 per unit length (in mm) in the second direction. That is to say, within the same length range, the number of first doped portions 22 is greater than the number of second doped portions 31.

[0125] Thus, by setting the arrangement density of the first doped part 22 of the P-type doping type to be relatively dense, the carrier collection efficiency of the first doped part 22 can be improved.

[0126] Specifically, the carrier collection capability of the first doped part 22 of the P-type doping type is relatively poor. If the first doped part 22 is arranged too dispersedly, the carrier collection efficiency will be even worse. Therefore, by setting it in this way, the carrier collection efficiency of the first doped part 22 can be improved.

[0127] Furthermore, in such an embodiment, in the first doped structure 20, the distribution density of the first doped portion 22 in the second direction is 3-60 portions / mm;

[0128] In the second doped structure 30, the distribution density of the second doped portion 31 in the second direction is 2-50 portions / mm.

[0129] Thus, by controlling the distribution density of the first doped portion 22 and the second doped portion 31 within the aforementioned ranges, the collection efficiency of holes and electrons can be guaranteed, avoiding excessively low collection efficiencies that would affect overall efficiency. In other words, this configuration balances the relationship between bifaciality and carrier collection efficiency, ensuring the efficiency of the back-contact solar cell 100 while improving bifaciality.

[0130] Please see Figure 8 In some embodiments, the back surface 12 of the silicon wafer 10 has a plurality of first serial connection areas 101 and a plurality of second serial connection areas 102, the plurality of first serial connection areas 101 and the plurality of second serial connection areas 102 being alternately arranged along a second direction and all extending along a first direction.

[0131] The first series connection area 101 is used to provide a first conductive connector 80 that is electrically connected to the first fine grid 60 and insulated from the second fine grid 70. The second series connection area 102 is used to provide a second conductive connector 90 that is electrically connected to the second fine grid 70 and insulated from the first fine grid 60. The number of first series connection areas 101 is less than the number of second gaps 32, and the number of second series connection areas 102 is less than the number of first gaps 21.

[0132] Thus, the series connection between the back-contact solar cells 100 can be achieved through the first conductive connector 80 and the second conductive connector 90.

[0133] Specifically, the first series connection area 101 refers to a specific area on the back side 12 of the silicon wafer 10 used to set the first conductive connector 80 (e.g., main gate and / or solder ribbon). By setting the first conductive connector 80 at the first series connection area 101, conductive contact with the first fine gate 60 is achieved. The second series connection area 102 refers to a specific area on the back side 12 of the silicon wafer 10 used to set the second conductive connector 90 (e.g., solder ribbon). By setting the second conductive connector 90 at the second series connection area 102, conductive contact with the second fine gate 70 is achieved, thereby realizing the overall current conduction. The number of first series connection areas 101 is less than the number of second gaps 32, and the number of second series connection areas 102 is less than the number of first gaps 21, which can avoid the increased risk of leakage caused by the excessively dense arrangement of the first conductive connector 80 and the second conductive connector. When the back contact solar cell 100 is a gridless back contact solar cell, both the first conductive connector 80 and the second conductive connector 90 can be solder ribbons. When the back contact solar cell 100 is a grid-connected back contact solar cell, the first conductive connector 80 and the second conductive connector 90 are the grid and the solder ribbon, respectively.

[0134] In some possible embodiments, in order to achieve insulation between the first conductive connector 80 and the second fine gate 70, insulating adhesive can be provided at the position where the second fine gate 70 overlaps with the first series connection area 101. In order to achieve insulation between the second conductive connector 90 and the first fine gate 60, insulating adhesive can be provided at the position where the first fine gate 60 overlaps with the second series connection area 102.

[0135] Of course, in some embodiments, in order to achieve insulation between the first conductive connector 80 and the second fine gate 70 and insulation between the second conductive connector 90 and the first fine gate 60, the second fine gate 70 can be set to be disconnected at the first serial connection area 101 and the first fine gate 60 can be set to be disconnected at the second serial connection area 102.

[0136] In such a case, please refer to Figure 8 In some embodiments, in the first direction, the first gap 21 may correspond to the second doped portion 31, and the second gap 32 may correspond to the first doped portion 22.

[0137] The first serial connection area 101 corresponds to a second gap 32. That is, each first serial connection area 101 corresponds to a second gap 32, and the positions corresponding to some of the second gaps 32 are the first serial connection areas 101.

[0138] The second serial connection area 102 corresponds to a first gap 21. That is, each second serial connection area 102 corresponds to a first gap 21, and the positions corresponding to some of the first gaps 21 are the second serial connection areas 102.

[0139] The first fine gate 60 is disconnected at the first gap 21 corresponding to the second serial connection area 102, and the second fine gate 70 is disconnected at the second gap 32 corresponding to the first serial connection area 101. That is, the first fine gate 60 is disconnected at part of the first gap 21, and the second fine gate 70 is disconnected at part of the second gap 32.

[0140] Specifically, the first fine gate 60 being disconnected means that the continuity of the first fine gate 60 is interrupted at the first gap 21 corresponding to the second series connection area 102, so as to prevent the first fine gate 60 from contacting the second conductive connector 90 in the second series connection area 102. The second fine gate 70 being disconnected means that the continuity of the second fine gate 70 is interrupted at the second gap 32 corresponding to the first series connection area 101, so as to prevent the second fine gate 70 from contacting the first conductive connector 80 in the first series connection area 101.

[0141] In this way, a portion of the first gap 21 can be used as the second series connection area 102, and a portion of the second gap 32 can be used as the first series connection area 101. It is only necessary to set the first fine gate 60 to be discontinuous in the portion of the first gap 21 and the second fine gate 70 to be discontinuous in the portion of the second gap 32 to achieve insulation between the fine gate and conductive connectors of different polarities.

[0142] Furthermore, in such an embodiment, the length of the second gap 32 corresponding to the first serial connection area 101 in the second direction may be greater than the length of the other second gaps 32 in the second direction;

[0143] The length of the first gap 21 corresponding to the second serial connection area 102 in the second direction may be greater than the length of the other first gaps 21 in the second direction.

[0144] Thus, a wider gap for setting the conductive connectors allows for the accommodation of wider main gates and / or solder strips without the need for extremely fine main gates and / or solder strips, reducing the difficulty of the manufacturing process.

[0145] Please see Figure 3 , Figure 4 as well as Figure 6 In some embodiments, a plurality of first holes 51 penetrating the back passivation film 50 are formed on the portion of the back passivation film 50 corresponding to the first doped portion 22, and the first fine gate 60 makes conductive contact with the first doped portion 22 through the first holes 51; and / or

[0146] A plurality of second holes 52 are formed on the portion of the back passivation film 50 corresponding to the second doped portion 31, and the second fine gate 70 is electrically connected to the second doped portion 31 through the second holes 52.

[0147] Thus, by creating openings in the back passivation film 50, point contacts can be made between the fine gate and the doped portion, reducing the contact area of ​​metallization and reducing recombination.

[0148] Specifically, the first aperture 51 and the second aperture 52 refer to the local opening areas formed on the passivation layer by etching or laser aperture technology. Specifically, selective laser ablation or chemical etching processes can be used. The apertures formed on the passivation layer are only located in a part of the area covering the doped part, so that the fine gate forms point contact with the doped part through the aperture, thereby reducing the metallization contact area.

[0149] In some embodiments, in the back-contact solar cell 100, the sum of the areas of all the first apertures 51 is less than 0.2%-1% of the area of ​​the back surface 12.

[0150] Thus, by setting the area ratio of the first opening 51 within this reasonable range, it is possible to avoid the area ratio of the first opening 51 being too small, which would result in the area of ​​the metallization contact region on the first doped part 22 being too small and thus affecting the collection effect. It is also possible to avoid the area ratio of the first opening 51 being too large, which would result in excessive damage during the opening process and thus a significant decrease in efficiency.

[0151] Specifically, in such an embodiment, the area percentage of the first opening 51 can be, for example, any value between 0.2%, 0.25%, 0.3%, 0.35%, 0.4%, 0.45%, 0.5%, 0.55%, 0.6%, 0.65%, 0.7%, 0.75%, 0.8%, 0.85%, 0.9%, 0.95%, 1%, 1.25%, 1.5%, 1.75%, 2%, or 0.2%-2%.

[0152] In some embodiments, in the back-contact solar cell 100, the sum of the areas of all the second apertures 52 is less than 0.2%-0.5% of the area of ​​the back surface 12.

[0153] Thus, by setting the area ratio of the second opening 52 within this reasonable range, it is possible to avoid the area of ​​the metallization contact region on the emitter doped layer 30 being too small due to the area ratio of the second opening 52 being too small, which would affect the collection effect. It is also possible to avoid the damage during the opening process being too large due to the area ratio of the second opening 52 being too large, which would lead to a significant decrease in efficiency.

[0154] Specifically, in such an embodiment, the area percentage of the second opening 52 can be, for example, any value between 0.2%, 0.25%, 0.3%, 0.35%, 0.4%, 0.45%, 0.5%, or 0.2%-0.5%.

[0155] Specifically, the area ratio refers to the numerical relationship between the total open area of ​​the holes and the total area of ​​the back side 12 of the battery. This can be achieved by adjusting the size of a single hole or the number of holes per unit area. This ratio directly affects the contact area between the metal electrode and the doped layer.

[0156] Both the first hole 51 and the second hole 52 can be circular or rectangular openings. There are no specific restrictions on the shape of the openings. The distribution density of the holes in the second direction can be adjusted according to the length of the doped part.

[0157] Please see Figure 9 In some embodiments, in at least one first doped structure 20, a plurality of first doped portions 22 include at least one first test portion 221, the length of the first test portion 221 in the second direction being greater than the length of the remaining first doped portions 22 in the second direction; and / or

[0158] In at least one second doped structure 30, a plurality of second doped portions 31 include at least one second test portion 311, the length of the second test portion 311 in the second direction being greater than the length of the remaining second doped portions 311 in the second direction.

[0159] Specifically, the first test section 221 and the second test section 331 can serve as probe contact points for a testing device, such as an IV testing device or an EL testing device. Thus, the first test section 221 and the second test section 331 are designed to be relatively long, allowing the test probe to completely abut against them during testing. This prevents the test probe from being unable to stably abut against the fine gate, and also avoids the need for the test probe to abut against different doped regions, which could prevent equal-point contact.

[0160] In the description of this specification, the use of terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., refers to specific features, structures, materials, or characteristics described in connection with the embodiments or examples, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0161] Furthermore, the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back contact solar cell, characterized by, include: Silicon wafers; A plurality of first doped structures and a plurality of second doped structures are stacked on the back side of the silicon wafer. The first doped structures and the second doped structures are arranged alternately along a first direction and all extend along a second direction, which intersects the first direction. Each first doped structure includes a plurality of first doped portions spaced apart along the second direction, with a first gap between adjacent first doped portions. Each second doped structure includes a plurality of second doped portions spaced apart along the second direction, with a second gap between adjacent second doped portions. A back passivation film layer, the back passivation film layer covering the back side; A plurality of first fine gates are disposed on the back passivation film layer, the first fine gates are located on the first doped structure, the first fine gates penetrate at least a portion of the back passivation film layer corresponding to the first doped portion to make conductive contact with the first doped portion, and the first fine gates are continuous at at least a portion of the first gap. and A plurality of second fine gates are disposed on the back passivation film layer, the second fine gates are located on the second doped structure, the second fine gates penetrate at least a portion of the back passivation film layer corresponding to the second doped portion to make conductive contact with the second doped portion, and the first fine gates are continuous at at least a portion of the second gap.

2. The back contact solar cell of claim 1, wherein, At least a portion of the first gap, the first fine gate does not penetrate the back passivation film layer; and / or At least in part of the second gap, the second fine gate does not penetrate the back passivation film layer.

3. The back contact solar cell of claim 1, wherein, In the same first fine gate, the contact area between the first fine gate and a single first doped portion is greater than the contact area between the first fine gate and the silicon wafer at a single first gap; and / or In the same second fine gate, the contact area between the second fine gate and a single second doped portion is greater than the contact area between the second fine gate and the silicon wafer at a single second gap.

4. The back contact solar cell of claim 1, wherein, The contact area per unit length between the first fine gate and a single first doped portion is greater than the contact area per unit length between the first fine gate and the silicon wafer at a single first gap; and / or The contact area per unit length between the second fine gate and a single second doped portion is greater than the contact area per unit length between the second fine gate and the silicon wafer at a single second gap.

5. The back contact solar cell of claim 1, wherein, At the first gap, a first doped region is formed within the silicon wafer, and the doping type of the first doped region is the same as the doping type of the first doped portion; and / or At the second gap, a second doped region is formed within the silicon wafer, and the doping type of the second doped region is the same as the doping type of the second doped portion.

6. The back-contact solar cell according to claim 1, characterized in that, The length of a single first doped portion in the second direction is 5µm-5000µm; and / or The length of a single second doped portion in the second direction is 5µm-5000µm.

7. The back contact solar cell of claim 1 wherein, The length of the first gap in the second direction is 10µm-2000µm; and / or The length of the second gap in the second direction is 10um-2000um.

8. The back contact solar cell of claim 1, wherein, The first doped portion is P-type doped, the second doped portion is N-type doped, the silicon wafer is an N-type silicon wafer, and the length of the first gap in the second direction is less than the length of the second gap in the second direction.

9. The back contact solar cell of claim 1 wherein, The doping type of the first doped portion is opposite to that of the silicon wafer, and the doping type of the second doped portion is the same as that of the silicon wafer. The sum of the projected areas of all the first doped portions on the back surface is greater than the sum of the projected areas of all the second doped portions on the back surface.

10. The back contact solar cell of claim 1 wherein, The first doped portion is P-type doped, the second doped portion is N-type doped, and the silicon wafer is an N-type silicon wafer; In the adjacent first doped structure and second doped structure, the distribution density of the first doped portion in the first doped structure in the second direction is greater than the distribution density of the second doped portion in the second doped structure in the second direction.

11. The back contact solar cell of claim 10, wherein, In the first doped structure, the distribution density of the first doped portion in the second direction is 3-60 per mm; In the second doped structure, the distribution density of the second doped portion in the second direction is 2-50 per mm.

12. The back contact solar cell of claim 1 wherein, The back side of the silicon wafer has a plurality of first serial connection areas and a plurality of second serial connection areas. The plurality of first serial connection areas and the plurality of second serial connection areas are alternately arranged along the second direction and all extend along the first direction. The first serial connection areas are used to provide a first conductive connector that is electrically connected to the first fine gate and insulated from the second fine gate. The second serial connection areas are used to provide a second conductive connector that is electrically connected to the second fine gate and insulated from the first fine gate. The number of first serial connection areas is less than the number of second gaps, and the number of second serial connection areas is less than the number of first gaps.

13. The back contact solar cell of claim 12, wherein, In the first direction, the first gap corresponds to the second doped portion, the second gap corresponds to the first doped portion, the first serial connection region corresponds to one second gap, the second serial connection region corresponds to one first gap, the first fine gate is broken at the first gap corresponding to the second serial connection region, and the second fine gate is broken at the second gap corresponding to the first serial connection region.

14. The back contact solar cell of claim 13, wherein, The length of the second gap corresponding to the first serial connection area in the second direction is greater than the length of the other second gaps in the second direction; The length of the first gap corresponding to the second serial connection area in the second direction is greater than the length of the remaining first gaps in the second direction.

15. The back contact solar cell of claim 1 wherein, A plurality of first holes are formed on the portion of the back passivation film layer corresponding to the first doped portion, and the first fine gate is conductively contacted by the first holes through the first doped portion. and / or A plurality of second holes are formed on the portion of the back passivation film corresponding to the second doped portion, and the second fine gate is conductively contacted by penetrating the second holes.

16. The back contact solar cell of claim 15, wherein, In the back-contact solar cell, the ratio of the sum of the areas of all the first apertures to the area of ​​the back surface is 0.2%-1%; and / or In the back-contact solar cell, the sum of the areas of all the second apertures is 0.2%-0.5% of the area of ​​the back surface.

17. The back contact solar cell of claim 1 wherein, In at least one of the first doped structures, a plurality of the first doped portions include at least one first test portion, wherein the length of the first test portion in the second direction is greater than the length of the remaining first doped portions in the second direction; and / or In at least one of the second doped structures, a plurality of the second doped portions include at least one second test portion, the length of the second test portion in the second direction being greater than the length of the remaining second doped portions in the second direction.

18. A battery assembly characterized by, Includes the back-contact solar cell as described in any one of claims 1-17.

19. A photovoltaic system characterized by, Includes the battery assembly as described in claim 18.

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