A silicon substrate, photovoltaic cell and photovoltaic module

Abstract

This utility model discloses a silicon substrate, a photovoltaic cell, and a photovoltaic module, relating to the field of photovoltaic technology. The silicon substrate includes a first surface and a second surface opposite to each other, and a side surface located between the first surface and the second surface. The side surface includes a chamfered surface obtained by laser cutting. A molten silicon region and a smooth region are formed on the chamfered surface, and the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is greater than or equal to 10%. In the silicon substrate provided by this utility model, by controlling the area of ​​the smooth region, the passivation effect of the chamfered surface of the subsequent solar cell can be guaranteed, effectively improving the photoelectric conversion efficiency and module power.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic technology, and in particular to a silicon substrate, a photovoltaic cell, and a photovoltaic module. Background Technology

[0002] A solar cell is a device that utilizes solar energy, directly converting light energy into electrical energy through the photoelectric effect or photochemical effect. Solar cells include slab solar cells. Currently, the production of slab solar cells typically involves cutting a solar cell that has already formed multiple film layers into at least two slabs, such as two half-cells. These slab solar cells are then used to manufacture photovoltaic modules.

[0003] However, after cutting, the cut surfaces of sectional solar cells often have laser-damaged areas. For example, when a laser partially melts the silicon substrate of a solar cell to create guide grooves for the slicing, the molten silicon recrystallizes and partially oxidizes as the temperature decreases, producing silicon slag and silicon oxide that adhere to the surface of the cut surface. These conditions affect the passivation and other properties of the sectional solar cells, thus impacting their photoelectric conversion efficiency. Utility Model Content

[0004] The purpose of this invention is to provide a silicon substrate, a photovoltaic cell, and a photovoltaic module, which improves the photoelectric conversion efficiency of the photovoltaic cell by controlling the relative area of ​​the smooth region.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a silicon substrate. The silicon substrate includes a first surface and a second surface opposite to each other, and a side surface located between the first surface and the second surface; the side surface includes a chamfered surface obtained by laser cutting; a molten silicon region and a smooth region are formed on the chamfered surface, and the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is greater than or equal to 10%.

[0006] In the silicon substrate provided by this invention, by controlling the area of ​​the smooth region, the passivation effect of the chamfered surface of the subsequent solar cells can be guaranteed, effectively improving the photoelectric conversion efficiency and module power.

[0007] Secondly, this invention also provides a photovoltaic cell. The photovoltaic cell includes a passivation layer and the silicon substrate described in the first aspect, wherein the passivation layer is formed at least on a chamfered surface.

[0008] The photovoltaic cell provided by this utility model is obtained by laser cutting and slicing, which has good passivation effect and high photoelectric conversion efficiency.

[0009] Thirdly, this utility model also provides a photovoltaic module. The photovoltaic module includes: a plurality of photovoltaic cells as described in the second aspect, an encapsulation layer covering the surface of the plurality of photovoltaic cells, and a cover plate covering the surface of the encapsulation layer away from the photovoltaic cells.

[0010] The photovoltaic module provided by this utility model is manufactured using solar cells obtained by laser slicing, and has high module power. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the present invention and constitute a part of this invention, illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the present invention and do not constitute an undue limitation thereof. In the drawings:

[0012] Figure 1 This is a schematic diagram of the silicon substrate structure in an embodiment of the present invention;

[0013] Figure 2 SEM image of the chamfered surface of the silicon substrate in this embodiment of the invention. Figure 1 ;

[0014] Figure 3 As an embodiment of this utility model Figure 2 Corresponding diagram;

[0015] Figure 4 SEM image of the chamfered surface of the silicon substrate in this embodiment of the invention. Figure 2 ;

[0016] Figure 5 As an embodiment of this utility model Figure 4 Corresponding diagram;

[0017] Figure 6 This is a side view of the silicon substrate in an embodiment of the present invention;

[0018] Figure 7 This is a SEM image of the chamfered surface of the photovoltaic cell in this embodiment of the present invention;

[0019] Figure 8 As an embodiment of this utility model Figure 7 The corresponding diagram.

[0020] Figure label:

[0021] 1-Silicon substrate, 10-First surface, 11-Second surface, 12-Side surface, 120-Chamfered surface, 121-First side surface, 16-Molten silicon region, 17-Ablation region, 19-Smooth region; 20-Etching region 1, 21-Etching region 2, 22-Etching region 3, 23-First etching line; 24-Second etching line. Detailed Implementation

[0022] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0023] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0025] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0026] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0027] To address the aforementioned technical problems, firstly, this invention provides a silicon substrate. (See also...) Figures 1 to 6 The silicon substrate 1 includes a first surface 10 and a second surface 11 opposite to each other, and a side surface located between the first surface 10 and the second surface 11; the side surface includes a chamfered surface 120 obtained by laser cutting.

[0028] In terms of conductivity type, the silicon substrate can be an intrinsically conductive substrate, an N-type conductive substrate, or a P-type conductive substrate. In terms of the photovoltaic cell manufacturing process, in the first aspect of this invention, the silicon substrate is the raw material for the photovoltaic cell, i.e., a bare silicon wafer, which is the original silicon wafer after being squared, cut, cleaned, and inspected from a Czochralski-grown single-crystal silicon rod.

[0029] When a whole silicon substrate is divided into multiple wafer silicon substrates (i.e., the silicon substrates described in this invention), the side surface of the wafer silicon substrate is divided into a "second side surface" that is not cut during the dicing process, and a "beveled surface" and a "first side surface between the beveled surfaces" formed after dicing. It should be noted that "side surface" here is a general concept, referring to all the side surfaces of the silicon substrate or wafer silicon substrate. Figure 1 It is only used to show the relative positional relationship between the chamfered surface 120, the first side surface 121, the first surface 10, and the second surface 11.

[0030] A molten silicon region 16 and a smooth region 19 are formed on the chamfered surface 120. The ratio of the total area of ​​the smooth region 19 to the total area of ​​the chamfered surface 120 is greater than or equal to 10%. For example, the ratio of the total area of ​​the smooth region 19 to the total area of ​​the chamfered surface 120 can be 10%, 10.1%, 10.2%, 10.3%, 10.4%, 10.5%, 10.6%, 10.7%, 10.8%, 10.9%, or 11%, etc.

[0031] In the silicon substrate provided by this invention, by controlling the area of ​​the smooth region, the passivation effect of the chamfered surface of the subsequent solar cells can be guaranteed, effectively improving the photoelectric conversion efficiency and module power.

[0032] As one possible implementation, see Figures 1 to 6 A molten silicon region 16 and a smooth region 19 are formed on the chamfered surface 120. The molten silicon region 16 protrudes from the surface of the chamfered surface 120, while the smooth region 19 has a relatively flat surface and is part of the chamfered surface.

[0033] As one possible implementation, the smooth region 19 is located between the molten silicon region 16 and the second surface, with one end of the smooth region 19 at least partially overlapping the second surface 11.

[0034] The area of ​​the smooth zone can be adjusted by controlling the parameters of laser cutting, such as controlling the laser power and the number of cuts.

[0035] During the laser processing of silicon substrate 1, the silicon substrate 1 absorbs laser energy, melts, and oxidizes to form silicon slag and silicon oxide. The portion of the silicon slag and silicon oxide retained after processing forms the molten silicon zone 16 in this invention. In this embodiment, the molten silicon zone 16 is located within the chamfered surface 120 and is formed from silicon slag and silicon oxide.

[0036] like Figures 2 to 6 As shown, in terms of shape, the molten silicon region 16 refers to a region of silicon material with a circular, cuboid, or irregular shape that is attached to the chamfered surface of the silicon substrate. Because it is attached to the silicon substrate, the surface of the molten silicon region protrudes more than the other surfaces of the chamfered surface. In terms of material, the molten silicon region 16 includes silicon and silicon oxides.

[0037] In one alternative embodiment, the ratio of the total area of ​​the molten silicon region to the total area of ​​the chamfered surface is greater than 0% and less than or equal to 40%. For example, the ratio may be 0.1%, 1%, 5%, 8%, 10%, 12%, 15%, 20%, 22%, 25%, 30%, 32%, 35%, 38%, or 40%, etc.

[0038] The area of ​​the molten silicon zone can be adjusted by controlling the parameters of laser cutting, such as by controlling the laser power and frequency.

[0039] The ratio of the total area of ​​the molten silicon region to the total area of ​​the chamfered surface is within the above range. Therefore, the molten silicon region will be washed away in the subsequent cell fabrication and will not affect the subsequent passivation layer fabrication.

[0040] In one alternative embodiment, the length of the orthographic projection of the aforementioned molten silicon region on the second surface is less than or equal to 10 μm. For example, it can be 0.1 μm, 1 μm, 1.3 μm, 1.5 μm, 2 μm, 2.3 μm, 2.5 μm, 3 μm, 3.5 μm, 3.8 μm, 4 μm, 4.5 μm, 4.8 μm, 5 μm, 5.3 μm, 5.5 μm, 6 μm, 6.3 μm, 6.5 μm, 7 μm, 7.3 μm, 7.5 μm, 8 μm, 8.3 μm, 8.5 μm, 9 μm, 9.3 μm, 9.5 μm, or 10 μm, etc. It is worth noting that, since the molten silicon region is formed by silicon and silicon oxide adhering to the chamfered surface of the silicon substrate, its surface is more convex than other surfaces. The height of this convexity, which is the length of the orthographic projection of the molten silicon region onto the second surface, can be understood as the thickness of the silicon and silicon oxide. The orthographic projection of the molten silicon region onto the second surface is controlled to be less than or equal to 10 μm. Therefore, during the subsequent fabrication of photovoltaic cells, this region is easier to clean and flatten to form a relatively flat plane.

[0041] In one alternative approach, see Figures 2 to 6 The molten silicon zones 16 are distributed in clusters. For example... Figure 2As shown, the molten silicon region 16 contains multiple silicon atoms and silicon oxides, which form a cluster-like pattern. For example, the cluster-like molten silicon region 16 is formed by the repeated application of a single laser beam to the silicon substrate during high-precision dicing, creating laser pillars. At this point, the resulting chamfered surface is smooth, with only the molten silicon region adhering to it. This molten silicon region, after undergoing the cleaning process in the battery manufacturing process, will not affect the subsequent passivation of the battery.

[0042] In one alternative approach, see Figure 4 and Figure 5 The molten silicon regions 16 are distributed in a cluster, and their ends are formed with multiple boundaries. For example, the ends of the molten silicon regions 16 are at least one of a wavy boundary formed by multiple curves and / or a sawtooth boundary formed by multiple line segments.

[0043] It is worth noting that the crest height of the aforementioned wavy boundary refers to the vertical distance between a crest and its adjacent trough along the direction from the first surface to the second surface. Since crests and troughs are irregularly shaped, the shapes of two adjacent troughs may differ; therefore, the crest height here refers to the maximum crest height formed by the crest and two troughs. Similarly, the tooth height of a sawtooth boundary refers to the maximum tooth height formed by the same tooth crest and two adjacent tooth troughs. The wavelength of the aforementioned wavy boundary refers to the distance between two adjacent crests or troughs, the direction of which is perpendicular to the direction from the first surface to the second surface. The tooth pitch of a sawtooth boundary refers to the distance between two adjacent tooth crests, the direction of which is perpendicular to the direction from the first surface to the second surface.

[0044] Understandable, Figure 5 The jagged boundary formed by multiple line segments shown in the image is similar to the wavy boundary formed by multiple curves, except that one is composed of line segments and the other of curves. Therefore, the peak height of the wavy boundary in this invention can be referenced. Figure 5 The tooth height L3 of the sawtooth boundary; the wavelength of the wavy boundary can be referenced. Figure 5 The tooth pitch L4 of the sawtooth boundary; the height difference between any two adjacent peaks can be referenced. Figure 5 The height difference H between any two adjacent tooth peaks; the included angle formed by the curves on both sides of any peak can be referenced. Figure 5 The angle E formed by the included angle of the sawtooth pattern; the vertical distance between the end of the molten silicon region closest to the first surface and the wave crest can be referenced. Figure 5 The vertical distance L5 between the end of the medium-melting silicon zone closest to the first surface and the tooth peak.

[0045] In one alternative approach, see Figure 4 and Figure 5Along the direction from the first surface to the second surface, the peak height of the wavy boundary is greater than or equal to 30 μm and less than or equal to 40 μm; or, the tooth height L3 of the sawtooth boundary is greater than or equal to 30 μm and less than or equal to 40 μm; for example, it can be 30 μm, 31 μm, 32 μm, 35 μm, 36 μm, 37 μm, 38 μm, 39 μm or 40 μm, etc.

[0046] In one alternative approach, see Figure 4 and Figure 5 Along the direction from the first surface to the second surface, the wavelength of the wavy boundary is greater than or equal to 10 μm and less than or equal to 20 μm; or, the tooth pitch L4 of the sawtooth boundary is greater than or equal to 10 μm and less than or equal to 20 μm; for example, it can be 10 μm, 11 μm, 12 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc.

[0047] In one alternative approach, see Figure 4 and Figure 5 The height difference between any two adjacent peaks is greater than or equal to 5 μm and less than or equal to 15 μm; or the height difference H between any two adjacent peaks is greater than or equal to 5 μm and less than or equal to 15 μm; for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 13 μm or 15 μm, etc.

[0048] In one alternative approach, see Figure 4 and Figure 5 The angle formed by the curves on both sides of any wave crest is greater than or equal to 5° and less than or equal to 10°; or the angle E formed by any sawtooth is greater than or equal to 5° and less than or equal to 10°; for example, it can be 5°, 5.5°, 6°, 6.5°, 7°, 7.5°, 8°, 8.5°, 9°, 9.5° or 10°, etc.

[0049] In one alternative approach, see Figure 4 and Figure 5 The vertical distance between the end of the molten silicon region closest to the first surface and the wave crest is greater than or equal to 70 μm and less than or equal to 100 μm; or, the vertical distance L5 between the end of the molten silicon region closest to the first surface and the tooth crest is greater than or equal to 70 μm and less than or equal to 100 μm; for example, it can be 70 μm, 72 μm, 73 μm, 75 μm, 78 μm, 80 μm, 82 μm, 83 μm, 84 μm, 85 μm, 86 μm, 87 μm, 88 μm, 89 μm, 90 μm, 92 μm, 95 μm or 100 μm, etc.

[0050] When the relevant parameters of the wavy and / or sawtooth boundaries of the molten silicon zone are within the above range, it is beneficial to clean the molten silicon zone thoroughly and will not affect the passivation of the battery later.

[0051] As one possible implementation, see Figures 1 to 6 An ablation region 17 is also formed on the chamfered surface 120. The ablation region 17 starts from the first surface 10 and is located between the edge of the chamfered surface 120 and the molten silicon region 16. At least part of the ablation region 17 is recessed from the chamfered surface toward the interior of the silicon substrate.

[0052] In some embodiments, the chamfered surface 120 includes an ablation region near the laser incident surface. The morphology of the ablation region is the morphology left by the ablation of large particles along the crystal lattice orientation during laser ablation.

[0053] In some embodiments, the morphology left by the ablation of large particles with the crystal orientation during laser ablation can be understood as: a groove-shaped structure of depression left on the surface of the silicon substrate due to the melting of part of the silicon on the surface of the silicon substrate.

[0054] In one alternative approach, the ratio of the total area of ​​the ablation zone to the total area of ​​the chamfered surface is less than or equal to 50%. For example, the ratio may be 0.1%, 1%, 5%, 8%, 10%, 12%, 15%, 20%, 22%, 25%, 30%, 32%, 35%, 38%, 40%, 45%, 48%, or 50%, etc.

[0055] The area of ​​the ablation zone can be adjusted by controlling the parameters of the laser cutting, such as by controlling the laser power.

[0056] When the ratio of the total area of ​​the ablation zone to the total area of ​​the chamfered surface is within the above range, it is easier to clean and flatten the ablation zone within the above range to form a relatively flat plane when cleaning the silicon substrate during the later fabrication of photovoltaic cells. This facilitates the formation of a passivation layer at this location and improves the passivation effect.

[0057] In some embodiments, see Figure 3 Along the direction from the first surface to the second surface, the length D of the ablation region 17 is less than or equal to 50 μm. For example, the length D of the ablation region 17 can be 0.1 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 48 μm, or 50 μm, etc. It should be noted that the length of the ablation region 17 varies with the thickness of the silicon substrate 1. Therefore, during the subsequent fabrication of photovoltaic cells, this region is more easily cleaned and flattened to form a relatively flat plane.

[0058] See Figure 6The length L2 of the orthographic projection of the ablation region 17 onto the second surface 11 is less than or equal to 3 μm. For example, the length L2 of the orthographic projection of the ablation region 17 onto the second surface 11 can be 0.1 μm, 0.5 μm, 1 μm, 1.3 μm, 1.5 μm, 2 μm, 2.3 μm, 2.5 μm, or 3 μm, etc. It should be noted that the length of the orthographic projection of the ablation region onto the second surface refers to the length of the orthographic projection of two opposite points in the ablation region onto the second surface 11 along the length direction D of the ablation region 17. For the same ablation region, depending on the specific ablation region, there may be multiple "lengths of the orthographic projection of the ablation region onto the second surface." That is, the lengths of these orthographic projections are all greater than 0 μm and less than or equal to 3 μm. Therefore, during the subsequent fabrication process of photovoltaic cells, this area is more easily cleaned and flattened to form a relatively flat plane.

[0059] When the area of ​​the molten silicon region on the chamfered surface is fixed, and the length of the ablation region and the length of its orthographic projection on the second surface meet the aforementioned ranges, it not only increases the area of ​​the unformed molten silicon region and the ablation region on the chamfered surface, but also improves the film quality of the passivation layer after it is formed in this area, thereby enhancing the passivation effect. Simultaneously, it has minimal impact on the surface of the photovoltaic cell process. Furthermore, controlling the length of the ablation region and the length of its orthographic projection on the second surface makes the chamfered surface smooth. This not only improves the film quality of the passivation layer, resulting in a better subsequent passivation effect, but also allows for better control of transported microcracks, improving the yield of the silicon substrate.

[0060] In one alternative approach, see Figures 2 to 6 The chamfered surface includes a smooth area 19, the surface of which is flat. This improves the film quality of the passivation layer in the smooth area 19, enhancing the passivation effect and thus increasing the conversion efficiency of the photovoltaic cell and the module power.

[0061] The following description of the silicon substrate dicing process is based on one possible implementation. It should be noted that the following description is for understanding purposes only and is not intended to limit the specific implementation.

[0062] Step 1: Provide a silicon substrate to be sliced; for example, it can be a raw silicon wafer after being squared, cut, cleaned and inspected from a Czochralski single crystal silicon rod; the silicon substrate to be sliced ​​includes a first surface and a second surface opposite to each other;

[0063] Step two, using a first laser to process the first surface to create a guide groove on the first surface, the guide groove extending along a first direction; the first direction can be the length direction or the width direction of the silicon substrate to be sliced.

[0064] For example, the first laser described above is a destructive laser. Using a destructive laser to cut grooves on the silicon substrate to be sliced ​​serves as a guide groove, which facilitates the subsequent slicing of the silicon substrate along the guide groove, ensuring that the shape of the slicing silicon substrate meets the actual requirements. In some embodiments, the first laser is a nanosecond laser with a pulse width of 1ns to 500ns, an average power of 20W to 100W, a frequency of 100kHz to 5000kHz, and a spot size of 1μm to 40μm. For example, the laser acts in a pulsed manner on the silicon substrate to be sliced, causing a portion of the silicon substrate to be sliced ​​to vaporize and create the guide groove.

[0065] Step 3: Use a second laser to perform heat treatment on the first surface along the first direction, and form a heat treatment path;

[0066] For example, the second laser described above is a non-destructive thermal cracking laser. This non-destructive thermal cracking laser acts only on the portion of the silicon substrate to be sliced ​​located in the middle of the guide groove, reducing damage to the silicon substrate. In some embodiments, the second laser is a nanosecond continuous laser with a pulse width of 1 ns to 500 ns, an average power of 50 W to 500 W, and a spot size of 1 μm to 2 μm (circular or elliptical). For example, for the non-destructive thermal cracking laser, the laser is used to heat the silicon substrate to be sliced.

[0067] Step four: Along the heat treatment path, the silicon substrate to be sliced ​​is divided into at least two sliced ​​silicon substrates; the sliced ​​silicon substrates include a first side and a second side opposite to each other, and a side surface located between the first side and the second side. The side surface includes a first side surface, which is a new side surface generated after the thermal cracking of the silicon substrate.

[0068] For example, after a heat treatment path and two guide grooves are formed on the first surface of the silicon substrate to be sliced, water is sprayed onto the silicon substrate to be sliced, at which point the silicon substrate to be sliced ​​naturally cracks to form at least two sliced ​​silicon substrates.

[0069] Step 5: The silicon substrate is segmented using a third laser to form a wafer-like silicon substrate including a chamfered surface and a first side surface. The silicon substrate includes opposing first and second surfaces, and a side surface located between the first and second surfaces; the side surface includes a chamfered surface obtained by laser cutting; a molten silicon region and a smooth region are formed on the chamfered surface, and the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is greater than or equal to 10%.

[0070] It is understood that the aforementioned side surface includes the chamfered surface and the first side surface. Specifically, when the silicon substrate is processed using the third laser, the third laser processes the first side surface, and the remaining side surface serves as the aforementioned chamfered surface, with the first side surface located between the two chamfered surfaces.

[0071] Optionally, the third laser mentioned above is a picosecond laser. The third laser is a picosecond continuous laser with a pulse width of 1ps to 500ps, an average power of 20W to 100W, a frequency of 100kHz to 5000kHz, and a spot size of 1μm to 40μm. The diced silicon substrate is treated by vaporizing the diced silicon substrate using the laser.

[0072] Secondly, this utility model embodiment also provides a photovoltaic cell. This utility model embodiment does not specifically limit the type of photovoltaic cell; it can be any photovoltaic cell capable of converting light energy into electrical energy. For example, the photovoltaic cell provided in this utility model embodiment can be a photovoltaic cell that only includes a tunneling passivation contact structure, a photovoltaic cell that only includes a heterostructure, or a hybrid photovoltaic cell that includes both a tunneling passivation contact structure and a heterostructure, etc. Alternatively, the photovoltaic cell provided in this utility model embodiment can be a bifacial photovoltaic cell or a back-contact photovoltaic cell. For example, the photovoltaic cell provided in this utility model embodiment can be a PERC cell, a TOPcon cell, a TBC cell, or a heterojunction photovoltaic cell.

[0073] In the second aspect of this invention, the silicon substrate is a silicon substrate prepared from a raw wafer through a passivation layer process. It can be a silicon substrate immediately after the passivation layer is prepared, or a silicon substrate after the passivation layer is prepared and the battery is printed. This invention does not limit the stage of the silicon substrate after the passivation layer preparation. It is understood that the silicon substrate provided in the second aspect of this invention and the silicon substrate provided in the first aspect of this invention have the same original structural framework, except for the different preparation stages.

[0074] See Figure 1 , Figure 7 and Figure 8 The photovoltaic cell includes a silicon substrate 1 and a passivation layer. The silicon substrate includes a first surface and a second surface opposite to each other, and a side surface located between the first surface and the second surface; the side surface includes a chamfered surface obtained by laser cutting; a molten silicon region and a smooth region are formed on the chamfered surface, and the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is greater than or equal to 10%. The passivation layer is formed at least on the chamfered surface.

[0075] The photovoltaic cell provided by this utility model is obtained by laser cutting and slicing, which has good passivation effect and high photoelectric conversion efficiency.

[0076] As one possible implementation, the passivation layer includes at least one of a silicon nitride layer, an aluminum oxide layer, or a silicon nitride layer.

[0077] As one possible implementation, the passivation layer can be a single-layer film, such as a single layer of silicon nitride; or it can be a stack of multiple films, such as a stack of aluminum oxide and silicon nitride layers, or a stack of silicon nitride alone.

[0078] In the process of manufacturing photovoltaic cells, the silicon substrate needs to be cleaned multiple times to remove damage layers generated during laser cutting and reduce lattice defects. For example, the original silicon substrate needs to be cleaned before photovoltaic cell fabrication, or after the tunneling layer is fabricated. In a specific embodiment, the fabrication process steps for solar cells are: Cleaning 1-LP1-Boron diffusion-Patterning 1-Cleaning 2-LP2-Phosphorus diffusion-Patterning 2-Cleaning 3-Cleaning 4; where, due to the PSG protection formed by LP1 and boron diffusion during Cleaning 2, the chamfered surface is not cleaned.

[0079] For example, in step 1 of cleaning, a tank cleaning machine is used to clean the original silicon substrate. First, the original silicon substrate is polished and cleaned with NaOH solution at a high temperature of 75°C. After polishing and cleaning, the silicon substrate is then cleaned with HF and HCl. Next, the silicon substrate after HF and HCl cleaning is dried.

[0080] For example, in step 2 of cleaning, a tank cleaning machine is used, and the substrate is first cleaned with NaOH and additives and then with HF solution.

[0081] For example, in step 3 of cleaning, a chain machine is used to clean the silicon substrate, wherein a mixture of HNO3 and HF is used to clean the silicon substrate.

[0082] For example, in step 4 of cleaning, the silicon substrate is cleaned in a tank cleaning machine. First, the silicon substrate is cleaned with NaOH solution at 60°-70°. After cleaning with NaOH solution, the silicon substrate is then cleaned with HF and HCl. Finally, the silicon substrate cleaned with HF and HCl is dried.

[0083] As one possible implementation, see Figure 7 and Figure 8 An etched region 20 is formed on the chamfered surface 120. The etched region 20 has a first etch line 23, and the extension direction N of the first etch line 23 intersects the direction M from the first surface to the second surface. For example, the extension direction N of the first etch line 23 can be perpendicular to the direction M from the first surface to the second surface; or, the extension direction N of the first etch line 23 can form an angle between 70 and 110 degrees with the direction M from the first surface to the second surface.

[0084] Since the area of ​​the molten silicon region on the silicon substrate was previously controlled to be greater than 0 and less than or equal to 40%, after cleaning at the cell end, the molten silicon region on the chamfered surface is removed, leaving only the first etching line formed after laser cutting. The surface of the first etching line is flat, and it does not need to form a thick passivation layer to desaturate the surface dangling bonds generated by the chamfered surface of the silicon substrate being directly exposed to the air. It can be well passivated and film formed subsequently, resulting in good photovoltaic cell conversion efficiency and module power.

[0085] In one alternative approach, see Figure 7 and Figure 8 An etched region 21 is also formed on the chamfered surface 120. The etched region 21 begins on the first surface 10 and is located between the edge of the chamfered surface 120 and the first etched region 20. At least a portion of the etched region 21 is recessed from the chamfered surface toward the interior of the silicon substrate. By widening the area and size of the ablation zone in the silicon substrate, the recessed area in the etched region 21 has a small structure and a small area ratio, making it easier to passivate and form a film. Furthermore, the etched region 21, recessed from the chamfered surface toward the interior of the silicon substrate, can improve the light-trapping effect of the silicon substrate 1, fully utilize the light at the chamfered surface 120, increase the light absorption rate, and improve the light utilization rate of the chamfered surface 120 of the silicon substrate 1, thereby improving the efficiency of the photovoltaic cell.

[0086] In one alternative approach, see Figure 7 and Figure 8 A third etched region 22 is formed on the chamfered surface 120. One end of the third etched region 22 at least partially overlaps with the second surface 11. The third etched region 22 is located between the edge of the chamfered surface 120 and the first etched region 20. The third etched region 22 has a second etch line 24, and the extension direction N of the second etch line intersects the direction from the first surface to the second surface M. For example, the extension direction N of the second etch line 24 can be perpendicular to the direction from the first surface to the second surface M; or, the extension direction N of the second etch line 24 can form an angle between 70 and 110 degrees with the direction from the first surface to the second surface M. The surface of the second etch line 24 is flat, which can better passivate the film.

[0087] In one alternative approach, see Figure 7 and Figure 8 The number of second etching lines 24 per unit area is less than the number of first etching lines 23 per unit area. Since the third etching region 22 is closer to the second surface and the first etching region 20 is relatively closer to the center of the chamfered surface 120, it is more conducive to passivation film formation during the passivation process.

[0088] Thirdly, this utility model embodiment also provides a photovoltaic module. The photovoltaic module includes: a plurality of photovoltaic cells as described in the second aspect, an encapsulation layer covering the surface of the plurality of photovoltaic cells, and a cover plate covering the surface of the encapsulation layer away from the photovoltaic cells.

[0089] The photovoltaic module provided by this invention is manufactured using cells obtained by laser slicing, resulting in high module power.

[0090] The following describes the structure and effects of the silicon substrate of the first aspect and the photovoltaic cell of the second aspect of this utility model using several specific embodiments. It is worth noting that this is only for explaining this utility model and does not limit it.

[0091] Example 1

[0092] 10,000 N-type silicon substrates, each 210*210 mm in length and width and 130 μm in thickness, were selected after laser cutting. Each N-type silicon substrate includes a first and a second opposing surface, and a side surface located between the first and second surfaces. The side surface includes a chamfered surface obtained by laser cutting, on which molten silicon regions and smooth regions are formed. The ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is 60%-99%, and the ratio of the total area of ​​the molten silicon region to the total area of ​​the chamfered surface is 1%-40%.

[0093] Solar cells were fabricated on the aforementioned 10,000 silicon substrates, and the average efficiency value of the entire batch of solar cells was obtained using a photovoltaic cell efficiency tester.

[0094] Example 2

[0095] The difference from Example 1 is as follows:

[0096] The chamfered surface includes a molten silicon zone, an ablation zone, and a smooth zone. The ratio of the total area of ​​the smooth zone to the total area of ​​the chamfered surface is 10%-50%, the ratio of the total area of ​​the molten silicon zone to the total area of ​​the chamfered surface is 5%-40%, and the ratio of the total area of ​​the ablation zone to the total area of ​​the chamfered surface is 5%-45%.

[0097] Comparative Example 1

[0098] The difference from Example 1 is that:

[0099] The ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is 0-9%; the ratio of the total area of ​​the molten silicon region to the total area of ​​the chamfered surface is 91%-100%.

[0100] Comparative Example 2

[0101] The difference from Example 2 is that:

[0102] The ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is 0-9%; the ratio of the total area of ​​the molten silicon region to the total area of ​​the chamfered surface is 5%-40%; and the ratio of the total area of ​​the ablation region to the total area of ​​the chamfered surface is 51%-100%.

[0103] Table 1. Fragmentation rate and battery efficiency data for Examples 1-2 and Comparative Examples 1-2

[0104]

[0105]

[0106] As can be seen from the test data of the above embodiments, by controlling the ratio of the total area of ​​the smooth area to the total area of ​​the chamfered surface, the ratio of the total area of ​​the molten silicon area to the total area of ​​the chamfered surface, and the ratio of the total area of ​​the ablation area to the total area of ​​the chamfered surface within an ideal range, the breakage rate of the silicon substrate and the breakage rate in the cell manufacturing process can be guaranteed, and the cell efficiency of solar cells can be further improved.

[0107] In Comparative Example 1, the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is too small, while the ratio of the total area of ​​the molten silicon region to the total area of ​​the chamfered surface is too large. In Comparative Example 2, the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is too small, while the ratio of the total area of ​​the ablation region to the total area of ​​the chamfered surface is too large. When photovoltaic cells are fabricated using silicon substrates with the above parameters, compared with silicon substrates where the ratios of the total area of ​​the smooth region to the total area of ​​the chamfered surface, the molten silicon region to the total area of ​​the chamfered surface, and the ablation region to the total area of ​​the chamfered surface are all controlled within ideal ranges, the breakage rate during the cell fabrication process increases, resulting in a significant loss of photovoltaic cell efficiency.

[0108] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0109] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A silicon substrate, characterized by, The silicon substrate includes a first surface and a second surface opposite to each other, and a side surface located between the first surface and the second surface; the side surface includes a chamfered surface obtained by laser cutting. The chamfered surface has a molten silicon region and a smooth region, and the ratio of the total area of ​​the smooth region to the total area of ​​the chamfered surface is greater than or equal to 10%.

2. The silicon substrate of claim 1, wherein The ratio of the total area of ​​the molten silicon zone to the total area of ​​the chamfered surface is greater than 0% and less than or equal to 40%.

3. The silicon substrate of claim 1, wherein The molten silicon zones are distributed in clusters.

4. The silicon substrate of claim 1, wherein The end of the molten silicon zone is at least one of a wavy boundary formed by multiple curves and / or a sawtooth boundary formed by multiple line segments.

5. The silicon substrate according to claim 4, characterized in that, Along the direction from the first surface to the second surface, the height of the wave crest of the wavy boundary is greater than or equal to 30 μm and less than or equal to 40 μm; and / or, the wavelength of the wavy boundary is greater than or equal to 10 μm and less than or equal to 20 μm; and / or, the height difference between any two adjacent wave crests is greater than or equal to 5 μm and less than or equal to 15 μm. And / or, the included angle formed by the curves on both sides of any wave crest is greater than or equal to 5° and less than or equal to 10°; and / or, the vertical distance between the end of the molten silicon region closest to the first surface and the wave crest is greater than or equal to 70μm and less than or equal to 100μm; And / or, along the direction from the first surface to the second surface, the tooth height of the serrated boundary is greater than or equal to 30 μm and less than or equal to 40 μm; the tooth pitch of the serrated boundary is greater than or equal to 10 μm and less than or equal to 20 μm; and / or, the height difference between any two adjacent tooth peaks is greater than or equal to 5 μm and less than or equal to 15 μm; and / or, the included angle formed by any serration is greater than or equal to 5° and less than or equal to 10°; and / or, the vertical distance between the end of the molten silicon region closest to the first surface and the tooth peak is greater than or equal to 70 μm and less than or equal to 100 μm; And / or, the length of the orthographic projection of the molten silicon region onto the second surface is less than or equal to 10 μm.

6. The silicon substrate of claim 1, wherein An ablation zone is also formed on the chamfered surface. The ablation zone starts from the first surface and is located between the edge of the chamfered surface and the molten silicon zone. At least a portion of the ablation zone is recessed from the chamfered surface toward the interior of the silicon substrate.

7. The silicon substrate of claim 6, wherein The ratio of the total area of ​​the ablation zone to the total area of ​​the chamfered surface is less than or equal to 50%.

8. The silicon substrate of claim 6, wherein Along the direction from the first surface to the second surface, the length of the ablation zone is less than or equal to 50 μm; And / or, the length of the orthographic projection of the ablation zone onto the second surface is less than or equal to 3 μm.

9. The silicon substrate of claim 1, wherein The smooth region is located between the molten silicon region and the second surface, and one end of the smooth region at least partially overlaps with the second surface.

10. A photovoltaic cell, characterized by include: The silicon substrate according to any one of claims 1 to 9; A passivation layer is formed at least on the chamfered surface.

11. The photovoltaic cell of claim 10, wherein, An etched area is formed on the chamfered surface. The etched area has a first etch line, and the extension direction of the first etch line intersects the direction from the first surface to the second surface.

12. The photovoltaic cell of claim 11, wherein, A second etched region is also formed on the chamfered surface. The second etched region starts from the first surface and is located between the edge of the chamfered surface and the first etched region. At least a portion of the second etched region is recessed from the chamfered surface toward the interior of the silicon substrate.

13. Photovoltaic cell according to claim 11 or 12, characterized in that The chamfered surface has three etched regions, one end of which at least partially overlaps with the second surface. The three etched regions are located between the edge of the chamfered surface and the first etched region. The three etched regions also have a second etch line, the extension direction of which intersects the direction from the first surface to the second surface.

14. The photovoltaic cell of claim 13, wherein, The number of second etching lines per unit area is less than the number of first etching lines per unit area.

15. A photovoltaic module, characterized by, include: Multiple photovoltaic cells as described in any one of claims 10 to 14; An encapsulation layer covers the surface of the plurality of photovoltaic cells; A cover plate that covers the surface of the encapsulation layer away from the photovoltaic cell.

Images