Back contact cells, stacked cells and photovoltaic modules

Abstract

The application relates to a back contact cell, a laminated cell and a photovoltaic module, which can balance carrier transport performance and passivation performance. The back contact cell comprises a semiconductor substrate including a front surface and a back surface, the back surface being provided with a first region, a second region and a spacing region arranged in sequence in an X-axis direction, the spacing region including a first isolation region and a second isolation region in the X-axis direction, the first isolation region being located between the first region and the second isolation region, and the distance between the bottom wall of the first isolation region and the center line of the semiconductor substrate in a Z-axis direction being less than the distance between the bottom wall of the first isolation region and the center line of the semiconductor substrate; a laminated structure is arranged in the first region and includes a first doped layer, a first tunneling oxide layer and a second doped layer arranged in the first region, the second doped layer and the first doped layer being opposite in conductive type; a third doped layer is formed in the second region and is opposite in conductive type to the first doped layer; and a first electrode and a second electrode.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back contact cell, a tandem cell, and a photovoltaic module. Background Technology

[0002] Back-contact technology is a platform technology that eliminates front-side grid obstruction, resulting in high cell efficiency and aesthetically pleasing modules. Front-side passivation optimization is unaffected by the cell emitter. IBC (Interdigitated back-contact) is the cornerstone of back-contact solar cell technology. IBC cells can be combined with various high-efficiency cell technologies to further improve photoelectric conversion efficiency; for example, IBC technology can be combined with HJT (High-Jet-Temperature) cells to create HBC cells or with TOPCON (Top-Contact) cells to create TBC (Top-Contact) cells.

[0003] Existing back-contact passivation structures primarily consist of a tunneling dielectric oxide layer plus doped polysilicon. The tunneling oxide layer needs to simultaneously achieve both interface passivation performance and carrier transport performance. Achieving a balance between passivation and superior contact performance is a key challenge. Utility Model Content

[0004] Based on this, it is necessary to provide a back-contact cell, a tandem cell, and a photovoltaic module to address how to balance carrier transport performance and passivation performance.

[0005] This application proposes a back-contact battery, comprising: a semiconductor substrate including a front side and a back side, wherein the back side has a first region and a second region arranged sequentially in the X-axis direction, and a spacing region located between the first region and the second region; in the X-axis direction, the spacing region includes a first isolation region and a second isolation region arranged sequentially, the first isolation region being located between the first region and the second isolation region; in the Z-axis direction, the distance between the bottom wall of the second isolation region and the centerline of the semiconductor substrate is less than the distance between the bottom wall of the first isolation region and the centerline of the semiconductor substrate; a stacked structure disposed in the first region, the stacked structure including a first doped layer, a first tunneling oxide layer and a second doped layer arranged sequentially in the first region, the second doped layer having an opposite conductivity type to the first doped layer; a third doped layer formed in the second region, the third doped layer having an opposite conductivity type to the first doped layer; and a first electrode and a second electrode, the first electrode being in electrical contact with the second doped layer, and the second electrode being in electrical contact with the third doped layer.

[0006] In some embodiments, a second tunneling oxide layer and a third tunneling oxide layer are further included, wherein the second tunneling oxide layer is located between the stacked structure and the semiconductor substrate; and the third tunneling oxide layer is located between the third doped layer and the semiconductor substrate.

[0007] In some embodiments, the semiconductor substrate is an n-type semiconductor, and the second doped layer and the third doped layer have the same conductivity type, but different conductivity type from the first doped layer.

[0008] In some embodiments, a fourth tunneling oxide layer and a fourth doped layer are sequentially stacked on the third doped layer, wherein the conductivity type of the fourth doped layer is the same as that of the third doped layer.

[0009] In some embodiments, the first doped layer, the second doped layer, and the third doped layer are all doped polysilicon layers.

[0010] In some embodiments, the width of the interval region in the X-axis direction is 40-65 μm.

[0011] In some embodiments, the width of the first isolation region is 5-10 μm, and the width of the second isolation region is 35-55 μm.

[0012] In some embodiments, a first passivation layer is also included, which covers the surfaces of the first region, the second region, and the spacer region.

[0013] In some embodiments, a first antireflection layer is also included, which covers the first passivation layer.

[0014] In some embodiments, a second passivation layer and a second antireflection layer are also included, which are sequentially disposed on the front side of the semiconductor substrate.

[0015] This application proposes a stacked battery, including the aforementioned back contact battery; a perovskite battery disposed on the front side of the back contact battery, the perovskite battery including, in sequence away from the back contact battery, a hole transport layer, a perovskite active absorption layer, an electron transport layer, an interface buffer layer, a transparent conductive layer, an antireflection film layer, and a contact electrode electrically in contact with the transparent conductive layer.

[0016] This application also proposes a photovoltaic module including the aforementioned back contact battery.

[0017] In this application, by dividing the "dielectric layer" on the back side into a stacked structure emission region and a second electrode emission region, the stacked structure emission region can balance its interface passivation and carrier transport performance, and the second electrode emission region can also ensure contact performance. Thus, the back contact cell and photovoltaic module of this application can achieve electron transport performance from the absorption layer to the back electrode while maintaining a good passivation effect and reducing leakage and short circuit. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a back contact battery according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the structure of a back contact battery according to another embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the structure of a stacked battery according to an embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the structure of a photovoltaic module according to an embodiment of this application.

[0022] Figure label:

[0023] 100. Photovoltaic module; 1. Back contact cell; 10. Semiconductor substrate; C. Center line; 110. Front side; 111. Second passivation layer; 112. Second antireflection layer; 120. Back side; 130. First region; 140. Second region; 150. Spacer region; 151. First isolation region; 152. Second isolation region; 20. Stacked structure; 210. First doped layer; 220. First tunneling oxide layer; 230. Second doped layer; 240. Second tunneling oxide layer; 30. 1. Third doped layer; 410. First electrode; 420. Second electrode; 50. Third tunneling oxide layer; 60. Fourth tunneling oxide layer; 70. Fourth doped layer; 80. First passivation layer; 90. First antireflection layer; 2. Perovskite solar cell; 21. Hole transport layer; 22. Perovskite active layer; 23. Electron transport layer; 24. Interface buffer layer; 25. Transparent conductive layer; 26. Antireflection film layer; 27. Contact electrode; 3. First adhesive film; 4. Second adhesive film; 5. Front plate; 6. Back plate. Detailed Implementation

[0024] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0027] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art.

[0028] As used herein, the term "semiconductor" can refer to, for example, a material layer, substrate, wafer, or substructure, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon sapphire (SOS) technology, silicon-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art.

[0029] This application aims to propose a back-contact battery with a contact structure that balances carrier transport performance and passivation performance, achieving good passivation while maintaining good electron transport performance from the absorption layer to the back electrode, thus reducing leakage and short circuits. Based on this, this application also proposes a photovoltaic module incorporating such a back-contact battery.

[0030] refer to Figure 1This application provides an embodiment of a back contact battery 1. The back contact battery 1 includes a semiconductor substrate 10. The semiconductor substrate 10 includes a front side 110 and a back side 120. The back side 120 has a first region 130 and a second region 140 arranged sequentially in the X-axis direction, and a spacing region 150 located between the first region 130 and the second region 140. In the X-axis direction, the spacing region 150 includes a first isolation region 151 and a second isolation region 152 arranged sequentially. The first isolation region 151 is located between the first region 130 and the second isolation region 152. In the Z-axis direction, the distance d1 between the bottom wall of the second isolation region 152 and the center line C of the semiconductor substrate 10 is smaller than the distance d2 between the bottom wall of the first isolation region 151 and the center line C of the semiconductor substrate 10.

[0031] The back contact battery 1 also includes a stacked structure 20. The stacked structure 20 is disposed in a first region 130 and includes a first doped layer 210, a first tunneling oxide layer 220, and a second doped layer 230 sequentially disposed in the first region 130. The second doped layer 230 and the first doped layer 210 have opposite conductivity types. The back contact battery 1 also includes a third doped layer 30, a first electrode 410, and a second electrode 420. The third doped layer 30 is formed in a second region 140, and the conductivity type of the third doped layer 30 is opposite to that of the first doped layer 210. The first electrode 410 is in electrical contact with the second doped layer 230, and the second electrode 420 is in electrical contact with the third doped layer 30. The thicknesses of the first doped layer 210, the first tunneling oxide layer 220, the second doped layer 230, and the third doped layer 30 can be 5-300 nm, respectively; for example, they can be 5 nm, 20 nm, 60 nm, 100 nm, 120 nm, 200 nm, 260 nm, 300 nm, 400 nm, 450 nm, and 500 nm.

[0032] The semiconductor substrate 10 is used to receive incident light and generate photogenerated carriers. The material of the semiconductor substrate 10 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the substrate material may also be silicon carbide, organic materials, or multi-component compounds. Multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenide, etc. Here, when the back-contact battery 1 is used, the front side 110 faces the sun. The back side 120 is the backlight side, the side facing away from the sun. (Reference) Figure 1 The X-axis is parallel to the front 110° and the back 120°. The Z-axis is perpendicular to the front 110° and the back 120°.

[0033] The stacked structure 20 and the third doped layer 30 are used to form emitter regions with different conductivity types, respectively defined as the stacked structure emitter region and the second electrode emitter region. In this application, the stacked structure 20 includes doped layers of two polarities. The material of the first tunneling oxide layer 220 can be, but is not limited to, dielectric materials with tunneling properties such as alumina, silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon. The first tunneling oxide layer 220 can be a stacked structure of one or more of these materials. The first tunneling oxide layer 220 mainly provides good interface passivation and carrier transport.

[0034] The first doped layer 210 and the second doped layer 230 are used to form a good stacked structure 20 with the first tunneling oxide layer 220. During the fabrication process, the first doped layer 210 and the second doped layer 230 are ensured to have a high doping concentration and low internal diffusion to avoid excessive parallel resistance. The third doped layer 30 is used to ensure good contact performance.

[0035] The first doped layer 210, the second doped layer 230, and the third doped layer 30 are all semiconductor doped layers. Regarding their internal arrangement, the first doped layer 210, the second doped layer 230, and the third doped layer 30 can be amorphous, microcrystalline, single-crystal, nanocrystalline, or polycrystalline. Regarding specific materials, the first doped layer 210, the second doped layer 230, and the third doped layer can be silicon (Si), germanium (Ge), antimony (Sb), silicon carbide (SiCx), or gallium arsenide (GaAs). Regarding conductivity type, the first doped layer 210, the second doped layer 230, and the third doped layer 30 can be n-type or p-type doped layers. Specifically, the first doped layer 210, the second doped layer 230, and the third doped layer 30 are all doped polycrystalline silicon layers.

[0036] The interval region 150 includes a first isolation zone 151 and a second isolation zone 152 arranged sequentially, with their bottom walls positioned at different locations in the Z direction. (See reference) Figure 1 The bottom wall of the second isolation region 152 is recessed relative to the bottom wall of the first isolation region 151, thus forming an isolation structure with different heights, thereby blocking the emitter region of the stacked structure and the emitter region of the second electrode. That is, the bottom wall of the second isolation region 152 is recessed relative to the bottom wall of the first isolation region 151, and the depth of the second isolation region 152 on the back side of the semiconductor substrate 10 is greater than the depth of the first isolation region 151.

[0037] In this application, the first isolation region 151 is located between the second isolation region 152 and the stacked structure 20. The first isolation region 151 can eliminate the influence of the fabrication of the second doped layer 230 on the width of the spacer region 150. Specifically, taking the second doped layer 230 as a phosphorus doped layer as an example, when the phosphorus doped layer is formed, a phosphorus diffusion region is formed on the side of the second region 140. This phosphorus diffusion region will affect the width of the isolation region, thereby affecting the leakage prevention effect of the isolation region. In this application, when the isolation region is formed between the first region 130 and the second region 140 using a laser, the first isolation region 151 and the second isolation region 152 are formed simultaneously. When forming the first isolation region 151, since the phosphorus diffusion region needs to be removed by the laser, the depth of the first isolation region 151 is less than the depth of the second isolation region 152.

[0038] The widths of the first isolation region 151 and the second isolation region 152 are determined based on the width of the phosphorus diffusion region. In some embodiments, the width of the first isolation region 151 is 5-10 μm, and the width of the second isolation region is 35-55 μm. Optionally, the width of the first isolation region 151 is 10 μm, 12 μm, 14 μm, or 15 μm; and the width of the second isolation region is 45 μm, 48 μm, 50 μm, or 55 μm. The height difference between the first isolation region 151 and the second isolation region 152 is 10-30 μm, such as 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm.

[0039] Each doped layer and tunneled oxidation forms the "dielectric layer" on the back side 120. In this application, by dividing the "dielectric layer" of the back side 120 into a stacked structure emitter region and a second electrode emitter region, the stacked structure emitter region can balance its interface passivation and carrier transport performance, and the second electrode emitter region can also ensure contact performance. Thus, the back contact battery of this application can achieve electron transport performance from the absorption layer to the back electrode while maintaining a good passivation effect and reducing leakage and short circuit.

[0040] In some examples, the semiconductor substrate 10 is an n-type semiconductor, and the second doped layer 230 and the third doped layer 30 have the same conductivity type, which is opposite to that of the first doped layer 210. Specifically, in this embodiment, the semiconductor substrate 10 is an n-type semiconductor, the first doped layer 210 is a p-type doped layer, and the second doped layer 230 and the third doped layer 30 are n-type doped layers. The dopants in the p-type doped layer include boron, gallium, indium, etc. The dopants in the n-type doped layer can be, for example, phosphorus, arsenic, antimony, etc. Optionally, the second doped layer 230 and the third doped layer 30 are phosphorus doped layers, and their doping concentration is controlled in the range of 1e19cm-3 to 6e19cm-3.

[0041] The second doped layer 230 and the third doped layer 30 have the same conductivity type, so they can be formed in the same process, thus simplifying the fabrication process.

[0042] refer to Figure 1 Furthermore, the back contact battery 1 in this embodiment also includes a second tunneling oxide layer 240 and a third tunneling oxide layer 50. The second tunneling oxide layer 240 is located between the stacked structure 20 and the semiconductor substrate 10; the third tunneling oxide layer 50 is located between the third doped layer 30 and the semiconductor substrate 10. The thicknesses of the second tunneling oxide layer 240 and the third tunneling oxide layer 50 can be 5-300 nm, respectively; for example, they can be 5 nm, 20 nm, 60 nm, 100 nm, 120 nm, 200 nm, 260 nm, 300 nm, 400 nm, 450 nm, and 500 nm.

[0043] The specific materials of the second tunneling oxide layer 240 and the third tunneling oxide layer 50 can be exactly the same as those of the first tunneling oxide layer 220, and will not be described again here. By setting the second tunneling oxide layer 240 and the third tunneling oxide layer 50, the passivation performance is further enhanced in the emitter region of the stacked structure and the emitter region of the second electrode, respectively. This can reduce the recombination of charge carriers on the substrate surface, thereby increasing the open-circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0044] refer to Figure 1 In this embodiment, the system further includes a first passivation layer 80, a first antireflection layer 90, a second passivation layer 111, and a second antireflection layer 112. The first passivation layer 80 covers the surfaces of the first region 130, the second region 140, and the spacer region 150. The antireflection layer covers the first passivation layer 80. The second passivation layer 111 and the second antireflection layer 112 are sequentially disposed on the front side 110 of the semiconductor substrate 10. The thickness of each passivation layer and antireflection layer can be 5-300 nm; for example, it can be 5 nm, 20 nm, 60 nm, 100 nm, 120 nm, 200 nm, 260 nm, 300 nm, 400 nm, 450 nm, or 500 nm.

[0045] The first passivation layer 80 and the second passivation layer 111 can ensure that the surface of the semiconductor substrate 10 has a good passivation effect. The first antireflection layer 90 and the second antireflection layer 112 can reduce the optical reflection loss of the antireflection layer and improve the light absorption efficiency of the back contact cell 1.

[0046] The materials of the first passivation layer 80 and the second passivation layer 111 can be silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The first passivation layer 80 and the second passivation layer 111 can be a single-layer structure or a multi-layer structure. For a multi-layer structure, the materials of different layers can be different from each other, or some layers can be made of the same material but different from the materials of other layers. For example, the first passivation layer 80 and the second passivation layer 111 can be a multi-layer structure of silicon nitride and aluminum oxide layers.

[0047] The materials of the first antireflective layer 90 and the second antireflective layer 112 can be silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The first antireflective layer 90 and the second antireflective layer 112 can be a single-layer structure or a multi-layer structure. For a multi-layer structure, the materials of different layers can be different from each other, or some layers can be made of the same material but different from the materials of other layers. For example, the first antireflective layer 90 and the second antireflective layer 112 can be a multi-layer structure of silicon nitride and aluminum oxide layers.

[0048] In this application, the width of the spacing region 150 in the X-axis direction is 40-65 μm. Optionally, the width of the spacing region 150 is, for example, 40 μm, 50 μm, 55 μm, 60 μm, or 65 μm.

[0049] refer to Figure 2 This illustrates a back contact battery 1 according to another embodiment of this application, and... Figure 1 The difference in the embodiment shown is that: in another embodiment, a fourth tunneling oxide layer 60 and a fourth doped layer 70 are sequentially disposed on the third doped layer 30, and the conductivity type of the fourth doped layer 70 is the same as that of the third doped layer 30.

[0050] In another embodiment, the fourth tunneling oxide layer 60 and the fourth doped layer 70 constitute a passivation contact structure, which enhances the passivation performance and reduces carrier recombination on the substrate surface, thereby increasing the open-circuit voltage of the solar cell and improving its photoelectric conversion efficiency. The thicknesses of the fourth tunneling oxide layer 60 and the fourth doped layer 70 can be 5-300 nm, respectively; for example, they can be 5 nm, 20 nm, 60 nm, 100 nm, 120 nm, 200 nm, 260 nm, 300 nm, 400 nm, 450 nm, or 500 nm.

[0051] The material of the fourth tunneling oxide layer 60 can be the same as that of the first tunneling oxide layer 220 and other tunneling layers. Optionally, the material of the fourth doped layer 70 can be silicon (Si), germanium (Ge), antimony (Sb), silicon carbide (SiCx), or gallium arsenide (GaAs), etc.

[0052] In this embodiment, the semiconductor substrate 10 is an n-type semiconductor, and the second doped layer 230 and the third doped layer 30 have the same conductivity type, which is opposite to that of the first doped layer 210. However, unlike the previous embodiment, in this embodiment, the first doped layer 210 is an n-type doped layer, and the second doped layer 230 and the third doped layer 30 are both p-type doped layers. In addition, the fourth doped layer 70 is a p-type doped layer, and the influence of the p-type dopant diffusion during the fabrication process does not need to be considered.

[0053] Figure 1 The preparation process of the back contact battery 1 shown is briefly described below.

[0054] S1. Polish the silicon wafer to serve as a semiconductor substrate. S2. Sequentially deposit a silicon oxide film and a polysilicon layer on the back side of the silicon wafer. S3. Dope the polysilicon layer with phosphorus to form a P+ polysilicon doped layer, i.e., the first doped layer 210. S4. Remove the phosphorus doped layer and silicon oxide film on the second region 140; or remove only the phosphorus doped layer on the second region 140, with a doping concentration ranging from 1e19cm⁻³ to 6e19cm⁻³. S5. Clean to remove any remaining phosphorus doped layer and silicon oxide film on the second region 140. S6. Form the second doped layer 230 and the third doped layer 30, both specifically phosphorus-doped N+ polysilicon doped layers, with a doping concentration ranging from 1e19cm⁻³ to 6e19cm⁻³. S7. Use a laser to create the first isolation region 151 and the second isolation region 152. S8, texturing and cleaning to remove residual phosphorus-doped layers and silicon oxide films in the first isolation region 151 and the second isolation region 152; a textured surface is also formed on the front side 110. S9, a passivation layer and an antireflection layer are formed on the front side 110 and the back side 120, respectively. S10, a first electrode 410 and a second electrode 420 are formed.

[0055] Figure 2 The preparation process of the back contact battery 1 shown is similar in principle to the preparation process described above, except that... Figure 2 In the back contact battery 1 shown, a fourth tunneling oxide layer 60 and a fourth doped layer 70 are further formed on the third doped layer 30.

[0056] refer to Figure 3 This application also proposes a stacked battery. The stacked battery includes the aforementioned back contact battery 1 and perovskite battery 2. The perovskite battery 2 is disposed on the front side of the back contact battery 1. The perovskite battery 2 includes, in sequence away from the back contact battery 1, a hole transport layer 21, a perovskite active layer 22, an electron transport layer 23, an interface buffer layer 24, a transparent conductive layer 25, and an antireflection film layer 26, and further includes a contact electrode 27 electrically connected to the transparent conductive layer 25.

[0057] refer to Figure 4 This application also proposes a photovoltaic module 100, including the back contact battery 1 described in any of the above embodiments.

[0058] For example, the photovoltaic module 100 includes a back contact cell 1 or Figure 3 The stacked battery, the first adhesive film 3 and the second adhesive film 4, the front plate 5 and the back plate 6.

[0059] Taking a photovoltaic module including a back contact cell 1 as an example, a first encapsulating film 3 and a second encapsulating film 4 are located on opposite sides of the back contact cell 1. Specifically, the first encapsulating film 3 faces the front side 110 of the back contact cell 1, and the second encapsulating film 4 faces the back side 120 of the back contact cell 1. Exemplarily, both the first encapsulating film 3 and the second encapsulating film 4 are EPE encapsulating films. A front panel 5 is disposed on the side of the first encapsulating film 3 facing away from the back contact cell 1, and a back panel 6 is disposed on the side of the second encapsulating film 4 facing away from the back contact cell 1. In this way, the front panel 5 is bonded to the back contact cell 1 through the first encapsulating film 3, and the back panel 6 is bonded to the back contact cell 1 through the second encapsulating film 4, thereby forming a photovoltaic module 100. Exemplarily, both the front panel 5 and the back panel 6 are transparent glass plates.

[0060] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back-contact battery, characterized in that, include: A semiconductor substrate includes a front side and a back side. The back side has a first region and a second region arranged sequentially in the X-axis direction, and a gap region located between the first region and the second region. In the X-axis direction, the gap region includes a first isolation region and a second isolation region arranged sequentially. The first isolation region is located between the first region and the second isolation region. In the Z-axis direction, the distance between the bottom wall of the second isolation region and the center line of the semiconductor substrate is less than the distance between the bottom wall of the first isolation region and the center line of the semiconductor substrate. A stacked structure is disposed in the first region, the stacked structure comprising a first doped layer, a first tunneling oxide layer and a second doped layer sequentially disposed in the first region, wherein the second doped layer and the first doped layer have opposite conductivity types. A third doped layer is formed in the second region, the conductivity type of the third doped layer being opposite to that of the first doped layer; and A first electrode and a second electrode, wherein the first electrode is in electrical contact with the second doped layer and the second electrode is in electrical contact with the third doped layer.

2. The back contact battery according to claim 1, characterized in that, It also includes a second tunneling oxide layer and a third tunneling oxide layer, wherein the second tunneling oxide layer is located between the stacked structure and the semiconductor substrate; and the third tunneling oxide layer is located between the third doped layer and the semiconductor substrate.

3. The back contact battery according to claim 1, characterized in that, The semiconductor substrate is an n-type semiconductor, and the second doped layer and the third doped layer have the same conductivity type, but different conductivity type from the first doped layer.

4. The back contact battery according to claim 1, characterized in that, It also includes a fourth tunneling oxide layer and a fourth doped layer sequentially disposed on the third doped layer, wherein the conductivity type of the fourth doped layer is the same as that of the third doped layer.

5. The back contact battery according to claim 1, characterized in that, The first doped layer, the second doped layer, and the third doped layer are all doped polycrystalline silicon layers.

6. The back contact battery according to claim 1, characterized in that, In the X-axis direction, the width of the interval region is 40-65 μm.

7. The back contact battery according to claim 6, characterized in that, The width of the first isolation zone is 5-10 μm, and the width of the second isolation zone is 35-55 μm.

8. The back contact battery according to claim 1, characterized in that, It also includes a first passivation layer that covers the surfaces of the first region, the second region, and the spacer region.

9. A stacked battery, characterized in that, include: The back contact battery as described in any one of claims 1-8; A perovskite solar cell is disposed on the front side of the back contact cell. The perovskite solar cell includes, in sequence away from the back contact cell, a hole transport layer, a perovskite active absorption layer, an electron transport layer, an interface buffer layer, a transparent conductive layer, an antireflection film layer, and a contact electrode electrically in contact with the transparent conductive layer.

10. A photovoltaic module, characterized in that, It includes the back contact battery as described in any one of claims 1-8, or the stacked battery as described in claim 9.

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