An FPGA-based high-speed ADC signal acquisition circuit system
By introducing an FPGA as the main controller into the ADC signal acquisition system, combined with a differential double balun circuit and a power supply circuit, efficient and accurate acquisition and testing of high-speed ADC signals are achieved. This solves the problems of expensive and inefficient testing equipment in traditional methods and meets the verification needs of complex application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHAANXI ELECTRONIC TECH RES INST
- Filing Date
- 2025-06-05
- Publication Date
- 2026-07-28
AI Technical Summary
Existing high-speed ADC signal acquisition technologies suffer from problems such as expensive testing equipment, stringent testing accuracy requirements, and low testing efficiency. In particular, traditional methods are unable to meet the demands of real-time performance and computing power in the testing of high-speed, high-precision ADCs.
Using an FPGA as the main controller, combined with an ADC main control circuit, a differential double balun circuit, and a power supply circuit, the FPGA circuit realizes data acquisition and analog-to-digital conversion, performs digital filtering within the FPGA, generates chart information, and transmits it to the PC, reducing dependence on imported testing equipment and improving the degree of testing automation.
It achieves efficient and accurate ADC signal acquisition and testing, meets the verification requirements of high-speed ADCs in complex application scenarios, reduces dependence on expensive testing equipment, and improves the automation and efficiency of testing.
Smart Images
Figure CN224571239U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic system technology, and in particular to a high-speed ADC signal acquisition circuit system based on FPGA. Background Technology
[0002] In recent years, signal acquisition technology has become a crucial aspect of ADC (Analog-to-Digital Converter) chip development. However, in verifying new product functionality and troubleshooting chip defects, the testing and verification of mixed-signal circuits not only consumes a significant amount of time but also constitutes a substantial portion of chip development costs. Especially in the testing of high-speed, high-precision ADCs, traditional methods face challenges such as expensive testing equipment, stringent minimum signal strength (LSB) requirements, and low testing efficiency.
[0003] Commonly used testing methods include code density histogram (CDH) method, sine fitting method, and Fast Fourier Transform (FFT) method. Among these, CDH requires the acquisition of massive amounts of data, resulting in relatively low efficiency; sine fitting method is suitable for low LSB testing of high-precision ADCs; and FFT method, as a core means of dynamic testing, relies on window functions to suppress spectral leakage to improve testing accuracy. However, these methods place extremely high demands on the real-time performance, computational power, and data transmission rate of the testing system.
[0004] FPGAs are increasingly demonstrating enhanced performance in timing control and logic operations. In high-speed data acquisition system design, FPGAs serve as the main controller, compatible with DSP and other IP cores. The FPGA acts as the control and processing core of the entire system, using an AD module to acquire and convert data from analog to digital. The acquired data is then transmitted to the FPGA, where internal calculations and static and dynamic parameter analyses are performed. Graph information is generated and processed within the FPGA before being transmitted to relevant boards. Therefore, there is an urgent need for an efficient, high-precision FPGA-based ADC signal acquisition and testing system to reduce reliance on imported testing equipment, improve testing automation, and meet the verification requirements of high-speed ADCs in complex application scenarios. Utility Model Content
[0005] The embodiments of this application provide a high-speed ADC signal acquisition circuit system based on FPGA.
[0006] To achieve the above objectives, embodiments of this application provide a high-speed ADC signal acquisition circuit system based on FPGA, comprising: ADC main control circuit; The differential double balun circuit has an analog input signal at its input terminal and its output terminal connected to the input terminal of the ADC main control circuit. The FPGA circuit has its input terminals connected to the output terminals of the ADC main control circuit. The power supply circuit is connected to the ADC main control circuit and the FPGA circuit.
[0007] In one embodiment, it further includes a crystal oscillator circuit, which is connected to the ADC main control circuit and the power supply circuit.
[0008] In one embodiment, the crystal oscillator circuit includes: an active crystal oscillator OSC1, which is used to generate an 80MHz clock signal; The VCC pin of the active crystal oscillator OSC1 is connected to the power supply circuit; the VCC pin of the active crystal oscillator OSC1 is also connected to one end of the first isolation capacitor C809, and the other end of the first isolation capacitor C809 is grounded; the OUT pin of the active crystal oscillator OSC1 is connected to the first isolation resistor R815; the OE pin of the active crystal oscillator OSC1 is connected to one end of the first pull-down resistor R814, and the other end of the first pull-down resistor R814 is connected to GND; the GND pin of the active crystal oscillator OSC1 is connected to GND.
[0009] In one embodiment, it further includes a reference circuit, which is connected to the ADC main control circuit and the power supply circuit.
[0010] In one embodiment, the reference circuit includes: a reference chip U201; the IN pin of the reference chip U201 is connected to the power supply circuit through one end of a first filter capacitor C201; the other end of the first filter capacitor C201 is connected to GND; the OUT pin of the reference chip U201 is connected to the ADC main control circuit through one end of a second filter capacitor C202; the other end of the second filter capacitor C202 is connected to GND; the SET pin of the reference chip U201 is connected to one end of a first pull-up resistor R201 and one end of a first isolation resistor R202, the other end of the first pull-up resistor R201 is connected to the power supply circuit, and the other end of the first isolation resistor R202 is connected to GND.
[0011] In one embodiment, it further includes: an SPI circuit, which is connected to the ADC main control circuit and the FPGA circuit respectively; The SPI circuit includes a first communication branch and a second communication branch. The first communication branch transmits data signals, and the second communication branch transmits clock signals and chip select signals.
[0012] In one embodiment, the first communication branch includes: a first SPI chip U301; the VCC pin of the first SPI chip U301 is connected to the power supply circuit and connected to GND through a first pull-down capacitor C301; the Y1 pin of the first SPI chip U301 is connected to one end of a first pull-up resistor R310 and one end of a first impedance resistor R311, the other end of the first pull-up resistor R310 is connected to DVDD, and the other end of the first impedance resistor R311 is connected to SDIO_DUT; the Y2 pin of the first SPI chip U301 is defined as USB_SDO and is connected to the power supply circuit through a second pull-up resistor R312; the A1 pin of the first SPI chip U301 is defined as USB_SDI and is connected to GND through a first pull-down resistor R309, and the A1 pin is connected to the FPGA circuit through the FMC interface; the A2 pin of the first SPI chip U301 is defined as SDIO_DUT and is pulled down to GND through a second pull-down resistor R313.
[0013] In one embodiment, the second communication branch includes: a second SPI chip U302, the VCC pin of which is connected to the power supply circuit and connected to GND through a second pull-down capacitor C302; the Y1 pin of the second SPI chip U302 is defined as SCLK_DUT and connected to GND through a fifth pull-down resistor R315; the Y2 pin of the second SPI chip U302 is defined as CSB_DUT and connected to the power supply circuit through a third pull-up resistor R314; the A1 pin of the second SPI chip U302 is defined as USB_SCLK and connected to GND through a third pull-down resistor R316, and the A1 pin is connected to the FPGA circuit through the FMC interface; the A2 pin of the second SPI chip U302 is defined as USB_CSB and pulled down to GND through a fourth pull-down resistor R317.
[0014] In one embodiment, the power supply circuit includes a first power supply branch, a second power supply branch, a third power supply branch, and a fourth power supply branch; a first protection diode CR103 and a second protection diode CR104 are connected between one end of the first power supply branch and one end of the second power supply branch. One end of the second power supply branch is connected to one end of the third power supply branch and one end of the fourth power supply branch; The other end of the first power supply branch is connected to the reference circuit, SPI circuit, and crystal oscillator circuit. The other end of the second power supply branch is connected to the SPI circuit; The other end of the third power supply branch and the other end of the fourth power supply branch are both connected to the ADC main control circuit.
[0015] In one embodiment, it further includes a communication circuit connected to the FPGA circuit.
[0016] Compared with the prior art, this application has the following advantages: the FPGA circuit can process the digital signal output by the ADC chip more accurately, analyze the dynamic and static performance test indicators of the high-speed ADC, calculate and design various parameters of the high-speed ADC, verify the frequency domain analysis (FFT) and time domain analysis of the ADC chip parameters, and meet the application requirements of the design of high-speed ADC signal acquisition circuit system. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of the FPGA-based high-speed ADC signal acquisition circuit system according to an embodiment of this application; Figure 2 This is a schematic diagram of the ADC main control circuit in the FPGA-based high-speed ADC signal acquisition circuit system according to an embodiment of this application. Figure 3 This is a schematic diagram of the FPGA circuit in the high-speed ADC signal acquisition circuit system based on FPGA according to an embodiment of this application; Figure 4 This is a schematic diagram of the crystal oscillator circuit in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment; Figure 5 This is a schematic diagram of the reference circuit in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment; Figure 6 This is a schematic diagram of the first communication branch in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment; Figure 7 This is a schematic diagram of the second communication branch in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment; Figure 8 This is a schematic diagram of the power supply circuit in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment; Figure 9 This is a schematic diagram of the external power supply circuit in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment; Figure 10 This is a schematic diagram of the communication circuit in the FPGA-based high-speed ADC signal acquisition circuit system of this application embodiment. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation", "connection" and "joining" should be interpreted broadly, for example, they can refer to fixed connection, detachable connection, or integral connection; for those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.
[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0023] Reference Figure 1 The embodiments of this application provide a high-speed ADC signal acquisition circuit system based on FPGA, including: ADC main control circuit 1, Differential double balun circuit 9, the input terminal of differential double balun circuit 9 is input with analog input signal, and the output terminal of differential double balun circuit 9 is connected to the input terminal of ADC main control circuit 1; FPGA circuit 7, the input terminal of FPGA circuit 7 is connected to the output terminal of ADC main control circuit 1; Power supply circuit 3 is connected to ADC main control circuit 1 and FPGA circuit 7.
[0024] Specifically, the ADC main control circuit 1 uses a fully integrated analog-to-digital converter (ADC) chip U2. This chip incorporates a high-performance sample-and-hold circuit and an on-chip reference voltage source, employs a multi-stage differential pipeline architecture, and features built-in output error correction logic. It provides 14-bit precision at an 80MSPS data rate and guarantees no code loss across the entire operating temperature range. This ADC chip incorporates various functionalities, using a single differential clock input to control all internal conversion cycles. The digital output data format is offset binary, Gray code, or two's complement. Each ADC channel has a data output clock (DCO) to ensure correct latching timing for the receiving logic. Output data can also be multiplexed on a single output bus. The obtained digital test codes include built-in fixed codes and pseudo-random codes, as well as user-defined test codes input via the serial port interface (SPI).
[0025] like Figure 2 As shown, the ADC chip U2 can be the SE9251. The internal circuitry of the ADC chip U2 includes the following main components: differential input buffer, high-performance sample-and-hold circuit (S / H), multi-differential pipeline architecture, DAC, SPI configuration module, differential clock input and duty cycle regulator (DCS), and on-chip reference voltage source. This ADC chip features excellent pipeline architecture and digital error correction logic to ensure 14-bit accuracy, suitable for I / Q demodulation in communication base stations; its low-power design and on-chip reference support the battery power requirements of portable medical devices; and programmable test codes and SPI configuration simplify the debugging process for radar or ultrasound equipment.
[0026] Furthermore, the ADC chip U2 provides a pipeline delay of 9 clock cycles for latching data, and the data output is available after one propagation delay (TPD) following the rising edge of the clock signal. This minimizes the length of the output data line and the applied load, thereby reducing the transients of the ADC chip that degrade its dynamic performance. The ADC chip U2 achieves this through differential driving of the analog input. For baseband applications below 10 MHz, the VCM voltage can be configured using differential dual-balun coupling to bias the analog input, achieving minimal high-frequency signal attenuation at input frequencies at the second Nyquist zone and above.
[0027] Reference Figure 2In the ADC chip U2, the AVDD pin is connected to a 1.8V analog DC voltage. The eight AVDD pins are pulled down to GND through the first filter capacitor C210, the second filter capacitor C212, the third filter capacitor C213, the fourth filter capacitor C214, the fifth filter capacitor C215, the sixth filter capacitor C216, the seventh filter capacitor C217, and the eighth filter capacitor C218 for signal filtering and decoupling. The DRVDD pin of the ADC chip U2 is connected to a 3.3V digital output drive voltage. The four DRVDD pins are pulled down to GND through the first pull-down capacitor C207, the second pull-down capacitor C208, the third pull-down capacitor C209, and the fourth pull-down capacitor C211 for signal filtering and decoupling. The SYNC pin of ADC chip U2 is connected to one end of the eleventh DC blocking capacitor C206. The SYNC synchronous input clock signal enters the SYNC pin of ADC chip U2 through the combination of the eleventh DC blocking capacitor C206 and the third pull-down resistor R207. The other end of the third pull-down resistor R207 is connected to GND.
[0028] The ADC chip U2 includes two analog input channels, channel A and channel B. The data clock output pins DCOA and DCOB of channels A and B of the ADC chip U2 are connected to the sixteenth isolation resistor R15 and the seventeenth isolation resistor R16. The other end of the isolation resistor is connected to the peripheral FPGA circuit 7 through the FMC interface to capture data in the external register.
[0029] Reference Figure 2 In this circuit, the D0A~D13A and D0B~D13B digital output pins of the ADC chip U2 are connected to one end of the eighteenth isolation resistor R17~thirty-first isolation resistor R30 and the first isolation resistor R00~fourteenth isolation resistor R13, respectively. The other end of all isolation resistors is connected to the FPGA circuit 7 through the FMC interface, which allows for the acquisition of digital signals converted from analog input signals. The resistance value of each isolation resistor is 0Ω, and the function of the 0Ω resistor is to isolate AC interference from the output signal.
[0030] The differential double balun circuit 9 is used to convert analog input signals into differential pairs of analog signals. (Continue to refer to...) Figure 2 In the differential dual balun circuit 9, two baluns are used to convert the single-ended input signal into a differential signal to match the differential input requirements of the ADC and improve the common-mode interference immunity. The single-ended signal enters the balun through a DC blocking capacitor, and a differential signal with equal amplitude and a 180° phase difference is generated through internal magnetic coupling. The back-end resistor and capacitor ensure that the common-mode voltage VCM of the differential signal matches the ADC input (ADC chip U2 has a 100Ω differential impedance), optimizing signal integrity. The balun can be of model MABA-007159-000000. The two baluns are designated as the first differential dual balun input B3 and the second differential dual balun input B4.
[0031] like Figure 2 As shown, taking analog input channel B as an example, the differential dual balun circuit 9 includes a first differential dual balun input B3. The VIP pin of the first differential dual balun input B3 is pulled down to GND through the first pull-down resistor R524 to isolate other stray signals. The analog input signal VINB reaches the VIN pin of the first differential dual balun input B3 through the first DC blocking capacitor C503, thereby blocking the DC component in the analog input signal and allowing only AC signals to enter the balun, avoiding DC bias from affecting the balun conversion performance. The first differential dual balun input B3... The VOUTP output pin of the first differential dual balun input B3 is connected to the VOUN output pin of the second differential dual balun input B4 and one end of the second DC blocking capacitor C506. The VOUTN output pin of the first differential dual balun input B3 is connected to the VIP input pin of the second differential dual balun input B4 and one end of the third DC blocking capacitor C507. The DC blocking capacitor at the output end prevents the DC component of the balun output from entering subsequent circuits, ensuring that the differential AC signal is transmitted to the ADC chip U2. The VOUP output pin of the second differential dual balun input B4 is connected to GND. The VCM pin of ADC chip U2 is connected to GND through the twelfth DC blocking capacitor C203 and the fourth DC blocking capacitor C523. The fourth DC blocking capacitor C523 is connected to one end of the second voltage divider resistor R503 and one end of the first voltage divider resistor R504. The other end of the third DC blocking capacitor C507 is connected to the other end of the second voltage divider resistor R503 and one end of the fourth voltage divider resistor R509. The other end of the second DC blocking capacitor C506 is connected to the other end of the first voltage divider resistor R504 and one end of the third voltage divider resistor R508. The resistors are connected together and form a voltage divider circuit to provide a suitable common-mode voltage VCM for the differential signal, ensuring that the differential signal is within the ADC input range, maintaining line impedance balance, and reducing signal distortion. The other end of the third voltage divider resistor R508 is connected to one end of the fifth DC blocking capacitor C510 and the VIN-B pin of the ADC chip U2, and the other end of the fourth voltage divider resistor R509 is connected to the other end of the fifth DC blocking capacitor C510 and the VIN+B pin of the ADC chip U2, thereby realizing the circuit design of single-ended to differential input signal.
[0032] The differential double balun circuit 9 for channel A of ADC chip U2 is similar to that for channel B, and will not be described in detail here.
[0033] like Figure 3 As shown, the main FPGA chip of the FPGA circuit can preferably be the Xilinx-Kintex-7 series FPGA chip XC7K325T series.
[0034] The main FPGA chip U1 of the FPGA circuit provides UART communication. The FX3_UART_RTS, FX3_UART_CTS, FX3_UART_TXD, and FX3_UART_RXD defined by the main FPGA chip U1 are connected to the communication chip U21 of the communication circuit with the same defined pins. The FPGA circuit performs data processing by completing the SPI signal interaction with the ADC chip U2 and the acquisition and buffering of the output digital signal. The FPGA serves as the control and processing core of the entire system. The ADC main control circuit realizes the acquisition and analog-to-digital conversion of data and transmits the acquired data to the FPGA circuit. The FPGA circuit performs digital filtering on the read data to remove high-frequency interference or noise and then sends the data to the PC through the interface (UART interface) to display the acquisition and analysis of the signal, thus completing the closed loop.
[0035] In one embodiment, the FPGA-based high-speed ADC signal acquisition circuit system further includes a crystal oscillator circuit 5, which is connected to the ADC main control circuit 1 and the power supply circuit 3.
[0036] Among them, such as Figure 4 As shown, the crystal oscillator circuit 5 includes an active crystal oscillator OSC1, which generates an 80MHz clock signal. The active crystal oscillator OSC1 can be of model CB3-3I-80M000000. The active crystal oscillator OSC1 mainly consists of a quartz crystal, an oscillation circuit, an amplifier circuit, a filter circuit, and a power supply circuit. The CB3-3I-80M000000 is a highly regulated, low-temperature drift, and highly interference-resistant 80MHz active crystal oscillator. It outputs TTL level and features advanced TCXO (temperature compensated crystal oscillator) technology and an extremely low temperature drift of ±10ppm.
[0037] The VCC pin of the active crystal oscillator OSC1 is connected to the power supply circuit 3; the first isolation capacitor C809 is connected to the VCC pin to block DC signals; the OUT pin of OSC1 is connected to the 0Ω first isolation resistor R815, which, together with the equivalent capacitance of the internal output terminal of the active crystal oscillator OSC1, can form an RC integrator circuit to reduce harmonic interference and limit it; the GND pin of OSC1 is connected to GND; the OE pin of OSC1 is connected to the first pull-down resistor R814, and the other end of the first pull-down resistor R814 is connected to GND; the OE pin can also be jumpered to AVDD3.3V.
[0038] The clock circuit primarily performs impedance matching, shaping, and filtering of external clock signals to provide the ADC chip with a low-jitter, low-phase-noise clock signal. This signal can be provided by a clock generator or an on-board crystal oscillator. The VIN signal uses a MABA-007159-000000 differential dual balun input, while the clock signal generated by the 80MHz crystal oscillator is transmitted to the SE9251.
[0039] In one embodiment, the FPGA-based high-speed ADC signal acquisition circuit system further includes a reference circuit 2, which is connected to the ADC main control circuit 1 and the power supply circuit 3.
[0040] Among them, such as Figure 5 As shown, the reference circuit 2 includes: a reference chip U201, the IN pin of the reference chip U201 is connected to the first power supply branch output terminal AVDD3.3V of the power supply circuit 33 through one end of the first filter capacitor C201, and the other end of the first filter capacitor C201 is connected to GND, which serves as decoupling to filter out high-frequency noise and ripple at the power input terminal and ensure the stability of the reference voltage output by the reference chip U201; the OUT pin of the reference chip U201 is connected to the VREF of the ADC chip U2 through one end of the second filter capacitor C202, which is used to provide an external reference source for the ADC chip U2, and the other end of the second filter capacitor C202 is connected to GND, which filters the output reference voltage, suppresses high-frequency noise and provides a more stable and low-noise input reference voltage for the ADC chip; the SET pin of the reference chip U201 is connected to one end of the first pull-up resistor R201 and one end of the first isolation resistor R202, the other end of the first pull-up resistor R201 is connected to the AVDD3.3V of the power supply circuit 3, and the other end of the first isolation resistor R202 is connected to GND.
[0041] Among them, the reference chip U201 can be ADR130. ADR130 is a high-precision and anti-interference reference voltage source that provides a stable, low-noise, and high-precision (0.35%) voltage source for the ADC chip, ensuring the accuracy and consistency of digital-to-analog conversion. It has advanced temperature drift curvature correction technology and an extremely low temperature drift of ±25ppm, minimizing the nonlinearity of the output voltage and temperature characteristic curve.
[0042] Continue to refer to Figure 2The connection between ADC chip U2 and reference circuit 2 includes: the digital input OEB pin of ADC chip U2 is connected to one end of the fourth pull-down resistor R208, and the other end of the fourth pull-down resistor R208 is connected to GND; the digital input PDWN pin of ADC chip U2 is connected to one end of the fifth pull-down resistor R209, and the other end of the fifth pull-down resistor R209 is connected to GND; the OEB and PDWN pins of ADC chip U2 are active low, enabling the digital output of channels A and B; the reference voltage VREF pin of ADC chip U2 is connected to chip U201 of reference circuit 2 through the fifth pull-down capacitor C204 and the sixth pull-down capacitor C205, and the other ends of the fifth pull-down capacitor C204 and the sixth pull-down capacitor C205 are connected to GND, achieving decoupling of the reference voltage; the reference mode SENSE pin of ADC chip U2 can switch different reference modes. If the SENSE pin is grounded, the reference amplifier switch is connected to the internal resistor divider, internally setting VREF to 1.0. When the SENSE pin is connected to AVDD, the internal reference voltage is disabled, allowing the use of an external reference voltage. The analog input common-mode VCM pin of ADC chip U2 is connected to GND through the twelfth DC blocking capacitor C203, which has the function of decoupling and blocking DC for the signal; the analog current bias RBIAS pin of ADC chip U2 is connected to GND through the seventh pull-down resistor R206, which is used to set the main reference current of the ADC core.
[0043] The Serial Port Interface (SPI) of the ADC chip U2 allows users to configure the corresponding internal function registers of the ADC to meet specific functional and operational needs. The serial port allows access to and reading from the address space. The SPI of the ADC chip U2 consists of three parts: the SCLK pin, the SDIO pin, and the CSB pin. The SCLK (Serial Clock) pin is used to synchronize the ADC's read and write data; the SDIO (Serial Data Input / Output) dual-function pin allows data to be sent to or read from internal registers; the CSB (Chip Select) pin is an active-low control pin that enables or disables read / write cycles.
[0044] Furthermore, SPI (Serial Peripheral Interface) is a full-duplex communication protocol based on synchronous timing, commonly used for communication between chips. Typically, the SPI protocol consists of four signal lines: clock line SCK, chip select signal line CS, master-in-slave-out line MISO, and master-out-slave-in line MOSI. The clock line SCK is output by the master device and is used to drive data transmission from the slave device; the chip select signal line CS is output by the master device and is used to select the slave device to communicate with; the master-in-slave-out line MISO is output by the slave device and is used to return data to the master device; and the master-out-slave-in line MOSI is output by the master device and is used to send data to the slave device. Important aspects of FIFO read / write control include: only after the FIFO has stored data to its upper limit does it send a request to the host computer, i.e., a DMA data transfer request. Reading data from the FIFO and simultaneously transferring it to the host computer requires the FPGA to receive a DMA data transfer command from the host computer. Verify that the system can correctly acquire, process, and display ADC data by observing data on the display device or using tools such as a logic analyzer to check the operating status of the internal modules of the FPGA. Test input signals of different frequencies and amplitudes to check whether the acquired data accurately reflects the characteristics of the input signal.
[0045] In one embodiment, the FPGA-based high-speed ADC signal acquisition circuit system further includes an SPI circuit 4, which is connected to the ADC main control circuit 6 and the FPGA circuit 7 respectively. The SPI circuit 4 includes a first communication branch and a second communication branch. The first communication branch transmits data signals, and the second communication branch transmits clock signals and chip select signals.
[0046] Among them, such as Figure 6As shown, the first communication branch includes: a first SPI chip U301; the VCC pin of the first SPI chip U301 is connected to the output terminal DVDD of the second power supply branch of the power supply circuit 33, and is connected to GND through the first pull-down capacitor C301; the Y1 pin of the first SPI chip U301 is connected through the first pull-up resistor R310 and the first impedance resistor R311, the other end of the first pull-up resistor R310 is connected to DVDD, and the other end of the first impedance resistor R311 is connected to SDIO_DUT; the Y2 pin of the first SPI chip U301 is defined as US B_SDO is connected to the first power supply branch output terminal AVDD3.3V of the power supply circuit 33 through the second pull-up resistor R312; the A1 pin of the first SPI chip U301 is defined as USB_SDI, and is connected to GND through the first pull-down resistor R309. The A1 pin is connected to the peripheral FPGA circuit 7 through the FMC interface, and can transmit SPI signals; the A2 pin of the first SPI chip U301 is defined as SDIO_DUT, and is pulled down to GND through the second pull-down resistor R313. The A2 pin can perform SPI master-slave mode interaction.
[0047] Among them, the first SPI chip U301 transmits data signals, and the USB_SDI (FPGA circuit output) signal can be driven to SDIO_DUT (ADC chip input) through U301. At the same time, the SDIO_DUT signal can also be fed back to USB_SDO (FPGA circuit input) through U301 to realize full-duplex communication.
[0048] Among them, such as Figure 7 As shown, the second communication branch includes: a second SPI chip U302, whose VCC pin is connected to the output terminal DVDD of the second power supply branch of the power supply circuit 33, and connected to GND through the second pull-down capacitor C302; the Y1 pin of the second SPI chip U302 is defined as SCLK_DUT, and connected to GND through the fifth pull-down resistor R315; the Y2 pin of the second SPI chip U302 is defined as CSB_DUT, and connected to the output terminal DVDD of the second power supply branch of the power supply circuit 33 through the third pull-up resistor R314; the A1 pin of the second SPI chip U302 is defined as USB_SCLK, and connected to GND through the third pull-down resistor R316. The A1 pin is connected to the peripheral FPGA circuit 7 through the FMC interface, and can transmit SPI signals; the A2 pin of the second SPI chip U302 is defined as USB_CSB, and pulled down to GND through the fourth pull-down resistor R317. The A2 pin can perform SPI master-slave mode interaction.
[0049] The second SPI chip U302 transmits clock (USB_SCLK) and chip select (USB_CSB) signals. Through an internal mechanism, it drives the clock and chip select signals from the USB end to the ADC end (SCLK_DUT, CSB_DUT), ensuring timing synchronization and chip select control in master-slave mode, and synchronously realizing full-duplex communication.
[0050] Among them, the first pull-down resistor R309, the second pull-down resistor R313, the third pull-down resistor R316, and the fourth pull-down resistor R317 pull the signal to a low level by default to avoid floating noise and ensure signal stability; the first pull-up resistor R310, the second pull-up resistor R312, and the third pull-up resistor R314 pull the signal to a high level by default to ensure the correct initial state of the circuit; the SPI circuit 4 realizes the SPI communication between the USB terminal (FPGA circuit 7) and the DUT (ADC chip). The FPGA circuit 7 sends data through USB_SDI, which is transmitted to SDIO_DUT (ADC chip) via the first SPI chip U301. The ADC chip returns data through SDIO_DUT, which is transmitted to USB_SDO (FPGA circuit 7) via the first SPI chip U301. The FPGA circuit 7 provides a clock through USB_SCLK, which is transmitted to SCLK_DUT via the second SPI chip U302 to synchronize the data transmission timing. The FPGA circuit 7 controls the chip select through USB_CSB, which is transmitted to CSB_DUT via the second SPI chip U302 to control the ADC chip. Through the above mechanism, SPI circuit 4 ensures the correct driving, switching and level stability of SPI signals, realizing high-speed and reliable full-duplex communication between master and slave devices.
[0051] As a preferred option, the first SPI chip U301 can be an NC7WZ07P6X (dual-channel ultra-high-speed open-drain buffer), and the second SPI chip U302 can be an NC7WZ16 (hex inverter gate chip). NC7WZ07P6X and NC7WZ16 are buffered transceivers that assist SPI communication through signal conditioning, buffering the signal and enhancing the driving capability. They also reduce interference through internal noise reduction circuitry to ensure stable signal transmission. The NC7WZ07P6X open-drain buffer enhances signal drive capability (output drive ±32mA), reduces signal attenuation and noise interference during transmission, and is especially suitable for SPI signal (such as SDIO_DUT) transmission in long-distance or high-noise environments, ensuring data integrity. Its internal EMI / noise reduction circuit can filter high-frequency noise to avoid interference affecting the timing and data accuracy of SPI communication. The NC7WZ16 inverter shapes SPI signals (such as USB_CSB), improves signal edge quality, enhances drive capability (±24mA), and avoids communication errors caused by signal distortion.
[0052] Continue to refer to Figure 2 The connection between the ADC master control circuit 1 and the SPI circuit 4 includes: the SPI data input and output SDIO / DCS pins of the ADC chip U2 are connected to the 33rd isolation resistor R301; the SPI clock input SCLK / DFS pin of the ADC chip U2 is connected to the 34th isolation resistor R302; and the SPI mode selection CSB pin of the ADC chip U2 is connected to the 35th isolation resistor R303. The other ends of the 33rd, 34th, and 35th isolation resistors R301, R302, and R303 are connected to the first SPI chip U301 and the second SPI chip U302 of the SPI circuit 4. When the ADC chip needs to fully utilize its full dynamic performance, the SPI port should be disabled. Usually, the SCLK, CSB, and SDIO signals are asynchronous with the ADC clock, and noise in these signals will degrade the converter performance. If the on-board SPI bus is used, a buffer needs to be connected between the bus and the ADC chip to prevent these signals from changing at the input during critical sampling periods.
[0053] In one embodiment, the power supply circuit 3 includes a first power supply branch, a second power supply branch, a third power supply branch, and a fourth power supply branch; a first protection diode CR103 and a second protection diode CR104 are connected between one end of the first power supply branch and one end of the second power supply branch. One end of the second power supply branch is connected to one end of the third power supply branch and one end of the fourth power supply branch; The other end of the first power supply branch is connected to the reference circuit 2, the SPI circuit 4, and the crystal oscillator circuit 5. The other end of the second power supply branch is connected to SPI circuit 4; The other end of the third power supply branch and the other end of the fourth power supply branch are both connected to the ADC main control circuit 1.
[0054] Among them, such as Figure 8 As shown, the first power supply branch, the second power supply branch, the third power supply branch, and the fourth power supply branch have the same structure.
[0055] The first power supply branch includes: a first LDO chip U101; the VIN and EN pins of the first LDO chip U101 are connected to the first filter capacitor C104, the second filter capacitor C103, and the first protection diode CR103; the other ends of the first filter capacitor C104 and the second filter capacitor C103 are connected to GND; the other end of the first protection diode CR103 is connected to the second protection diode CR104; the VOUT pin of the first LDO chip U101 is connected to the first output resistor R102, the first output capacitor C102, and the first filter bead E101; the other end of the first output capacitor C102 is connected to GND; the other end of the first output resistor R102 is connected to the second output resistor R103 and the ADJ pin of the first LDO chip U101; the other end of the second output resistor R103 is connected to GND; and the other end of the first filter bead E101 (AVDD 3.3V) is connected to the reference circuit 2, the SPI circuit 4, and the crystal oscillator circuit 5.
[0056] The second power supply branch includes: a second LDO chip U102, whose VIN and EN pins are connected to the third filter capacitor C107, the fourth filter capacitor C106, and the second protection diode CR104; the other ends of the third filter capacitor C107 and the fourth filter capacitor C106 are connected to GND; the VOUT pin of the second LDO chip U102 is connected to the third output resistor R104, the second output capacitor C105, and the second filter bead E102; the other end of the second output capacitor C105 is connected to GND; the other end of the third output resistor R104 is connected to the fourth output resistor R105 and the ADJ pin of the second LDO chip U102; the other end of the fourth output resistor R105 is connected to GND; and the other end DVDD of the second filter bead E102 is connected to SPI circuit 4. The third power supply branch includes: a third LDO chip U103, whose VIN and EN pins, along with the fifth filter capacitor C109 and the sixth filter capacitor C110, are connected to the VIN pin of the second LDO chip U102; the other ends of the fifth filter capacitor C109 and the sixth filter capacitor C110 are connected to GND; the VOUT pin of the third LDO chip U103 is connected to the fifth output resistor R106, the third output capacitor C108, and the third filter bead E103; the other end of the third output capacitor C108 is connected to GND; the other end of the fifth output resistor R106 is connected to the sixth output resistor R107 and the ADJ pin of the third LDO chip U103; the other end of the sixth output resistor R107 is connected to GND; and the other end of the third filter bead E103, AVDD, is connected to the ADC main control circuit 1.
[0057] The fourth power supply branch includes: similar to the third power supply branch, the other end of the fourth filter bead E104 in the fourth power supply branch, DRVDD, is connected to the ADC main control circuit 1.
[0058] Understandably, power supply circuit 3 is connected to external power supply circuit 9. For example... Figure 9 As shown, the external power supply circuit 9 is powered through an EMI filter module. The V of the external power supply circuit 9... IN The pin is connected to power supply circuit 3. This EMI filter module design can not only stabilize the +5V power supply, but also filter out high-frequency noise.
[0059] Specifically, the external power supply circuit includes a first filter capacitor C101, a first fuse F101, a first protection diode CR101, a first EMI filter FL101, a first light-emitting diode LED, and a first current-limiting resistor R101. The first filter capacitor C101 is connected to the first fuse F101, and the other end is connected to GND. The other end of the first fuse F101 is connected to the B pin of the first protection diode CR101 and the first EMI filter FL101. The other end of the first protection diode CR101 is connected to the PSG pin of the first EMI filter FL101 and then to GND. The CG pin of the first EMI filter FL101 is connected to GND, and the CB pin (VIN) of the first EMI filter FL101 is connected to the power supply circuit 3 to supply power to the subsequent modules.
[0060] As a preferred option, the first EMI filter FL101 is model BNX016-01. The BNX016-01 is a dual-channel 5th-order EMI filter with ESD protection. Internally, it employs a 5th-order filtering network (RC+LC network) composed of resistors, capacitors, and other components, which can more sharply attenuate signals above the cutoff frequency. High-frequency noise (such as electromagnetic interference signals) is significantly attenuated after entering the stopband, thus achieving frequency filtering of the input signal. The BNX016-01 5th-order filtering module achieves strong electromagnetic interference suppression (EMI) of high-frequency signals through a high-order filtering network, playing a crucial role in suppressing electromagnetic interference and purifying signals, thereby improving the circuit's anti-interference capability and stability.
[0061] In one embodiment, the FPGA-based high-speed ADC signal acquisition circuit system further includes a communication circuit 6, which is connected to the FPGA circuit 7.
[0062] like Figure 10As shown, the communication circuit 6 includes a communication chip U21. The IA0, IB0, IC0, and ID0 pins of the communication chip U21 are all connected to the peripheral FPGA circuit 7, serving as signal pins for the input channel IX0. These pins are connected to the UART signals of the FX3 chip (FX3_UART_RTS, FX3_UART_CTS, FX3_UART_TXD, and FX3_UART_RXD), respectively, as the UART signal input path. The VCC pin of the communication chip U21 is connected to the peripheral FPGA circuit 7 through a first filter capacitor C195. The other end of the first filter capacitor C195 is connected to GND. The SEL pin is connected to the peripheral FPGA circuit 7 via the first current-limiting resistor R131. The IA1, IB1, IC1, and ID1 pins of the communication chip U21 are signal pins of the input channel IX1, which are connected to the SPI signals of FX3 (FX3_SPI_SCK, FX3_SPI_SSN, FX3_SPI_MISO, and FX3_SPI_MOSI) as SPI signal input paths, respectively. The YA, YB, YC, and YD pins of the communication chip U21 are output pins, all of which are connected to the peripheral FPGA circuit 7 and to FPGA pins such as FX3_GPIO53 and FX3_GPIO54, to output the selected input signal (UART or SPI) to the FPGA, ensuring that the signals on the bus can be correctly received and transmitted.
[0063] The communication chip U21 switches the signal path by selecting the active input channel (IX0 or IX1) through the control signal SEL. When SEL=0, the output YX is connected to the input channel IX0; when SEL=1, the output YX is connected to the input channel IX1. The communication chip U21 can switch between UART and SPI signals, allowing the FPGA to select different communication interfaces as needed, optimizing hardware resource utilization and enhancing circuit flexibility.
[0064] The high-speed ADC signal acquisition circuit system based on FPGA provided in this application inputs analog input signals to the VIN+A, VIN-A, VIN+B, and VIN-B pins of the ADC chip U2 via a differential double balun circuit 9. The two A and B signal output terminals of the ADC chip U2 are connected to the FPGA circuit 7, used to output and acquire converted digital signals from the analog signals input to the ADC chip U2. The analog input signals include independent first and second analog input signals, both of which are input to the ADC main control circuit 1 via the differential double balun circuit 9. The two differential pairs of VINA_P, VINA_N, VINB_P, and VINB_N analog signals are converted from analog to digital by the ADC chip U2, outputting independent first and second digital signals, which are then connected to the FPGA circuit 7 via the FMC interface. Thus, the FPGA chip acquires the digital signals converted by the ADC.
[0065] Reference circuit 2 is connected to ADC main control circuit 1 and power supply circuit 3 to realize the reference configuration of VREF pin of ADC chip U2, so that the internal comparator can detect the voltage value of SENSE pin; crystal oscillator circuit 5 is connected to ADC main control circuit 1 to provide 80MHz CLOCK signal; power supply circuit 3 is connected to ADC main control circuit 1, reference circuit 2, SPI circuit 4 and crystal oscillator circuit 5 to provide power. Power supply circuit 3 is connected to external power supply circuit 8.
[0066] The SPI circuit 4 is connected to the ADC master control circuit 1 and the FPGA circuit 7 for master-slave SPI communication transmission, realizing the communication interaction between the ADC chip U2 and the FPGA circuit 7. The first SPI chip U301 transmits data signals (USB_SDI, SDIO_OUT, USB_SDO), and the second SPI chip U302 transmits clock signals (USB_SCLK) and chip select signals (USB_CSB).
[0067] The high-speed ADC signal acquisition circuit system based on FPGA provided in this application can more accurately process the digital signal output by the ADC chip by using FPGA circuit 7, analyze the dynamic and static performance functional test indicators of the high-speed ADC, calculate and design various parameters of the high-speed ADC, and verify the frequency domain analysis (FFT) and time domain analysis of the ADC chip parameters, thus meeting the application requirements for the design of a high-speed ADC signal acquisition circuit system.
[0068] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A high-speed ADC signal acquisition circuit system based on FPGA, characterized in that, include: ADC main control circuit (1); A differential double balun circuit (9) is provided, wherein an analog input signal is input to the input terminal of the differential double balun circuit (9), and the output terminal of the differential double balun circuit (9) is connected to the input terminal of the ADC main control circuit (1). FPGA circuit (7), the input terminal of the FPGA circuit (7) is connected to the output terminal of the ADC main control circuit (1); The power supply circuit (3) is connected to the ADC main control circuit (1) and the FPGA circuit (7).
2. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 1, characterized in that, Also includes: Crystal oscillator circuit (5), which is connected to the ADC main control circuit (1) and the power supply circuit (3).
3. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 2, characterized in that, The crystal oscillator circuit (5) includes: an active crystal oscillator OSC1, which is used to generate an 80MHz clock signal; The VCC pin of the active crystal oscillator OSC1 is connected to the power supply circuit (3); the VCC pin of the active crystal oscillator OSC1 is also connected to one end of the first isolation capacitor C809, and the other end of the first isolation capacitor C809 is grounded; the OUT pin of the active crystal oscillator OSC1 is connected to the first isolation resistor R815; the OE pin of the active crystal oscillator OSC1 is connected to one end of the first pull-down resistor R814, and the other end of the first pull-down resistor R814 is connected to GND; the GND pin of the active crystal oscillator OSC1 is connected to GND.
4. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 2, characterized in that, Also includes: The reference circuit (2) is connected to the ADC main control circuit (1) and the power supply circuit (3).
5. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 4, characterized in that, The reference circuit (2) includes: a reference chip U201; the IN pin of the reference chip U201 is connected to the power supply circuit (3) through one end of the first filter capacitor C201; the other end of the first filter capacitor C201 is connected to GND; the OUT pin of the reference chip U201 is connected to the ADC main control circuit (1) through one end of the second filter capacitor C202; the other end of the second filter capacitor C202 is connected to GND; the SET pin of the reference chip U201 is connected to one end of the first pull-up resistor R201 and one end of the first isolation resistor R202, the other end of the first pull-up resistor R201 is connected to the power supply circuit (3), and the other end of the first isolation resistor R202 is connected to GND.
6. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 4, characterized in that, Also includes: The SPI circuit (4) is connected to the ADC main control circuit (1) and the FPGA circuit (7) respectively. The SPI circuit (4) includes a first communication branch and a second communication branch. The first communication branch transmits data signals, and the second communication branch transmits clock signals and chip select signals.
7. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 6, characterized in that, The first communication branch includes: a first SPI chip U301; the VCC pin of the first SPI chip U301 is connected to the power supply circuit (3) and connected to GND through the first pull-down capacitor C301; the Y1 pin of the first SPI chip U301 is connected to one end of the first pull-up resistor R310 and one end of the first impedance resistor R311, the other end of the first pull-up resistor R310 is connected to DVDD, and the other end of the first impedance resistor R311 is connected to SDIO_DUT; the Y2 pin of the first SPI chip U301 is defined as USB_SDO and is connected to the power supply circuit (3) through the second pull-up resistor R312; the A1 pin of the first SPI chip U301 is defined as USB_SDI and is connected to GND through the first pull-down resistor R309, and the A1 pin is connected to the FPGA circuit (7) through the FMC interface; the A2 pin of the first SPI chip U301 is defined as SDIO_DUT and is pulled down to GND through the second pull-down resistor R313.
8. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 7, characterized in that, The second communication branch includes: a second SPI chip U302, the VCC pin of the second SPI chip U302 is connected to the power supply circuit (3), and is connected to GND through the second pull-down capacitor C302; the Y1 pin of the second SPI chip U302 is defined as SCLK_DUT, and is connected to GND through the fifth pull-down resistor R315; the Y2 pin of the second SPI chip U302 is defined as CSB_DUT, and is connected to the power supply circuit (3) through the third pull-up resistor R314; the A1 pin of the second SPI chip U302 is defined as USB_SCLK, and is connected to GND through the third pull-down resistor R316, and the A1 pin is connected to the FPGA circuit (7) through the FMC interface; the A2 pin of the second SPI chip U302 is defined as USB_CSB, and is pulled down to GND through the fourth pull-down resistor R317.
9. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 6, characterized in that, The power supply circuit (3) includes a first power supply branch, a second power supply branch, a third power supply branch and a fourth power supply branch; a first protection diode CR103 and a second protection diode CR104 are connected between one end of the first power supply branch and one end of the second power supply branch; One end of the second power supply branch is connected to one end of the third power supply branch and one end of the fourth power supply branch; The other end of the first power supply branch is connected to the reference circuit (2), the SPI circuit (4), and the crystal oscillator circuit (5); The other end of the second power supply branch is connected to the SPI circuit (4); The other end of the third power supply branch and the other end of the fourth power supply branch are both connected to the ADC main control circuit (1).
10. The FPGA-based high-speed ADC signal acquisition circuit system according to claim 1, characterized in that, Also includes: The communication circuit (6) is connected to the FPGA circuit (7).