Solar cells and photovoltaic modules

Abstract

This application discloses a solar cell and a photovoltaic module, relating to the field of photovoltaic technology. The solar cell includes a cell substrate and grid lines disposed on the cell substrate. The cell substrate includes a silicon substrate, a doped polycrystalline silicon layer, and a passivation layer, which are stacked. Grid line grooves are formed on the passivation layer, with the bottom of the grid line grooves exposing the doped polycrystalline silicon layer. At least a portion of the edge of the passivation layer adjacent to the grid line groove is warped away from the doped polycrystalline silicon layer to form a warped portion. The grid lines cover and fill the grid line grooves. In the solar cell of this application embodiment, the warped edge of the passivation layer forms a warped portion. On the one hand, this widens the bottom area of ​​the grid line groove, which helps to reduce the contact resistance between the grid lines and the doped polycrystalline silicon layer; on the other hand, it can improve the bonding strength between the grid lines and the cell substrate, reducing the risk of grid line detachment.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and more specifically, to a solar cell and a photovoltaic module. Background Technology

[0002] With the increasing cost of metallization in solar cells, reducing this cost has become a major trend. Copper grid lines possess low resistivity. Unlike the silver electrode sintering process, achieving good contact between the copper grid lines and the cell substrate requires laser-driven trenching in the passivation layer of the substrate to expose a doped polysilicon layer, followed by connecting the grid lines to the exposed doped polysilicon layer. However, in existing solar cells, the bonding strength between the grid lines and the substrate is poor, and the contact resistance is high, which affects the efficiency of the solar cell. Utility Model Content

[0003] The purpose of this application is to provide a solar cell and a photovoltaic module in which the grid lines have better bonding force and lower contact resistance with the cell substrate, thereby ensuring that the solar cell has better efficiency.

[0004] The embodiments of this application can be implemented as follows:

[0005] In a first aspect, this application provides a solar cell, including a cell substrate and grid lines disposed on the cell substrate. The cell substrate includes a silicon substrate, a doped polycrystalline silicon layer and a passivation layer. The doped polycrystalline silicon layer and the passivation layer are stacked. A grid line groove is formed on the passivation layer. The bottom of the grid line groove exposes the doped polycrystalline silicon layer. At least a portion of the edge of the passivation layer adjacent to the grid line groove is warped away from the doped polycrystalline silicon layer to form a warped portion. The grid lines cover and fill the grid line groove.

[0006] In an optional embodiment, the warped portion is attached to the surface of the grid line groove that is away from the grid line groove.

[0007] In an optional embodiment, the warpage angle of the warped portion relative to the doped polysilicon layer is 5° to 50°.

[0008] In an optional embodiment, the warped portion extends to the gate slot opening by a length of 50 nm to 2000 nm.

[0009] In an optional embodiment, the projected area of ​​the warped portion on the doped polysilicon layer accounts for 3% to 10% of the bottom area of ​​the gate trench.

[0010] In an optional embodiment, the warp height of the warp portion in the direction perpendicular to the doped polysilicon layer is 50 nm to 500 nm.

[0011] In an optional implementation, the area of ​​the doped polysilicon layer exposed at the bottom of the gate trench is a strip-shaped area, and the extension direction is consistent with the extension direction of the gate line.

[0012] Alternatively, the area of ​​the doped polysilicon layer exposed at the bottom of the gate trench is a series of continuous or discontinuous circular regions, which are arranged along the extension direction of the gate line.

[0013] Alternatively, the area of ​​the doped polysilicon layer exposed at the bottom of the gate trench is a series of discontinuous square regions, which are arranged along the extension direction of the gate lines.

[0014] In an optional embodiment, the area of ​​the doped polysilicon layer exposed at the bottom of the gate trench has a dimension of 5 μm to 30 μm in the width direction of the gate line.

[0015] In an optional embodiment, the surface of the doped polysilicon layer at the bottom of the gate trench has several protrusion structures.

[0016] In an optional embodiment, the height of the protrusion structure in the direction perpendicular to the doped polysilicon layer is 10 nm to 100 nm, and the width of the protrusion structure in the direction parallel to the doped polysilicon layer is 10 nm to 100 nm.

[0017] In an optional implementation, the total projected area of ​​all the protruding structures at the bottom of the grid groove accounts for 30% to 80% of the total area at the bottom of the grid groove.

[0018] In an optional embodiment, the gate line includes a barrier layer and a conductive layer, the conductive layer being disposed on the side of the barrier layer opposite to the doped polysilicon layer.

[0019] In an optional embodiment, the doped polysilicon layer includes an n-type doped polysilicon layer and a p-type doped polysilicon layer disposed on the back side of the silicon substrate. The n-type doped polysilicon layer and the p-type doped polysilicon layer are alternately distributed in a direction parallel to the silicon substrate, and the n-type doped polysilicon layer and the p-type doped polysilicon layer are separated by an isolation trench.

[0020] The passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer covers the surfaces of the n-type doped polysilicon layer and the p-type doped polysilicon layer, as well as the inner wall of the isolation trench. The gate trench is formed in the first passivation layer, and the second passivation layer covers the front side of the silicon substrate.

[0021] Secondly, this application provides a photovoltaic module, including the solar cell of any of the foregoing embodiments.

[0022] The beneficial effects of the solar cells and photovoltaic modules provided in this application include:

[0023] The solar cell provided in this application embodiment includes a cell substrate and grid lines disposed on the cell substrate. The cell substrate includes a silicon substrate, a doped polycrystalline silicon layer, and a passivation layer. The doped polycrystalline silicon layer and the passivation layer are stacked. Grid line grooves are formed on the passivation layer, with the bottom of the grid line grooves exposing the doped polycrystalline silicon layer. At least a portion of the edge of the passivation layer adjacent to the grid line groove is warped away from the doped polycrystalline silicon layer to form a warped portion. The grid lines cover and fill the grid line grooves. In the solar cell of this application embodiment, the edge of the passivation layer is warped to form a warped portion. On the one hand, the gap formed between the warped portion and the doped polycrystalline silicon layer widens the bottom area of ​​the grid line groove, thereby providing a larger contact area between the grid lines and the doped polycrystalline silicon layer, which is beneficial for reducing the contact resistance between the grid lines and the doped polycrystalline silicon layer. On the other hand, due to the warping, the cross-sectional profile of the grid groove resembles a dovetail shape. When the grid groove is filled with grid lines, the gap below the warping, as part of the grid groove space, is also filled by the grid lines. The warping effectively prevents the grid lines from detaching away from the doped polycrystalline silicon layer, thereby improving the bonding strength between the grid lines and the cell substrate and reducing the risk of grid line detachment. Therefore, the embodiments of this application improve the reliability and conductivity of the grid lines by improving the morphology of the grid groove, thereby ensuring that the solar cell has better reliability and cell efficiency.

[0024] The photovoltaic modules provided in this application include the aforementioned solar cells, and therefore also have the advantages of high reliability and high cell efficiency. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a partial schematic diagram of the battery substrate in one embodiment of this application;

[0027] Figure 2 This is a schematic diagram of grid lines being disposed on a battery substrate in one embodiment of this application;

[0028] Figure 3 This is a scanning electron microscope image (without grid lines) of the warped portion of the passivation layer in one embodiment of this application.

[0029] Figure 4 This is a scanning electron microscope image (with grid lines) of a portion of a solar cell in one embodiment of this application.

[0030] Figure 5 This is a scanning electron microscope image of the surface of the battery substrate in one embodiment of this application;

[0031] Figure 6 This is a partial cross-sectional view of a solar cell according to one embodiment of this application.

[0032] Icons: 100 - Battery substrate; 110 - Silicon substrate; 120 - Doped polysilicon layer; 121 - n-type doped polysilicon layer; 122 - p-type doped polysilicon layer; 123 - Protrusion structure; 130 - Passivation layer; 131 - First passivation layer; 132 - Second passivation layer; 133 - Gate trench; 134 - Warp portion; 140 - Tunneling oxide layer; 150 - Isolation trench; 200 - Gate line. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the utility model product is usually placed in during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0037] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0038] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0039] In related technologies, infrared or green lasers are used to create grid grooves on the passivation layer of the battery substrate, partially removing the passivation layer to expose the underlying doped polysilicon layer. Then, grid lines are fabricated on the battery substrate, covering the grid grooves. In these technologies, the adhesion between the grid lines and the battery substrate mainly comes from three aspects: first, the adhesion force (tensile stress) between the grid lines and the doped polysilicon layer at the bottom of the grid groove; second, the adhesion force (shear stress) between the grid lines and the sidewalls of the grid groove (formed by the edge of the passivation layer); and third, the adhesion force (tensile stress) between the grid lines and the outer surface of the passivation layer. In this case, the grid line reliability is still not good enough, and grid detachment is prone to occur. Furthermore, the opening and bottom width of the grid groove are roughly the same, resulting in a limited contact area between the bottom of the grid groove and the grid lines, making it difficult to further reduce the contact resistance.

[0040] To address the issues of poor grid line reliability and high contact resistance in the aforementioned related technologies, embodiments of this application provide a solar cell and a photovoltaic module. By warping the edges of the barrier layer, the bottom area of ​​the grid line slots is widened, which helps to reduce contact resistance. The grid lines cover and fill the grid line slots, with some grid lines located below the warped portion. Therefore, the bonding strength between the grid lines and the cell substrate is high, and they are not easily detached. Furthermore, embodiments of this application also provide a photovoltaic module including the aforementioned solar cell.

[0041] Figure 1 This is a partial schematic diagram of the battery substrate 100 in one embodiment of this application; Figure 2 This is a schematic diagram showing the grid lines 200 disposed on the battery substrate 100 in one embodiment of this application. Figure 1 and Figure 2 As shown, the solar cell provided in this application embodiment includes a cell substrate 100 and grid lines 200 disposed on the cell substrate 100. The cell substrate 100 includes a silicon substrate 110, a doped polycrystalline silicon layer 120 and a passivation layer 130. The doped polycrystalline silicon layer 120 and the passivation layer 130 are stacked. A grid line groove 133 is formed on the passivation layer 130. The bottom of the grid line groove 133 exposes the doped polycrystalline silicon layer 120. At least a portion of the edge of the passivation layer 130 adjacent to the grid line groove 133 is warped away from the doped polycrystalline silicon layer 120 to form a warped portion 134. The grid lines 200 cover and fill the grid line groove 133.

[0042] Figure 3 This is a scanning electron microscope image (without grid lines 200) of the warped portion 134 of the passivation layer 130 in one embodiment of this application. Figure 4 This is a scanning electron microscope (SEM) image (with grid lines 200) of a portion of a solar cell in one embodiment of this application. Combined with... Figures 1 to 4Because the warped portion 134 at the edge of the passivation layer 130 tilts upwards, the gate groove 133 becomes a groove structure with a bottom larger than the opening, and the cross-sectional profile of the gate groove 133 is similar to a dovetail shape. Therefore, when the gate groove 133 is filled with gate lines 200, the gap below the warped portion 134, as part of the space of the gate groove 133, is also filled by the gate lines 200; that is, a portion of the gate lines 200 is embedded in the gap between the warped portion 134 and the doped polysilicon layer 120 along a direction parallel to the doped polysilicon layer 120. The warped portion 134 can effectively prevent the gate lines 200 from detaching in a direction away from the doped polysilicon layer 120, thereby improving the bonding strength between the gate lines 200 and the battery substrate 100 and reducing the risk of the gate lines 200 falling off. Furthermore, the gap formed between the warped portion 134 and the doped polysilicon layer 120 widens the bottom area of ​​the gate groove 133, thereby giving the gate line 200 and the doped polysilicon layer 120 a larger contact area, which helps to reduce the contact resistance between the gate line 200 and the doped polysilicon layer 120.

[0043] In this embodiment, the warped portion 134, facing away from the surface of the doped polysilicon layer 120, is bonded to the gate line 200. Specifically, the surface of the warped portion 134 facing away from the doped polysilicon layer 120 is completely covered by the gate line 200. Furthermore, the non-warped portion of the passivation layer 130 is bonded to the doped polysilicon layer 120, and the gate line 200 is also bonded to the outer surface of the non-warped portion of the passivation layer 130.

[0044] Optionally, the warp angle A of the warp portion 134 relative to the doped polysilicon layer 120 is 5° to 50°, for example, any value among 5°, 10°, 20°, 30°, 40°, and 50°, or a value between any two points. Optionally, the warp angle A is 8° to 25°. It should be understood that if the warp angle of the warp portion 134 is too large, it means that more laser energy is required, and more laser energy can easily damage the doped polysilicon layer 120. Furthermore, if the warp angle of the warp portion 134 is too large, its blocking ability for the gate line 200 is weakened, which is also not conducive to improving the bonding strength between the gate line 200 and the doped polysilicon layer 120. Conversely, if the warp angle of the warp portion 134 is too small, the gate line 200 will have difficulty penetrating into the gap below the warp portion 134, which is also not conducive to improving the bonding strength between the gate line 200 and the doped polysilicon layer 120.

[0045] Optionally, the length L of the warped portion 134 extending into the opening of the gate groove 133 is 50nm to 2000nm, for example, any value among 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1200nm, 1400nm, 1600nm, 1800nm, and 2000nm, or a value between any two points. Optionally, the length L of the warped portion 134 is 100nm to 500nm. It is understood that if the warped portion 134 is too long, the gate line 200 will have difficulty penetrating and filling the gap below the warped portion 134, affecting contact performance. In addition, a longer warped portion 134 requires higher laser power, which can easily damage the silicon substrate 110 and the doped polycrystalline silicon layer 120.

[0046] Optionally, the warp height H of the warp portion 134 in the direction perpendicular to the doped polysilicon layer 120 is 50nm~500nm. If the warp height is too low, its effect on improving the bonding force of the gate line 200 is not obvious; while if the warp height is too high, the laser energy required is greater, which can easily damage the silicon substrate 110 and the doped polysilicon layer 120.

[0047] Optionally, the projected area of ​​the warped portion 134 on the doped polysilicon layer 120 accounts for 3% to 10% of the bottom area of ​​the gate trench 133. It is understood that when the projected area of ​​the warped portion 134 on the doped polysilicon layer 120 is too small, the effect of the warped portion 134 in improving the bonding force of the gate line 200 is not obvious; while when the projected area of ​​the warped portion 134 on the doped polysilicon layer 120 is too large, the laser energy required is greater, which can easily damage the silicon substrate 110 and the doped polysilicon layer 120.

[0048] Optionally, all edges of the passivation layer 130 adjacent to the gate slot 133 may form warped portions 134; or, the passivation layer 130 may form warped portions 134 on a portion of the edges adjacent to the gate slot 133, with multiple warped portions 134 spaced apart along the edges of the passivation layer 130. A portion of the gate slots 133 may have warped portions 134, for example, 20% to 80% of the gate slots 133 may have warped portions 134; alternatively, all gate slots 133 may have warped portions 134.

[0049] Optionally, the area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate trench 133 may be a plurality of continuous or discontinuous circular regions, which are arranged along the extension direction of the gate line 200. It should be understood that the extension direction of the gate line 200 is parallel to the doped polysilicon layer 120. Figure 5 This is a scanning electron microscope (SEM) image of the surface of the battery substrate 100 in one embodiment of this application. Figure 5As shown, in this embodiment, the multiple gate grooves 133 are circular and arranged at intervals along the extension direction of the gate line 200. That is, the area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate grooves 133 is a multiple discontinuous circular area.

[0050] In other alternative embodiments, the shape of the gate groove 133 (view perpendicular to the doped polysilicon layer 120) can be adjusted as needed. For example, the area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate groove 133 can be a plurality of discontinuous square regions, which are arranged along the extension direction of the gate line 200. Alternatively, the area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate groove 133 can also be a strip-shaped region, with the extension direction consistent with the extension direction of the gate line 200.

[0051] Optionally, the area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate trench 133 has a dimension W of 5 μm to 30 μm in the width direction of the gate line 200. The area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate trench 133 is positively correlated with this dimension W. The smaller W is, the smaller the area of ​​the doped polysilicon layer 120 exposed at the bottom of the gate trench 133, resulting in insufficient overall area of ​​the gate trench 133, which will limit the current transmission capability and affect the performance of the solar cell. On the other hand, the larger W is, the larger the area of ​​the doped polysilicon layer 120 exposed by the gate trench 133, which means that more laser energy is required and it is easy to damage the silicon substrate 110 and the doped polysilicon layer 120.

[0052] In this embodiment, the surface of the doped polysilicon layer 120 at the bottom of the gate groove 133 is provided with a plurality of protrusions 123. The plurality of protrusions 123 can effectively increase the contact area between the doped polysilicon layer 120 and the gate line 200, which is beneficial to reduce the contact resistance; at the same time, it can also increase the bonding force between the gate line 200 and the doped polysilicon layer 120, thereby improving the reliability of the gate line 200.

[0053] Optionally, the height of the protrusion structure 123 in the direction perpendicular to the doped polysilicon layer 120 is 10 nm to 100 nm, and the width of the protrusion structure 123 in the direction parallel to the doped polysilicon layer 120 is 10 nm to 100 nm. It is understood that if the protrusion height of the protrusion structure 123 is too low, the effect of increasing the contact area and improving the bonding strength will be limited; if the width of the protrusion structure 123 is too large, the number of protrusion structures 123 will be relatively small, thus limiting the effect of increasing the contact area and improving the bonding strength. Adjacent protrusion structures 123 can be continuous or spaced apart. The protrusion structure 123 can be conical, frustum-shaped, cylindrical, prismatic, pyramidal, or other shapes.

[0054] Optionally, the total projected area of ​​all the protrusions 123 at the bottom of the grid groove 133 accounts for 30% to 80% of the total area of ​​the bottom of the grid groove 133. It is understood that if the proportion of the protrusions 123 to the total area of ​​the bottom of the grid groove 133 is small, the effect of increasing the contact area and improving the bonding strength will be limited. It should be understood that the total area of ​​the bottom of the grid groove 133 here is calculated with the bottom of the grid groove 133 as the plane, and does not include the surface area increased due to the undulations of the protrusions 123.

[0055] In the embodiments of this application, the gate line 200 can be a single-layer structure or a composite layer structure. When the gate line 200 is a single-layer structure, a single metal or alloy with good conductivity can be used, such as an alloy composed of one or more of copper, silver, iron, zinc, tin, lead, titanium, chromium, cadmium, molybdenum, and vanadium.

[0056] When the gate line 200 is a composite layer structure, it includes a multilayer structure. In an optional embodiment, the gate line 200 includes a barrier layer and a conductive layer, with the conductive layer disposed on the side of the barrier layer opposite to the doped polysilicon layer 120. Both the barrier layer and the conductive layer are conductive, and the barrier layer also prevents the conductive layer material from diffusing into the doped polysilicon layer 120 and the silicon substrate 110. In a specific embodiment, the barrier layer is made of an aluminum alloy, for example, the main body is aluminum, and it also contains at least one element selected from nickel, chromium, tungsten, titanium, and molybdenum, while the conductive layer is made of copper. In this case, the barrier layer can effectively prevent the copper in the conductive layer from diffusing into the doped polysilicon layer 120 and the silicon substrate 110, avoiding degradation of battery performance. Optionally, the thickness of the barrier layer is 50 nm to 200 nm, and the thickness of the conductive layer is 50 nm to 200 nm. Further, the gate line 200 may also include a bonding layer, which is located on the outermost side of the gate line 200.

[0057] In this embodiment, the passivation layer 130 contains at least one of silicon nitride, aluminum oxide, and silicon oxynitride. The passivation layer 130 can be deposited by plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 400°C to 500°C. Optionally, the thickness of the passivation layer 130 is 50 nm to 200 nm.

[0058] The solar cell provided in this application embodiment can be manufactured through the following steps:

[0059] After the battery substrate 100 is fabricated, the area where the gate groove 133 needs to be formed is irradiated with an ultraviolet laser with a wavelength of 200nm~400nm. This thermally ablates part of the passivation layer 130, forming the gate groove 133. During the grooving process, the laser energy is absorbed by the passivation layer 130, and heat accumulates on the side of the passivation layer 130 near the doped polysilicon layer 120, i.e., at the inner interface of the passivation layer 130. This results in a large amount of thermal expansion and increased thermal stress on the inner side of the passivation layer 130, but no significant expansion occurs due to the constraint of the underlying doped polysilicon layer 120. When the passivation layer 130 at the gate groove 133 is removed by melting or vaporization, the thermal stress on the lower edge of the passivation layer 130 is released, and it peels off from the doped polysilicon layer 120 due to the difference in thermal expansion coefficients. The expansion on the lower edge of the passivation layer 130 is greater than the expansion on the upper surface, thus causing warping and forming a warped portion 134. The rapid cooling rate of the upper surface of the passivation layer 130 during the cooling process can also promote warping. Additionally, the vaporization phase transition during the ablation of the passivation layer 130 may increase the pressure on the underside of the passivation layer 130 in the gate slot 133 region, eventually causing it to "burst open" and resulting in warping of the passivation layer 130 edges. Optionally, the pulse width of the ultraviolet laser is 10×10. -15 s~20×10 -15 s, with an energy density of 200 μJ / cm 2 ~800μJ / cm 2 The power density is 1×10 9 W / cm 2 ~5×10 9 W / cm 2 .

[0060] After laser grooving, a sintering-photoinjection process is initiated, involving sintering at 750℃~850℃ for 30s~90s and photoinjection at 600℃~700℃ for 10s~60s to repair laser-induced passivation damage. Following this, the passivation layer residue at the bottom of the gate trench 133 is removed by cleaning, exposing the highly active doped polycrystalline silicon layer 120. The cleaning solution can be one or more of sulfuric acid, hydrochloric acid, hydrofluoric acid, sodium hydroxide, potassium hydroxide, and hydrogen peroxide, with a concentration of 0.5%~1.5%.

[0061] When fabricating the gate line 200, a barrier layer (such as an aluminum alloy layer) can be deposited first using a physical vapor deposition process (such as magnetron sputtering), and then a conductive layer (such as a copper layer) can be fabricated using either a physical vapor deposition process or an electroplating process, or a physical vapor deposition process and an electroplating process can be used sequentially.

[0062] This application embodiment improves the bonding method between the gate line 200 and the battery substrate 100, thereby reducing the contact resistance between the gate line 200 and the doped polysilicon layer 120 and increasing the bonding strength between the gate line 200 and the battery substrate 100. Specifically, it can reduce the series resistance Rs to 0.1Ω / cm. 2 ~0.4Ω / cm 2 The pull-out strength of grid line 200 is greater than 5 N·cm.

[0063] The solar cell in this application embodiment can be a back-contact cell. Figure 6 This is a partial cross-sectional view of a solar cell according to one embodiment of this application. Figure 6 As shown, the solar cell substrate 100 includes a silicon substrate 110, an n-type doped polycrystalline silicon layer 121, a p-type doped polycrystalline silicon layer 122, a first passivation layer 131, and a second passivation layer 132. The n-type doped polycrystalline silicon layer 121 and the p-type doped polycrystalline silicon layer 122 are both disposed on the back side of the silicon substrate 110 and separated by an isolation trench 150. Specifically, the n-type doped polycrystalline silicon layer 121 and the p-type doped polycrystalline silicon layer 122 are alternately distributed (only one n-type doped polycrystalline silicon layer 121 and one p-type doped polycrystalline silicon layer 122 are shown in the figure). A tunneling oxide layer 140, specifically silicon oxide, is disposed between the n-type doped polycrystalline silicon layer 121 and the silicon substrate 110, and between the p-type doped polycrystalline silicon layer 122 and the silicon substrate 110. A first passivation layer 131 is distributed on the surfaces of the n-type doped polysilicon layer 121 and the p-type doped polysilicon layer 122, as well as on the inner wall of the isolation trench 150. A second passivation layer 132 is disposed on the front side of the silicon substrate 110. Gate trenches 133 are formed on both the n-type doped polysilicon layer 121 and the p-type doped polysilicon layer 122, and gate lines 200 are provided therein. Furthermore, warped portions 134 are formed on the edges of the first passivation layer 131 adjacent to the gate trenches 133.

[0064] It should be understood that the combination of the grid line 200 and the battery substrate 100 provided in this application embodiment is not limited to back contact batteries, but can also be applied to other battery types that require the opening of grid line grooves 133, such as tunnel oxide passivated contact (TOPCon) batteries.

[0065] In summary, this application provides a solar cell and a photovoltaic module. The solar cell includes a cell substrate 100 and grid lines 200 disposed on the cell substrate 100. The cell substrate 100 includes a silicon substrate 110, a doped polycrystalline silicon layer 120, and a passivation layer 130. The doped polycrystalline silicon layer 120 and the passivation layer 130 are stacked. A grid line groove 133 is formed on the passivation layer 130, with the bottom of the grid line groove 133 exposing the doped polycrystalline silicon layer 120. At least a portion of the edge of the passivation layer 130 adjacent to the grid line groove 133 is warped away from the doped polycrystalline silicon layer 120 to form a warped portion 134. The grid lines 200 cover and fill the grid line groove 133. In the solar cell of this application embodiment, the edge of the passivation layer 130 is warped to form the warped portion 134. On the one hand, the gap formed between the warped portion 134 and the doped polysilicon layer 120 widens the bottom area of ​​the grid groove 133, thereby providing a larger contact area between the grid line 200 and the doped polysilicon layer 120. This helps to reduce the contact resistance between the grid line 200 and the doped polysilicon layer 120. On the other hand, because the warped portion 134 is raised, the cross-sectional profile of the grid groove 133 is similar to a dovetail shape. When the grid groove 133 is filled with the grid line 200, the gap below the warped portion 134, as part of the space of the grid groove 133, is also filled by the grid line 200. The warped portion 134 can effectively prevent the grid line 200 from detaching away from the doped polysilicon layer 120, thereby improving the bonding strength between the grid line 200 and the cell substrate 100 and reducing the risk of the grid line 200 falling off. Therefore, the embodiments of this application improve the reliability and conductivity of the grid line 200 by improving the morphology of the grid groove 133, thereby ensuring that the solar cell has better durability and cell efficiency.

[0066] The photovoltaic modules provided in this application include the aforementioned solar cells, and therefore also have the advantages of high reliability and high cell efficiency.

[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A solar cell, characterized in that, The battery includes a battery substrate and gate lines disposed on the battery substrate. The battery substrate includes a silicon substrate, a doped polysilicon layer, and a passivation layer. The doped polysilicon layer and the passivation layer are stacked. A gate line groove is formed on the passivation layer. The bottom of the gate line groove exposes the doped polysilicon layer. At least a portion of the edge of the passivation layer adjacent to the gate line groove is warped away from the doped polysilicon layer to form a warped portion. The gate lines cover and fill the gate line groove.

2. The solar cell according to claim 1, characterized in that, The warped portion, on the surface opposite to the grid groove, is in contact with the grid line.

3. The solar cell according to claim 1, characterized in that, The warping angle of the warped portion relative to the doped polycrystalline silicon layer is 5° to 50°.

4. The solar cell according to claim 1, characterized in that, The length of the warped portion extending into the opening of the grid groove is 50nm~2000nm.

5. The solar cell according to claim 1, characterized in that, The projected area of ​​the warped portion on the doped polysilicon layer accounts for 3% to 10% of the bottom area of ​​the gate groove.

6. The solar cell according to claim 1, characterized in that, The warped portion has a warping height of 50 nm to 500 nm in the direction perpendicular to the doped polycrystalline silicon layer.

7. The solar cell according to claim 1, characterized in that, The area of ​​the doped polysilicon layer exposed at the bottom of the gate trench is a strip-shaped area, and its extension direction is consistent with the extension direction of the gate line; Alternatively, the area of ​​the doped polysilicon layer exposed at the bottom of the gate trench may be a series of continuous or discontinuous circular regions, and the series of circular regions may be arranged along the extension direction of the gate line; Alternatively, the area of ​​the doped polysilicon layer exposed at the bottom of the gate trench is a plurality of discontinuous square regions, and the plurality of square regions are arranged along the extension direction of the gate line.

8. The solar cell according to claim 1, characterized in that, The area of ​​the doped polysilicon layer exposed at the bottom of the gate trench has a dimension of 5μm to 30μm in the width direction of the gate line.

9. The solar cell according to any one of claims 1-8, characterized in that, The surface of the doped polysilicon layer at the bottom of the gate groove has several protrusion structures.

10. The solar cell according to claim 9, characterized in that, The height of the protrusion structure in the direction perpendicular to the doped polysilicon layer is 10nm~100nm, and the width of the protrusion structure in the direction parallel to the doped polysilicon layer is 10nm~100nm.

11. The solar cell according to claim 9, characterized in that, The total projected area of ​​all the protruding structures at the bottom of the grid groove accounts for 30% to 80% of the total area of ​​the bottom of the grid groove.

12. The solar cell according to any one of claims 1-8, characterized in that, The gate line includes a barrier layer and a conductive layer, wherein the conductive layer is disposed on the side of the barrier layer opposite to the doped polysilicon layer.

13. The solar cell according to any one of claims 1-8, characterized in that, The doped polysilicon layer includes an n-type doped polysilicon layer and a p-type doped polysilicon layer disposed on the back side of the silicon substrate. The n-type doped polysilicon layer and the p-type doped polysilicon layer are alternately distributed in a direction parallel to the silicon substrate, and the n-type doped polysilicon layer and the p-type doped polysilicon layer are separated by an isolation trench. The passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer covers the surfaces of the n-type doped polysilicon layer and the p-type doped polysilicon layer, as well as the inner wall of the isolation trench. The gate trench is formed in the first passivation layer, and the second passivation layer covers the front side of the silicon substrate.

14. A photovoltaic module, characterized in that, The solar cell includes any one of claims 1-13.

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