Liquid crystal display panel

Abstract

The utility model provides a kind of liquid crystal display panel, comprising: multiple parallel scanning lines, multiple common electrode lines and multiple parallel data lines, two adjacent horizontal common electrode lines and two adjacent data lines define a subpixel, each subpixel includes first thin film transistor, second thin film transistor and third thin film transistor, multiple subpixels include different first subpixel and second subpixel of constituting mode, the third thin film transistor of first subpixel is connected with longitudinal common electrode line, the third thin film transistor of second subpixel is connected with longitudinal common electrode line and horizontal common electrode line, or the third thin film transistor of second subpixel is connected with longitudinal common electrode line, and the main area storage capacitor of second subpixel is connected with horizontal common electrode and is connected with longitudinal common electrode line by connecting structure, first subpixel and second subpixel are arranged in matrix mode, and the number of first subpixel is greater than the number of second subpixel on each row and each column.

Description

Technical Field

[0001] This utility model relates to the field of display panel manufacturing technology, and in particular to a liquid crystal display panel. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are one of the main products of current flat panel displays. With the improvement of information technology and people's living standards, people's requirements for panel size, resolution, and display image quality are also increasing. In the field of display technology, LCS (Low Color Shift) technology mainly reduces color shift caused by viewing images at different angles by improving the structure of the liquid crystal panel. Existing liquid crystal display panels use LCS technology, but their structure has the problem of the series connection between common electrodes occupying a large aperture area, resulting in a low pixel aperture ratio. Therefore, how to solve the above problems and enable liquid crystal displays with low color shift pixel design to avoid aperture ratio loss and improve the transmittance of liquid crystal display panels is one of the research topics that the industry is committed to. Utility Model Content

[0003] To address the aforementioned shortcomings of the prior art, this invention provides a pixel structure for a liquid crystal display panel that improves the aperture ratio and enhances the transmittance of the liquid crystal display panel. Additionally, a liquid crystal display panel incorporating this pixel structure is also provided.

[0004] This utility model provides a liquid crystal display panel, comprising: multiple parallel scan lines, multiple common electrode lines, and multiple parallel data lines. The multiple common electrode lines include parallel transverse common electrode lines and parallel longitudinal common electrode lines. The data line is perpendicular to the horizontal common electrode line and the scan line, and a data line is sandwiched between and parallel to two adjacent horizontal common electrode lines. Two adjacent horizontal common electrode lines and two adjacent data lines define a sub-pixel. Each sub-pixel is divided into a main pixel region and a secondary pixel region by the scan lines. The secondary pixel region includes a first thin-film transistor and a third thin-film transistor, and the main pixel region includes a second thin-film transistor. The plurality of sub-pixels are arranged in a matrix, and the plurality of sub-pixels include first sub-pixels and second sub-pixels with different configurations. The third thin-film transistor of the first sub-pixel is connected to the vertical common electrode line. The third thin-film transistor of the second sub-pixel is connected to the vertical common electrode line and the horizontal common electrode line, or the third thin-film transistor of the second sub-pixel is connected to the vertical common electrode line, and the main area storage capacitor of the second sub-pixel is connected to the horizontal common electrode and connected to the vertical common electrode line through a connection structure. The first sub-pixel and the second sub-pixel are arranged in a matrix, and the number of the first sub-pixel is greater than the number of the second sub-pixel in each row and each column.

[0005] Compared with the prior art, the liquid crystal display panel provided by this utility model achieves a grid-like connection of common electrode lines by mixing and arranging sub-pixels with different aperture ratios, which can improve the aperture ratio of pixels and enhance the transmittance of the liquid crystal display panel. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the equivalent circuit of the pixel area of ​​an embodiment of a liquid crystal display panel in the prior art.

[0007] Figure 2 This is a structural equivalent circuit diagram of a pixel unit in another embodiment of a liquid crystal display panel in the prior art.

[0008] Figure 3 This is a schematic diagram of the sub-pixel arrangement and equivalent circuit of an example of the pixel region of the pixel array substrate according to the first embodiment of this utility model.

[0009] Figure 4 (a) is the equivalent circuit diagram of sub-pixel A. Figure 4 (b) is the equivalent circuit diagram of sub-pixel B.

[0010] Figure 5 (a) is the pixel structure layout diagram of sub-pixel A. Figure 5 (b) is Figure 5 (a) A sectional view along line A-A'.

[0011] Figure 6 (a) is a layout diagram of the pixel structure of sub-pixel B. Figure 6 (b) is Figure 6 (a) A cross-sectional view along line B-B'.

[0012] Figure 7 This is a schematic diagram of the equivalent circuit of sub-pixel C.

[0013] Figure 8 This is a layout diagram of the pixel structure of sub-pixel C.

[0014] Figure 9 (a) is along Figure 8A sectional view of line A-A'. Figure 9 (b) is Figure 8 A sectional view along line C-C'.

[0015] Figure 10 This is a schematic diagram of the sub-pixel arrangement and equivalent circuit of an example of the pixel region of the pixel array substrate according to the second embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0018] refer to Figure 1 This is a schematic diagram of the equivalent circuit of the pixel area of ​​a liquid crystal display panel according to an embodiment of the prior art. Figure 1 The diagram illustrates a 3T structure for low color shift pixel design. This design utilizes three thin-film transistors (TFTs) to control the voltage of the main pixel electrode and the secondary pixel electrode, maintaining a specific ratio. This creates a difference in the tilting degree of the liquid crystal molecules in the two regions, resulting in low color shift. Specifically, each pixel electrode in the pixel region is divided into a main pixel electrode and a secondary pixel electrode. The main pixel electrode is driven by TFT T1, while the secondary pixel electrodes are driven by TFTs T2 and T3. In the secondary pixel region, the source of TFT T3, which acts as a resistive voltage divider, needs to be connected to a reference level. Figure 2 This is an equivalent circuit diagram of the pixel unit structure of another embodiment of a liquid crystal display panel in the prior art. To achieve a grid-like series connection of the common electrodes Acom on the array substrate and improve the potential stability of the common electrodes of each pixel, the horizontal common electrode of each pixel needs to be connected to the vertical common electrode. When the source of the thin-film transistor T3 needs to be connected to a reference level, the source of the thin-film transistor T3 in each pixel is connected to the horizontal common electrode and then connected in series to the vertical common electrode. However, since this series connection is between different process layers, it occupies a large opening area, resulting in a low pixel aperture ratio.

[0019] To address the aforementioned issues, this invention provides a liquid crystal display panel that achieves a grid-like interconnection of common electrode lines through the layout of sub-pixels with different structures, thereby increasing the pixel aperture ratio and enhancing the transmittance of the liquid crystal display panel.

[0020] The following detailed description, in conjunction with the accompanying drawings, outlines some embodiments of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0021] Please refer to Figures 3 to 5 , Figure 3 This is a schematic diagram of an example of the sub-pixel arrangement and equivalent circuit of the pixel area of ​​a liquid crystal display panel according to the first embodiment of this utility model. Figure 4 (a) is a schematic diagram of the equivalent circuit of sub-pixel A. Figure 4 (b) is the equivalent circuit diagram of sub-pixel B. Figure 5 (a) is a layout diagram of the pixel structure of sub-pixel A. Figure 5 (b) is Figure 5 (a) A sectional view along line A-A'. Figure 6 (a) is a layout diagram of the pixel structure of sub-pixel B. Figure 6 (b) is Figure 6 (a) A cross-sectional view along line B-B'.

[0022] See Figure 3 The equivalent circuit of the pixel area of ​​the liquid crystal display panel in this invention includes: multiple parallel scan lines Gate, multiple common electrode lines Acom, and multiple parallel data lines Data. The multiple common electrode lines Acom include multiple parallel horizontal common electrode lines Acom1 and multiple parallel vertical common electrode lines Acom2. The multiple horizontal common electrode lines Acom1 and Acom2 form a mesh structure. The data lines Data are perpendicular to the horizontal common electrode lines Acom1 and the scan lines Gate. A data line Data is sandwiched between two adjacent horizontal common electrode lines Acom1 and is arranged parallel to them. Two adjacent horizontal common electrode lines Acom1 and two adjacent data lines Data define the pixel area of ​​a sub-pixel. (Reference) Figure 4 Each sub-pixel region is divided into a main pixel region (bright area) and a secondary pixel region (dark area) by a scan line gate. The secondary pixel region contains a first thin-film transistor T1, a third thin-film transistor T3, and a secondary liquid crystal capacitor C. LCA and secondary storage capacitor C stA A second thin-film transistor T2 and a main area liquid crystal capacitor C are disposed within the main pixel area. LCB and main area storage capacitor C stBIn the case of a positive frame, the gate of the first thin-film transistor T1 is connected to the scan line Gate, the drain is connected to the data line Data, and the source is connected to the sub-region storage capacitor C of the pixel sub-region. stA One end and the secondary liquid crystal capacitor C LCA One end is connected to the drain of the third thin-film transistor T3. The sub-region storage capacitor C of the pixel sub-region... stA The other end is connected to the lateral common electrode line Acom1. The sub-region liquid crystal capacitor C of the pixel sub-region. LCA The other end is connected to the CF electrode CFcom. In the case of a positive frame, the gate of the third thin-film transistor T3 is connected to the scan line Gate, the source is connected to the vertical common electrode line Acom2, and the drain is connected to the source of the first thin-film transistor T1. The gate of the second thin-film transistor T2 in the main pixel area is connected to the scan line Gate, the drain is connected to the data line Data, and the source is connected to the main region storage capacitor C of the main pixel area. stB One end and the main area liquid crystal capacitor C LCB One end. The main storage capacitor C of the pixel's main region. stB The other end is connected to the aforementioned horizontal common electrode line Acom1, and the main area liquid crystal capacitor C of the pixel main area. LCB The other end is connected to the CF electrode CFcom.

[0023] The liquid crystal display panel of this invention further includes multiple sub-pixels arranged in a matrix. For example... Figure 3 and Figure 4 As shown, multiple sub-pixels include sub-pixels A and B with different configurations. Both sub-pixels A and B have the circuit configuration of the aforementioned pixel region, but they differ as follows: In sub-pixel A, the source of the third thin-film transistor T3 in the sub-region is only connected to the vertical common electrode line Acom2, and not to the horizontal common electrode line Acom1. In sub-pixel B, the source of the third thin-film transistor T3 in the sub-region is connected to both the vertical common electrode line Acom2 and the horizontal common electrode line Acom1.

[0024] The following is for reference Figure 5 and Figure 6 , Figure 5 (b) is Figure 5 The sectional view at line A-A' in (a) Figure 6 (b) is Figure 6 A cross-sectional view at line B-B' in (a). The structure S1 (i.e., the source of the third thin-film transistor T3 in sub-pixel A is connected to the longitudinal common electrode line Acom2) Figure 5 (a) at line A-A') Figure 5As shown in (b), the M2 layer includes the source of the third thin-film transistor T3 and the data line Data. The Acom ITO layer includes a vertical common electrode line Acom2, which extends into a hole 115 located above the source, making the source of the third thin-film transistor T3 electrically contact the vertical common electrode line Acom2. Thus, structure S1, in which the source of the thin-film transistor T3 in sub-pixel A is connected to the vertical common electrode line Acom2, only requires two process passes of the Acom ITO layer and the M2 layer to make the hole connection, and the hole 115 occupies a smaller opening area. In contrast, in sub-pixel B, structure S2, in which the source of the third thin-film transistor T3 is connected to the vertical common electrode line Acom2 and the horizontal common electrode line Acom1 (i.e., Figure 6 (a) at line B-B') Figure 6 As shown in (b), layer M1 includes a lateral common electrode line Acom1. Layer M2' includes the source of the third thin-film transistor T3 and a data line Data. The Acom ITO layer includes a vertical common electrode line Acom2. The vertical common electrode line Acom2 extends into a hole 117 disposed above the lateral common electrode line Acom1, so that the source of the third thin-film transistor T3, the lateral common electrode Acom1, and the vertical common electrode Acom2 are electrically connected to each other, thereby enabling the third thin-film transistor T3 in sub-pixel A to connect to both the vertical common electrode Acom2 and the lateral common electrode Acom1. However, the structure in sub-pixel B where the source of the third thin-film transistor T3 is connected to both the vertical common electrode Acom2 and the lateral common electrode Acom1 requires three processing passes of the Acom ITO layer, M1' layer, and M2 layer to form a hole connection compared to sub-pixel A. Hole 117 occupies a larger opening area than hole 115, resulting in a smaller aperture ratio for sub-pixel B than for sub-pixel A.

[0025] In order to achieve a grid-like connection of the common electrode lines Acom and improve the stability of the Acom potential of each pixel, the liquid crystal display panel of the first embodiment of this utility model arranges sub-pixels A and sub-pixels B in a mixed manner.

[0026] like Figure 3As shown, sub-pixels B, A, and A are sequentially arranged in the first row; sub-pixels A, B, and A are sequentially arranged in the second row; and sub-pixels A, A, and B are sequentially arranged in the third row, with this arrangement repeated. Specifically, the pixel composition in the vertical direction is as follows: sub-pixels A and B are alternately arranged, or two adjacent sub-pixels B are spaced n (n>1) sub-pixels A apart, or arranged in no fixed order; the pixel composition in the horizontal direction is as follows: sub-pixels A and B are alternately arranged, or two adjacent sub-pixels B are spaced n (n>1) sub-pixels A apart, or arranged in no fixed order, as long as there is at least one sub-pixel B in each row and each column. Through this arrangement, the horizontal common electrode and the vertical common electrode can form a grid-like connection. Compared to the existing technology where each pixel's horizontal common electrode is connected to a vertical common electrode, i.e., the entire liquid crystal display panel is arranged in the form of sub-pixels B, the liquid crystal display panel of the first embodiment of this utility model reduces the proportion of sub-pixels B by arranging sub-pixels A and B in a mixed manner. Furthermore, since the aperture ratio of sub-pixels A is greater than that of sub-pixels B, the liquid crystal display panel of the first embodiment of this utility model improves the overall aperture ratio and transmittance of the liquid crystal display panel compared to the existing technology where all pixels are arranged in the form of sub-pixels B.

[0027] In a first embodiment of this utility model, a liquid crystal display panel has sub-pixels A and B arranged in a predetermined order. For example... Figure 3 The arrangement of sub-pixels A and B shown has two consecutive sub-pixels A between two adjacent sub-pixels B horizontally, arranged as BAABAA… Similarly, two consecutive sub-pixels A between two adjacent sub-pixels B vertically (the interval between sub-pixels A and B is n=2), also arranged as BAABAA…. Therefore, the smallest repeating unit of this ordered arrangement is a 3×3 square, where 3 sub-pixels B are arranged along one diagonal, and the remaining squares are all sub-pixels A. Furthermore, the interval n between sub-pixels A and B is not limited to 2; it can also be a value greater than 2. In this case, the smallest repeating unit of the corresponding ordered arrangement is a (n+1)×(n+1) square, where (n+1) sub-pixels B are arranged along one diagonal, and the remaining squares are all sub-pixels A. Therefore, the number of sub-pixels B accounts for only 1 / 3 of the total number of sub-pixels. This ordered arrangement reduces the overall proportion of sub-pixels B, thereby increasing the overall aperture ratio and transmittance of the liquid crystal display panel.

[0028] This utility model also provides a liquid crystal display panel according to a second embodiment, which differs from the first embodiment only in that the liquid crystal display panel of the second embodiment has a different structure from the sub-pixel B structure, that is, the sub-pixel C of the second embodiment replaces the sub-pixel B of the first embodiment. Both sub-pixel C and sub-pixel A have the circuit configuration of the pixel region described in the first embodiment. The difference between sub-pixel C and sub-pixel A is that sub-pixel C has a connection structure S3 connecting the horizontal common electrode line Acom1 and the vertical common electrode line Acom2, in addition to the third thin-film transistor T3. For example... Figure 7 For example, connection structure S3 stores capacitor C in the main region of the pixel main region. stB Connect the longitudinal common electrode line Acom2 to the line connecting the transverse common electrode line Acom1. Refer to the following... Figure 8 and Figure 9 , Figure 9 (a) is Figure 8 The sectional view at line A-A' (i.e., structure S1) in the diagram. Figure 9 (b) is Figure 8 A cross-sectional view at line B-B' (i.e., connecting structure S3). For example... Figure 4 and Figure 7 As shown, the circuitry at the third thin-film transistor T3 of sub-pixel A and sub-pixel C is identical. Figure 7 As shown, the source of the third thin-film transistor T3 of sub-pixel C is only connected to the vertical common electrode line Acom2, and the main region storage capacitor C of the pixel's main region... stB Connect the transverse common electrode line Acom1, and connect it to the longitudinal common electrode Acom2 via the connecting structure S3. (As per...) Figure 5 As shown in (b), the structure S1, where the source of the third thin-film transistor T3 in sub-pixel A is connected to the vertical common electrode, requires two process passes (Acom ITO layer and M2 layer) for hole drilling. In the connection structure S3 of sub-pixel C, as shown... Figure 9 As shown in (b), layer M1 includes a lateral common electrode, and layer Acom ITO includes a vertical common electrode. Layer Acom ITO extends into hole 119 located above the lateral common electrode, thereby electrically connecting the lateral and vertical common electrodes. Thus, sub-pixel C can connect the vertical common electrode to the lateral common electrode through connection structure S3, which has an additional opening outside the source of the third thin-film transistor T3. Since sub-pixel C occupies a larger opening area due to both hole 115 of structure S1 and hole 119 of connection structure S3, the aperture ratio of sub-pixel C is smaller than that of sub-pixel A, which only contains hole 115 of structure S1.

[0029] Furthermore, such as Figure 10As shown, the sub-pixels A and C included in the liquid crystal display panel of the second embodiment can be arranged in the same matrix manner as the liquid crystal display panel of the first embodiment, so that the horizontal common electrode and the vertical common electrode of the liquid crystal display panel of the second embodiment can also form a grid-like connection. Compared with the existing technology where the horizontal common electrode of each pixel is connected to the vertical common electrode, that is, the liquid crystal display panel is arranged entirely in the form of sub-pixels C, the liquid crystal display panel of the first embodiment of the present invention reduces the proportion of sub-pixels C by arranging sub-pixels A and C in a mixed manner. Since the aperture ratio of sub-pixels A is greater than that of sub-pixels C, the liquid crystal display panel of the second embodiment of the present invention improves the overall aperture ratio and transmittance of the liquid crystal display panel compared with the existing technology where all sub-pixels are arranged in the form of C.

[0030] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the protection scope of the present invention.

Claims

1. A liquid crystal display panel, characterized in that, include: Multiple parallel scan lines, multiple common electrode lines, and multiple parallel data lines, wherein the multiple common electrode lines include mutually parallel transverse common electrode lines and mutually parallel longitudinal common electrode lines. The data line is perpendicular to the horizontal common electrode line and the scan line, and a data line is sandwiched between and parallel to two adjacent horizontal common electrode lines. Two adjacent horizontal common electrode lines and two adjacent data lines define a sub-pixel. Each sub-pixel is divided into a main pixel region and a secondary pixel region by the scan lines. The secondary pixel region includes a first thin-film transistor and a third thin-film transistor, and the main pixel region includes a second thin-film transistor. The plurality of sub-pixels are arranged in a matrix, and the plurality of sub-pixels include first sub-pixels and second sub-pixels with different configurations. The third thin-film transistor of the first sub-pixel is connected to the vertical common electrode line. The third thin-film transistor of the second sub-pixel is connected to the vertical common electrode line and the horizontal common electrode line, or the third thin-film transistor of the second sub-pixel is connected to the vertical common electrode line, and the main area storage capacitor of the second sub-pixel is connected to the horizontal common electrode and connected to the vertical common electrode line through a connection structure. The first sub-pixel and the second sub-pixel are arranged in a matrix, and the number of the first sub-pixel is greater than the number of the second sub-pixel in each row and each column.

2. The liquid crystal display panel according to claim 1, characterized in that, The multiple transverse common electrode lines and the multiple longitudinal common electrode lines form a mesh structure.

3. The liquid crystal display panel according to claim 1, characterized in that, The sub-pixel regions are respectively divided into primary pixel regions and secondary pixel regions by the scan lines. The pixel sub-region is provided with the first thin-film transistor, the third thin-film transistor, the sub-region liquid crystal capacitor, and the sub-region storage capacitor. The main pixel region is provided with a second thin-film transistor, a main region liquid crystal capacitor, and a main region storage capacitor.

4. The liquid crystal display panel according to claim 3, characterized in that, The gate of the first thin-film transistor is connected to the scan line, the drain of the first thin-film transistor is connected to the data line, the source of the first thin-film transistor is connected to one end of the secondary storage capacitor and one end of the secondary liquid crystal capacitor, and is connected to the drain of the third thin-film transistor. The other end of the secondary storage capacitor is connected to the lateral common electrode line, and the other end of the secondary liquid crystal capacitor is connected to the CF electrode. The gate of the third thin-film transistor is connected to the scan line, the source of the third thin-film transistor is connected to the vertical common electrode line, and the drain of the third thin-film transistor is connected to the source of the first thin-film transistor. The gate of the second thin-film transistor is connected to the scan line, the drain of the second thin-film transistor is connected to the data line, the source of the second thin-film transistor is connected to one end of the main region storage capacitor and one end of the main region liquid crystal capacitor, the other end of the main region storage capacitor is connected to the lateral common electrode line, and the other end of the main region liquid crystal capacitor is connected to the CF electrode.

5. The liquid crystal display panel according to claim 1, characterized in that, In the first sub-pixel, the source of the third thin-film transistor is only connected to the vertical common electrode line. The source of the third thin-film transistor in the second sub-pixel is connected to the vertical common electrode line and the horizontal common electrode line.

6. The liquid crystal display panel according to claim 1, characterized in that, In the first sub-pixel, the source of the third thin-film transistor is only connected to the vertical common electrode line. In the second sub-pixel, the source of the third thin-film transistor is only connected to the vertical common electrode line, and the main region storage capacitor of the second sub-pixel is connected to the horizontal common electrode line and connected to the horizontal common electrode through the connection structure.

7. The liquid crystal display panel according to claim 1, characterized in that, The first sub-pixel includes an M2 layer and an Acom ITO layer above the M2 layer. The source of the third thin-film transistor is disposed in the M2 layer, and the vertical common electrode line is disposed in the Acom ITO layer. The vertical common electrode line extends into a first hole disposed above the source of the third thin-film transistor, so that the source of the third thin-film transistor is electrically connected to the vertical common electrode line.

8. The liquid crystal display panel according to claim 1, characterized in that, The second sub-pixel includes, from bottom to top, layers M1, M2', and an Acom ITO layer. The lateral common electrode line is disposed on the M1 layer, the source of the third thin film transistor and the data line are disposed on the M2' layer, the vertical common electrode line is disposed on the Acom ITO layer, and the vertical common electrode line extends into a second hole disposed above the lateral common electrode line, so that the source of the third thin film transistor, the lateral common electrode and the vertical common electrode are electrically connected to each other.

9. The liquid crystal display panel according to claim 1, characterized in that, The second sub-pixel includes an M1 layer and an Acom ITO layer above the M1 layer. The lateral common electrode is disposed on the M1 layer, and the vertical common electrode is disposed on the Acom ITO layer. The vertical common electrode line extends into a third hole disposed above the lateral common electrode, so that the lateral common electrode and the vertical common electrode line are electrically connected.

10. The liquid crystal display panel according to claim 1, characterized in that, In the matrix method, The first sub-pixel and the second sub-pixel are set alternately, or Two adjacent second sub-pixels are spaced n times apart by the first sub-pixels, where n>1, or Arranged in no fixed order.

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