A common-mode detection circuit and control circuit

Abstract

This utility model discloses a common-mode detection circuit and control circuit, relating to the field of circuits. The control terminal of a first detection switch is connected to the input terminal of an operational amplifier. When the voltage jump amplitude at the input terminal of the operational amplifier does not reach a preset threshold, the on-resistance of the first detection switch is greater than that of the second detection switch, and the common-mode detection circuit outputs a first signal. When the voltage jump amplitude at the input terminal of the operational amplifier reaches the preset threshold, the on-resistance of the first detection switch is less than that of the second detection switch, and the common-mode detection circuit outputs a second signal. By utilizing the change in the on-resistance of the first detection switch, the voltage jump detection at the input terminal of the operational amplifier is achieved, thereby realizing the effective detection of the PWM wave common-mode signal, so that the operational amplifier can achieve enhancement and suppression of the PWM wave common-mode signal. At the same time, the detection threshold is set by a preset bias voltage, reducing the possibility of false triggering, ensuring detection accuracy, and ensuring the safety and reliability of the operational amplifier.

Description

Technical Field

[0001] This utility model relates to the field of circuits, and in particular to a common-mode detection circuit and control circuit. Background Technology

[0002] With the development of electronic technology, more and more electronic circuits require current measurement. Therefore, operational amplifiers, especially current sensing amplifiers, are increasingly widely used. Current sensing amplifiers integrate key components within the operational amplifier, achieving high common-mode rejection ratio, high input impedance, low noise, low linearity error, and low offset drift through a specific structure. Typically, in applications, a low-resistance, high-precision measuring resistor is inserted into the current path to be measured. The voltage across the measuring resistor is proportional to the current flowing through it. The two input terminals of the current sensing amplifier are connected to the two ends of the measuring resistor to amplify the voltage difference by a fixed factor. Then, based on the fixed factor and the resistance value of the measuring resistor, the precise current magnitude can be calculated, achieving high-precision current measurement. However, during operation amplifier testing, the input terminal is affected by common-mode signals, especially PWM (Pulse Width Modulation) common-mode signals. The high-frequency pulse characteristics of PWM common-mode signals can cause serious interference to the operation amplifier, resulting in detection errors. In severe cases, it can even lead to safety issues such as damage to the operation amplifier. Therefore, how to detect the common-mode signal at the input terminal of the operation amplifier has become an urgent technical problem to be solved. Utility Model Content

[0003] The purpose of this invention is to provide a common-mode detection circuit and control circuit, which aims to solve the problem of common-mode signal detection at the input of an operational amplifier.

[0004] To solve the above technical problems, this utility model provides a common-mode detection circuit, including a first detection switch and a second detection switch. The first detection switch and the second detection switch are connected in series, and the first end of the series circuit is connected to the power supply, and the second end is grounded. The control terminal of the first detection switch is connected to the input terminal of the operational amplifier, and the control terminal of the second detection switch is connected to a preset bias voltage.

[0005] When the voltage at the control terminal of the first detection switch changes by a greater than a preset threshold within a preset time period, the on-resistance of the first detection switch is less than that of the second detection switch.

[0006] Optionally, the preset threshold includes a first threshold and a second threshold, and the preset bias voltage includes a first bias voltage and a second bias voltage; the first detection switch includes a first NMOS transistor and a first PMOS transistor, and the second detection switch includes a second PMOS transistor and a second NMOS transistor;

[0007] The control terminal of the first NMOS transistor is connected to the input terminal of the operational amplifier, the first terminal is grounded, the second terminal is connected to the first terminal of the second PMOS transistor and serves as the first output terminal of the common-mode detection circuit, the second terminal of the second PMOS transistor is connected to the power supply, and the control terminal is connected to the first bias voltage.

[0008] When the voltage at the control terminal of the first NMOS transistor increases by more than a first threshold within a preset time period, the on-resistance of the first NMOS transistor is less than the on-resistance of the second PMOS transistor; when the voltage at the control terminal of the first NMOS transistor increases by less than or equal to the first threshold within a preset time period, the on-resistance of the first NMOS transistor is greater than the on-resistance of the second PMOS transistor.

[0009] The control terminal of the first PMOS transistor is connected to the input terminal of the operational amplifier, the first terminal is connected to the power supply, the second terminal is connected to the first terminal of the second NMOS transistor and serves as the second output terminal of the common-mode detection circuit, the second terminal of the second NMOS transistor is grounded, and the control terminal is connected to the second bias voltage.

[0010] When the voltage at the control terminal of the first PMOS transistor decreases by a greater than a second threshold within a preset time period, the on-resistance of the first PMOS transistor is less than the on-resistance of the second NMOS transistor; when the voltage at the control terminal of the first PMOS transistor decreases by a less than or equal to the second threshold within a preset time period, the on-resistance of the first PMOS transistor is greater than the on-resistance of the second NMOS transistor.

[0011] Optional, also includes:

[0012] The first capacitor has its first terminal connected to the non-inverting input terminal of the operational amplifier.

[0013] The second capacitor has its first end connected to the inverting input terminal of the operational amplifier, and its second end connected to the second terminal of the first capacitor and the control terminal of the first NMOS transistor, respectively.

[0014] The third capacitor has its first end connected to the non-inverting input terminal of the operational amplifier;

[0015] The fourth capacitor has its first end connected to the inverting input of the operational amplifier, and its second end connected to the second end of the third capacitor and the control terminal of the first PMOS transistor.

[0016] Optional, also includes:

[0017] The first bias voltage generation module has its output terminal connected to the control terminal of the second PMOS transistor, and is used to output the first bias voltage.

[0018] And / or,

[0019] The second bias voltage generation module has its output terminal connected to the control terminal of the second NMOS transistor, and is used to output the second bias voltage.

[0020] Optionally, the first bias voltage generation module includes a first current source and a third PMOS transistor. The input terminal of the first current source is connected to the first terminal of the third PMOS transistor, the control terminal of the third PMOS transistor, and the control terminal of the second PMOS transistor. The output terminal of the first current source is grounded, and the second terminal of the third PMOS transistor is connected to the power supply.

[0021] The second bias voltage generation module includes a second current source and a third NMOS transistor. The output terminal of the second current source is connected to the first terminal of the third NMOS transistor, the control terminal of the third NMOS transistor, and the control terminal of the second NMOS transistor. The second terminal of the third NMOS transistor is grounded.

[0022] Optional, also includes:

[0023] The fourth NMOS transistor has its first terminal grounded.

[0024] The first terminal of the fourth PMOS transistor is connected to the second terminal of the fourth NMOS transistor, the control terminal of the fourth NMOS transistor, the input terminal of the operational amplifier, and the control terminal of the first NMOS transistor. The control terminal is connected to the control terminal of the third PMOS transistor and the first terminal of the third PMOS transistor. The second terminal is connected to the power supply.

[0025] The fifth PMOS transistor has its first terminal connected to the power supply.

[0026] The fifth NMOS transistor has its first terminal connected to the second terminal of the fifth PMOS transistor, the control terminal of the fifth PMOS transistor, the input terminal of the operational amplifier, and the control terminal of the first PMOS transistor. Its control terminal is connected to the control terminal of the third NMOS transistor and the first terminal of the third NMOS transistor. Its second terminal is grounded.

[0027] Optional, also includes:

[0028] The first current limiting module has a first terminal connected to the input terminal of the operational amplifier and a second terminal connected to the control terminal of the first NMOS transistor.

[0029] And / or,

[0030] The second current limiting module has its first end connected to the input terminal of the operational amplifier and its second end connected to the control terminal of the first PMOS transistor.

[0031] Optional, also includes:

[0032] The first inverter has its input terminals connected to the second terminal of the first NMOS transistor and the first terminal of the second PMOS transistor, respectively.

[0033] And / or,

[0034] The second inverter has its input terminals connected to the second terminal of the first PMOS transistor and the first terminal of the second NMOS transistor, respectively.

[0035] To solve the above-mentioned technical problems, this utility model also provides a control circuit, including an operational amplifier, a first controllable switch, a second controllable switch, and a common-mode detection circuit as described above;

[0036] The output terminal of the common-mode detection circuit is connected to the control terminal of the first controllable switch and the control terminal of the second controllable switch, respectively. The first terminal of the first controllable switch is connected to the input terminal of the common-mode detection circuit and the first terminal of the measuring resistor, respectively, and the second terminal is connected to the non-inverting input terminal of the operational amplifier. The first terminal of the second controllable switch is connected to the input terminal of the common-mode detection circuit and the second terminal of the measuring resistor, respectively, and the second terminal is connected to the inverting input terminal of the operational amplifier.

[0037] The first controllable switch is used to turn off when the common-mode detection circuit detects that the voltage jump amplitude is greater than a preset threshold within a preset time period;

[0038] The second controllable switch is used to turn off when the common-mode detection circuit detects that the voltage jump amplitude is greater than a preset threshold within a preset time period.

[0039] Optional, also includes:

[0040] The third controllable switch has its first end connected to the non-inverting input of the operational amplifier and the second end of the first controllable switch, respectively. The second end is connected to a preset reference voltage and is used to turn on when the common-mode detection circuit detects that the jump amplitude is greater than a preset threshold within a preset time period.

[0041] The fourth controllable switch has its first end connected to the inverting input of the operational amplifier and the second end of the second controllable switch, respectively, and its second end connected to the preset reference voltage. It is used to turn on when the common-mode detection circuit detects that the jump amplitude is greater than the preset threshold within a preset time period.

[0042] This invention provides a common-mode detection circuit, including a first detection switch and a second detection switch. The control terminal of the first detection switch is connected to the input terminal of an operational amplifier, enabling effective detection of voltage jumps at the operational amplifier's input terminal. When the voltage jump amplitude at the operational amplifier's input terminal does not reach a preset threshold, the on-resistance of the first detection switch is greater than that of the second detection switch, and the common-mode detection circuit outputs a first signal. When the voltage jump amplitude at the operational amplifier's input terminal reaches the preset threshold, the on-resistance of the first detection switch is less than that of the second detection switch, and the common-mode detection circuit outputs a second signal. By utilizing the change in the on-resistance of the first detection switch, the voltage jump detection at the operational amplifier's input terminal is achieved, thereby realizing effective detection of PWM wave common-mode signals, enabling the operational amplifier to enhance and suppress PWM wave common-mode signals. Simultaneously, by setting a detection threshold through a preset bias voltage, the possibility of false triggering is reduced, detection accuracy is ensured, and the safety and reliability of the operational amplifier are guaranteed.

[0043] This invention also provides a control circuit that has the same beneficial effects as the common-mode detection circuit described above. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of a common-mode detection circuit provided by this utility model;

[0046] Figure 2 A schematic diagram of the structure of an up-jump detection circuit provided by this utility model;

[0047] Figure 3 This is a schematic diagram of the structure of a jump detection circuit provided by this utility model;

[0048] Figure 4 A schematic diagram of a control circuit provided by this utility model. Detailed Implementation

[0049] The core of this invention is to provide a common-mode detection circuit and control circuit. It utilizes the change in the on-resistance of the first detection switch to detect voltage jumps at the input terminal of the operational amplifier, thereby achieving effective detection of the common-mode signal of the PWM wave, so that the operational amplifier can enhance and suppress the common-mode signal of the PWM wave. At the same time, the detection threshold is set by a preset bias voltage, which reduces the occurrence of false triggers, ensures detection accuracy, and ensures the safety and reliability of the operational amplifier.

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0051] See Figure 1 As shown, Figure 1 This utility model provides a common-mode detection circuit. To solve the above-mentioned technical problems, this utility model provides a common-mode detection circuit, including a first detection switch 1 and a second detection switch 2. The first detection switch 1 and the second detection switch 2 are connected in series, and the first end of the series circuit is connected to the power supply, the second end is grounded, the control end of the first detection switch 1 is connected to the input end of the operational amplifier 3, and the control end of the second detection switch 2 is connected to a preset bias voltage Vb.

[0052] When the voltage at the control terminal of the first detection switch 1 changes by a magnitude greater than a preset threshold within a preset time period, the on-resistance of the first detection switch 1 is less than the on-resistance of the second detection switch 2; when the voltage at the control terminal of the first detection switch 1 changes by a magnitude less than or equal to a preset threshold within a preset time period, the on-resistance of the first detection switch 1 is greater than the on-resistance of the second detection switch 2.

[0053] It is easy to understand that, considering that the dynamic common-mode signal transition has a more serious and complex impact on the operational amplifier 3 (hereinafter referred to as op-amp), especially when there are switching devices in the circuit connected to the op-amp, its input terminal will be severely affected by the PWM wave common-mode signal. Therefore, this application mainly focuses on detecting the transition common-mode signal and sets up a common-mode detection circuit including a first detection switch 1 and a second detection switch 2. The series connection point of the first detection switch 1 and the second detection switch 2 is used as the output terminal of the common-mode detection circuit. The common-mode signal mainly exists in the form of a common-mode voltage. The control terminal of the first detection switch 1 is connected to the input terminal of the operational amplifier 3. Therefore, the voltage at its control terminal changes with the voltage at the input terminal of the operational amplifier. The first detection switch 1 is a voltage-controlled variable resistor whose conduction degree changes with the control terminal voltage. The control terminal of the second detection switch 2 is connected to a fixed preset bias voltage Vb. Its conduction degree and corresponding on-resistance remain unchanged. When the voltage at the input terminal of the operational amplifier is at a normal state (no voltage jump) or the voltage jump amplitude is relatively small, the conduction degree of the first detection switch 1 is relatively small and the on-resistance is relatively large. The output signal of the common-mode detection circuit is pulled down or pulled up by the second detection switch 2, which has a larger conduction degree. When the voltage jump amplitude at the input terminal of the operational amplifier is relatively large, the voltage at the control terminal of the first detection switch 1 suddenly increases or suddenly decreases. With the large jump of the control terminal voltage, the conduction degree of the first detection switch 1 increases and the on-resistance decreases. The output signal of the common-mode detection circuit is pulled up or pulled down by the first detection switch 1, which has a larger conduction degree.

[0054] It should be noted that this application does not impose any special limitations on the specific types and implementation methods of the first detection switch 1 and the second detection switch 2. They can be implemented using switching devices such as MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors). The first detection switch 1 can also be implemented using other types of variable resistor devices. This application mainly uses MOS transistors as an example for explanation. There are multiple choices for the specific value and implementation method of the preset bias voltage Vb. This application does not impose any special limitations on it. The on-resistance of the second detection switch 2 mainly depends on the magnitude of the preset bias voltage Vb. This application does not impose any special limitations on the specific type and implementation method of the operational amplifier 3. The common-mode detection circuit can be applied to various types of operational amplifiers 3, such as current sensing amplifiers. This application does not impose any special limitations on the specific type and implementation method of the power supply. The power supply of the operational amplifier can be directly reused.

[0055] Furthermore, when both the first detection switch 1 and the second detection switch 2 are implemented using switching devices, the change in the on-resistance of the first detection switch 1 can be achieved by utilizing different conduction levels of the switching devices, or directly by utilizing the on or off state of the switching devices. A preferred embodiment is to utilize different conduction levels of the switching devices, with both the first detection switch 1 and the second detection switch 2 remaining in the on state. Current always exists in the series circuit, allowing the conduction level of the first detection switch 1 to change in real time with the change in the control terminal voltage, ensuring rapid detection of common-mode voltage jumps. However, the conduction level of the first detection switch 1 will change with the change in the control terminal voltage, and the greater the change in the control terminal voltage, the smaller the on-resistance of the first detection switch 1. If the on or off state of the switching devices is directly utilized, when the voltage jump amplitude of the control terminal of the first detection switch 1 within a preset time period is less than or equal to a preset threshold, the first detection switch 1 is turned off; when the voltage jump amplitude of the control terminal of the first detection switch 1 within a preset time period is greater than the preset threshold, the first detection switch 1 is turned on, and the second detection switch 2 remains in the normally on state. This application does not impose any special restrictions on the specific values ​​and implementation methods of the preset time period and preset threshold. Voltage jump refers to the process of voltage rapidly changing from one steady state to another, which represents a significant change in voltage in a short period of time. Therefore, the value of the preset time period is generally relatively small, mainly detecting the phenomenon of voltage jump in common-mode signals in a short time or even instantaneously. The preset threshold can be set and adjusted according to the actual application scenario of the operational amplifier.

[0056] Understandably, the control terminal of the first detection switch 1 is directly connected to the input terminal of the operational amplifier. Once there is a voltage jump at the input terminal of the operational amplifier, the common-mode detection circuit can output a corresponding detection signal. The detection signal is directly output to the operational amplifier 3, enabling the operational amplifier and its peripheral circuits to respond promptly and execute the corresponding suppression strategy, thereby achieving enhanced suppression of common-mode signals. In the presence of common-mode signals, its impact on the operational amplifier output or signal transmission is minimized. The on-resistance of the first detection switch 1 responds quickly to the voltage change at the control terminal, ensuring the common-mode suppression effect. The second detection switch 2 maintains a fixed on-resistance to provide a signal reference for the common-mode detection circuit. The on-resistance of the second detection switch 2 helps to achieve the setting of the preset threshold. The on-resistance of the second detection switch 2 is negatively correlated with the preset threshold. The larger the voltage jump amplitude to be detected, the larger the preset threshold, and the smaller the on-resistance of the second detection switch 2. The more difficult it is for the on-resistance of the first detection switch 1 to be less than the on-resistance of the second detection switch 2. Only when the voltage jump reaches a certain level can the on-resistance of the first detection switch 1 be less than the on-resistance of the second detection switch 2, thus achieving jump detection. Therefore, the preset threshold can be set by adjusting the preset bias voltage Vb.

[0057] This invention provides a common-mode detection circuit that utilizes the correspondence between the on-resistance of the first detection switch 1 and the control terminal voltage to detect common-mode signals. It also allows setting a preset bias voltage Vb to establish a detection threshold for common-mode signals at the op-amp input, effectively preventing false triggering of the common-mode detection circuit during normal op-amp operation. This circuit enables rapid detection of common-mode signals at the op-amp input, allowing the op-amp to process them accordingly, thereby suppressing and enhancing common-mode signals, especially PWM wave common-mode signals. It optimizes the detection time for common-mode detection. Furthermore, the entire circuit structure is simple and easy to implement, simplifying the common-mode detection process and mitigating the impact of common-mode signals on op-amp operation to a certain extent, thus expanding the op-amp's operating scenarios and application range.

[0058] Based on the above embodiments: see Figure 2 As shown, Figure 2 A schematic diagram of the structure of an up-jump detection circuit provided by this utility model; see also Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a jump detection circuit provided by this utility model;

[0059] As an optional embodiment, the preset threshold includes a first threshold and a second threshold, the preset bias voltage Vb includes a first bias voltage Vbp and a second bias voltage Vbn; the first detection switch 1 includes a first NMOS transistor MN1 and a first PMOS transistor MP1, and the second detection switch 2 includes a second PMOS transistor MP2 and a second NMOS transistor MN2.

[0060] The control terminal of the first NMOS transistor MN1 is connected to the input terminal of the operational amplifier 3. The first terminal is grounded, and the second terminal is connected to the first terminal of the second PMOS transistor MP2 and serves as the first output terminal of the common-mode detection circuit. The second terminal of the second PMOS transistor MP2 is connected to the power supply, and the control terminal is connected to the first bias voltage Vbp.

[0061] When the voltage at the control terminal of the first NMOS transistor MN1 increases by more than the first threshold within a preset time period, the on-resistance of the first NMOS transistor MN1 is less than the on-resistance of the second PMOS transistor MP2; when the voltage at the control terminal of the first NMOS transistor MN1 increases by less than or equal to the first threshold within a preset time period, the on-resistance of the first NMOS transistor MN1 is greater than the on-resistance of the second PMOS transistor MP2.

[0062] The control terminal of the first PMOS transistor MP1 is connected to the input terminal of the operational amplifier 3. The first terminal is connected to the power supply, and the second terminal is connected to the first terminal of the second NMOS transistor MN2, and serves as the second output terminal of the common-mode detection circuit. The second terminal of the second NMOS transistor MN2 is grounded, and the control terminal is connected to the second bias voltage Vbn.

[0063] When the voltage at the control terminal of the first PMOS transistor MP1 decreases by a greater than the second threshold within a preset time period, the on-resistance of the first PMOS transistor MP1 is less than the on-resistance of the second NMOS transistor MN2; when the voltage at the control terminal of the first PMOS transistor MP1 decreases by a less than or equal to the second threshold within a preset time period, the on-resistance of the first PMOS transistor MP1 is greater than the on-resistance of the second NMOS transistor MN2.

[0064] Understandably, considering that voltage transitions include both upward and downward transitions, the common-mode detection circuit is equipped with an upward transition detection module comprising a first NMOS transistor MN1 and a second PMOS transistor MP2, and a downward transition detection module comprising a first PMOS transistor MP1 and a second NMOS transistor MN2. The upward transition detection module is connected in parallel between the two input terminals of the operational amplifier, and the downward transition detection module is connected in parallel between the two input terminals of the operational amplifier. Both the NMOS and PMOS transistors in this application are enhancement-mode MOS transistors. Throughout the detection process, the second PMOS transistor MP2 and the second NMOS transistor MN2 can operate in the saturation region under the corresponding first or second bias voltage, continuously providing uninterrupted bias current for the detection process. When a voltage transition occurs at the operational amplifier input terminal, the detection circuit with current present responds faster and can more quickly detect the common-mode voltage transition.

[0065] For voltage jumps at the op-amp input, a jump refers to a sudden increase in voltage over a short period. The conduction level of the first NMOS transistor MN1 increases with the increase of the gate (control terminal) voltage, while its on-resistance decreases. Its gate is connected to the op-amp input. When there is no voltage jump at the op-amp input or the jump amplitude is not greater than the first threshold, the conduction level of the first NMOS transistor MN1 is less than that of the second PMOS transistor MP2. In this case, the first output of the common-mode detection circuit is connected to the source (the second terminal of the second PMOS transistor MP2) of the power supply, which has a higher conduction level. When MP2 goes high, the first output terminal OUT1 outputs a first signal, indicating that there is no significant common-mode voltage jump at the op-amp input. When there is a voltage jump at the op-amp input and the jump amplitude is greater than the first threshold, the conduction level of the first NMOS transistor MN1 will switch from a state less than that of the second PMOS transistor MP2 to a state greater than that of the second PMOS transistor MP2. At this time, the first output terminal of the common-mode detection circuit will be pulled low by the first NMOS transistor MN1, which has a higher conduction level and whose source (first terminal) is grounded. The first output terminal OUT1 outputs a second signal, indicating that there is a significant common-mode voltage jump at the op-amp input. The first and second signals can be implemented using level signals or other methods, which are not specifically limited in this application. For example, the first signal can be high level and the second signal can be low level.

[0066] For the voltage drop at the op-amp input, a drop refers to a sudden decrease in voltage over a short period of time. The conduction level of the first PMOS transistor MP1 decreases as the gate (control terminal) voltage increases, while its on-resistance increases as the gate voltage increases. Its gate is connected to the op-amp input. When there is no voltage drop at the op-amp input or the drop amplitude is not greater than the second threshold, the conduction level of the first PMOS transistor MP1 is less than that of the second NMOS transistor MN2. In this case, the first output terminal of the common-mode detection circuit will be pulled up by the second NMOS transistor MN2, which has a higher conduction level and whose source (the second terminal of the second NMOS transistor MN2) is grounded. When the voltage drop at the op-amp input is low, the second output terminal OUT2 outputs a third signal, indicating that there is no significant common-mode voltage drop at the op-amp input. When there is a voltage drop at the op-amp input and the drop amplitude is greater than the second threshold, the conduction level of the first PMOS transistor MP1 will switch from a state less than that of the second NMOS transistor MN2 to a state greater than that of the second NMOS transistor MN2. At this time, the second output terminal of the common-mode detection circuit will be pulled high by the first PMOS transistor MP1, whose source (first terminal) is connected to the power supply and has a higher conduction level. The second output terminal OUT2 outputs a fourth signal, indicating that there is a significant common-mode voltage drop at the op-amp input. The third and fourth signals can be implemented using level signals or other methods, which are not specifically limited in this application. For example, the third signal can be low and the fourth signal can be high.

[0067] It should be noted that this application does not impose any special limitations on the specific values ​​and implementation methods of the first and second thresholds. A preferred embodiment is that the first threshold and the second threshold are equal. Similarly, this application does not impose any special limitations on the specific values ​​and implementation methods of the first and second bias voltages. Furthermore, this application does not impose any special limitations on the specific types and implementation methods of the first NMOS transistor MN1, the second PMOS transistor MP2, the first PMOS transistor MP1, and the second NMOS transistor MN2. A preferred embodiment is that the first NMOS transistor MN1 and the second NMOS transistor MN2 are implemented using NMOS transistors of the same type and specifications, and the first PMOS transistor MP1 and the second PMOS transistor MP2 are implemented using PMOS transistors of the same type and specifications.

[0068] Specifically, by independently setting up an up-switch detection module for detecting common-mode voltage up-switch and a down-switch detection module for detecting common-mode voltage down-switch, accurate detection of different common-mode voltage transition states can be achieved. When the common-mode voltage changes rapidly and significantly, it can be quickly detected by the voltage change at the control terminal of the corresponding first NMOS transistor MN1 or first PMOS transistor MP1, which greatly shortens the response time and ensures that the operational amplifier output remains stable even under large common-mode voltage changes. The circuit structure is simple and easy to implement.

[0069] As an optional embodiment, it also includes:

[0070] The first capacitor C1 has its first terminal connected to the non-inverting input terminal of the operational amplifier 3;

[0071] The second capacitor C2 has its first end connected to the inverting input terminal of the operational amplifier 3, and its second end connected to the second end of the first capacitor C1 and the control terminal of the first NMOS transistor MN1.

[0072] The first terminal of the third capacitor C3 is connected to the non-inverting input terminal of the operational amplifier 3;

[0073] The fourth capacitor C4 has its first end connected to the inverting input of operational amplifier 3, and its second end connected to the second end of the third capacitor C3 and the control terminal of the first PMOS transistor MP1.

[0074] It is easy to understand that, to avoid the influence of the op-amp's input voltage on the common-mode detection circuit during normal operation, capacitors can be added between the op-amp input and the common-mode detection circuit. Specifically, this includes a first capacitor C1 and a second capacitor C2 between the op-amp and the up-switch detection module, and a third capacitor C3 and a fourth capacitor C4 between the op-amp and the down-switch detection module. For a stable DC signal at the op-amp's input during normal operation, the capacitors act as an open circuit, preventing the signal from passing through. However, for common-mode voltage transitions, the capacitors charge and discharge due to voltage changes, thus coupling the transition signal into the common-mode detection circuit. This application does not specifically limit the specific types and implementation methods of the first capacitor C1, second capacitor C2, third capacitor C3, and fourth capacitor C4.

[0075] Specifically, coupling via capacitors ensures the common-mode detection circuit is sensitive only to rapidly changing common-mode signals, preventing false triggering. The common-mode detection circuit rapidly detects common-mode voltage jumps through voltage abrupt changes across the capacitors, significantly shortening the response time and achieving rapid detection of common-mode changes. The circuit structure is simple and easy to implement, achieving DC signal isolation between the operational amplifier and the common-mode detection circuit, thus protecting the common-mode detection circuit.

[0076] As an optional embodiment, it also includes:

[0077] The first bias voltage generation module has its output terminal connected to the control terminal of the second PMOS transistor MP2, and is used to output the first bias voltage.

[0078] And / or,

[0079] The second bias voltage generation module has its output terminal connected to the control terminal of the second NMOS transistor MN2, and is used to output the second bias voltage.

[0080] It is understandable that, in order to ensure that the second detection switch 2 can operate stably at a specific operating point corresponding to a preset threshold, a first bias voltage generation module can be directly set in the common-mode detection circuit to generate the first bias voltage required by the second PMOS transistor MP2 in the up-jump detection module, and a second bias voltage generation module can be set to generate the second bias voltage required by the second NMOS transistor MN2 in the down-jump detection module. This application does not specifically limit the specific types and implementation methods of the first and second bias voltage generation modules.

[0081] Specifically, by adding a first bias voltage generation module and a second bias voltage generation module, it is possible to ensure that the second detection switch 2 in the two detection modules operates at a specific operating point corresponding to the preset threshold, and to ensure that the second detection switch 2 always operates at the on-resistance corresponding to the preset threshold. Furthermore, the preset threshold can be set and adjusted by adjusting the first bias voltage generation module and the second bias voltage generation module, which is more flexible and has a wider range of applications.

[0082] As an optional embodiment, the first bias voltage generation module includes a first current source I1 and a third PMOS transistor MP3. The input terminal of the first current source I1 is connected to the first terminal of the third PMOS transistor MP3, the control terminal of the third PMOS transistor MP3, and the control terminal of the second PMOS transistor MP2. The output terminal of the first current source I1 is grounded, and the second terminal of the third PMOS transistor MP3 is connected to the power supply.

[0083] The second bias voltage generation module includes a second current source I2 and a third NMOS transistor MN3. The output terminal of the second current source I2 is connected to the first terminal of the third NMOS transistor MN3, the control terminal of the third NMOS transistor MN3, and the control terminal of the second NMOS transistor MN2. The second terminal of the third NMOS transistor MN3 is grounded.

[0084] It is easy to understand that a current source can be used to achieve a stable bias voltage output, while a current mirror structure is configured to output the bias voltage to the control terminal of the corresponding second detection switch 2. The current source can output a stable reference current. The third PMOS transistor MP3 and the second PMOS transistor MP2 form a set of current mirrors. The reference current output by the first current source I1 can be accurately replicated to the series circuit formed by the second PMOS transistor MP2 and the first NMOS transistor MN1 through this set of current mirrors. The third NMOS transistor MN3 and the second NMOS transistor MN2 form a set of current mirrors. The reference current output by the first current source I1 can be accurately replicated to the series circuit formed by the second NMOS transistor MN2 and the first PMOS transistor MP1 through this set of current mirrors. Thus, the combination of the current source and the current mirrors provides a stable bias current and bias voltage for the second detection switch 2.

[0085] Furthermore, the preset threshold can be adjusted by changing the ratio of the current mirror in the bias voltage generation module. By adjusting the ratio of the current mirror, different magnitudes of bias current and bias voltage are distributed to the second detection switch 2, thereby controlling the second detection switch 2 to maintain different conduction levels and corresponding different on-resistances, thus achieving the design and adjustment of the preset threshold. This application does not impose any special limitations on the specific types, output current magnitudes, or implementation methods of the first current source I1 and the second current source I2, nor does it impose any special limitations on the specific types and implementation methods of the third PMOS transistor MP3 and the third NMOS transistor MN3.

[0086] Specifically, the bias voltage corresponding to the second detection switch 2 can be effectively adjusted by using the current mirror ratio, thereby setting a preset threshold. When the common-mode voltage change at the op-amp input exceeds this preset threshold, the common-mode detection circuit will immediately respond and output a corresponding signal to operate the op-amp. The reference current output by the current source has stronger stability, which can ensure the stability and reliability of the generated bias voltage, improve the anti-interference capability of the entire common-mode detection circuit, and make it more flexible and adjustable with the current mirror structure, so as to adapt to various scenario requirements. The bias path implemented by the current mirror has a fast response speed, which can ensure the response speed of the common-mode detection circuit. The entire circuit structure is simple and easy to implement.

[0087] As an optional embodiment, it also includes:

[0088] The fourth NMOS transistor MN4 has its first terminal grounded.

[0089] The first terminal of the fourth PMOS transistor MP4 is connected to the second terminal of the fourth NMOS transistor MN4, the control terminal of the fourth NMOS transistor MN4, the input terminal of the operational amplifier 3, and the control terminal of the first NMOS transistor MN1. The control terminal is connected to the control terminal of the third PMOS transistor MP3 and the first terminal of the third PMOS transistor MP3. The second terminal is connected to the power supply.

[0090] The fifth PMOS transistor, MP5, has its first terminal connected to the power supply.

[0091] The first terminal of the fifth NMOS transistor MN5 is connected to the second terminal of the fifth PMOS transistor MP5, the control terminal of the fifth PMOS transistor MP5, the input terminal of the operational amplifier 3, and the control terminal of the first PMOS transistor MP1. The control terminal is connected to the control terminal of the third NMOS transistor MN3 and the first terminal of the third NMOS transistor MN3. The second terminal is grounded.

[0092] Understandably, to ensure that the first detection switch 1 remains on throughout the detection process, it is necessary to add a fourth NMOS transistor MN4 and a fourth PMOS transistor MP4 to the up-jump detection module, and a fifth PMOS transistor MP5 and a fifth NMOS transistor MN5 to the down-jump detection module. The control terminal of the fourth PMOS transistor MP4 is connected to the control terminal of the third PMOS transistor MP3, forming a current mirror structure with the third PMOS transistor MP3. Therefore, the fourth PMOS transistor MP4 can remain on under the action of the first bias voltage, while providing a stable bias current for the fourth NMOS transistor MN4 and the first NMOS transistor MN1. This allows the fourth NMOS transistor MN4 and the first NMOS transistor MN1 to remain on based on the first bias voltage even when the op-amp is operating normally, providing a stable initial operating point for the first NMOS transistor MN1 before common-mode detection. The current mirror structure formed by the third PMOS transistor MP3 and the fourth PMOS transistor MP4 can also be configured with a current mirror structure formed by the third PMOS transistor MP3 and the second PMOS transistor MP2 to configure the on-resistance of the first NMOS transistor MN1 in the initial state, ensuring that the on-resistance of the first NMOS transistor MN1 is greater than that of the second PMOS transistor MP2 in the initial state. The role of the fifth PMOS transistor MP5 in the down-jump detection module is similar to that of the fourth NMOS transistor MN4 in the up-jump detection module, and the role of the fifth NMOS transistor MN5 in the down-jump detection module is similar to that of the fourth PMOS transistor MP4 in the up-jump detection module. These details will not be elaborated further here. The specific types and implementation methods of the fourth NMOS transistor MN4, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the fifth NMOS transistor MN5 are not specifically limited here.

[0093] It should be noted that the ratio of the current mirror structure formed by the third PMOS transistor MP3 and the fourth PMOS transistor MP4 and the current mirror structure formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4 will be set to 1, and the ratio of the current mirror structure formed by the third PMOS transistor MP3 and the second PMOS transistor MP2 and the current mirror structure formed by the third NMOS transistor MN3 and the second NMOS transistor MN2 will be set to greater than 1, so that the on-resistance of the first detection switch 1 in the initial state is greater than the on-resistance of the second detection switch 2.

[0094] Specifically, by adding a fourth NMOS transistor MN4, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a fifth NMOS transistor MN5, the initial state of the first detection switch 1 is set, ensuring that the first detection switch 1 can always remain in the conducting state, and common-mode detection is achieved solely through changes in its own conduction degree; structural detection is easy to implement.

[0095] As an optional embodiment, it also includes:

[0096] The first current limiting module RX1 has its first terminal connected to the input terminal of the operational amplifier 3, and its second terminal connected to the control terminal of the first NMOS transistor MN1.

[0097] And / or,

[0098] The second current limiting module RX2 has its first end connected to the input terminal of the operational amplifier 3, and its second end connected to the control terminal of the first PMOS transistor MP1.

[0099] It is easy to understand that, to further protect the common-mode detection circuit, a first current-limiting module RX1 can be added between the op-amp input and the common-mode detection circuit to protect the up-switch detection module, and a second current-limiting module RX2 can be added to protect the down-switch detection module. The first current-limiting module RX1 and the second current-limiting module RX2 can limit the current output to the control terminal of the first detection switch 1, avoiding safety risks such as damage to the first detection switch 1 caused by excessive current and voltage surges. This application does not specifically limit the specific type and implementation method of the first current-limiting module RX1 and the second current-limiting module RX2, such as... Figure 2 and Figure 3 As shown, this can be achieved using a resistive element.

[0100] Specifically, by setting the first current limiting module RX1 and the second current limiting module RX2, the safety of the common mode detection circuit can be further protected, avoiding safety risks such as damage to components in the common mode detection circuit, and improving the service life of the common mode detection circuit.

[0101] As an optional embodiment, it also includes:

[0102] The first inverter has its input terminal connected to the second terminal of the first NMOS transistor MN1 and the first terminal of the second PMOS transistor MP2, respectively.

[0103] And / or,

[0104] The second inverter has its input terminals connected to the second terminal of the first PMOS transistor MP1 and the first terminal of the second NMOS transistor MN2, respectively.

[0105] It is understandable that, in order to ensure that the operational amplifier can effectively receive the output signal of the common-mode detection circuit, an inverter can be further added to the output terminal of the common-mode detection circuit. Specifically, this includes a first inverter connected to the first output terminal corresponding to the up-jump detection module and a second inverter connected to the second output terminal corresponding to the down-jump detection module. The inverter can improve the driving capability of the output signal of the common-mode detection circuit and avoid signal distortion and other abnormalities that may occur if the output signal of the series connection point of the first detection switch 1 and the second detection switch 2 is directly output. This application does not specifically limit the specific type and implementation method of the first and second inverters, such as... Figure 2 As shown, the first inverter can be implemented using a sixth PMOS transistor MP6 and a sixth NMOS transistor MN6 connected in series. The control terminals of both the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are connected to the series connection point of the first NMOS transistor MN1 and the second PMOS transistor MP2. The series connection point of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 serves as the first output terminal of the common-mode detection circuit. Figure 3 As shown, the second inverter can be implemented using a seventh PMOS transistor MP7 and a seventh NMOS transistor MN7 connected in series. The control terminals of the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are both connected to the series connection point of the first PMOS transistor MP1 and the second NMOS transistor MN2. The series connection point of the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 serves as the second output terminal of the common-mode detection circuit.

[0106] Specifically, by adding an inverter, the driving capability of the common-mode detection circuit output signal is improved, thereby enhancing the accuracy and reliability of the common-mode detection signal output to the operational amplifier, and further ensuring the stability and reliability of the common-mode detection results.

[0107] In one specific embodiment, all NMOS transistors in the common-mode detection circuit are implemented using NMOS transistors of the same type and specification, and all PMOS transistors are implemented using PMOS transistors of the same type and specification. The power supply is set to VS. Figure 2 As shown, for the jump detection module, when the input terminals of the operational amplifier (including the non-inverting input terminal IN+ and the inverting input terminal IN-) are in normal condition, the potential at point B, the control terminal of the first NMOS transistor MN1, is VB = ((2I b1 / K n ) 1 / 2 +V THn , where I b1 K is the reference current output by the first current source I1. n V represents the transconductance parameters of the final NMOS transistor of the same specification (in this formula, it actually represents the transconductance parameters of the fourth NMOS transistor MN4). THnThe threshold voltage of the NMOS transistor of the same specification used in the final application (in this formula, it is actually the threshold voltage of the fourth NMOS transistor MN4); at this time, point B is at a low potential, the on-resistance of the first NMOS transistor MN1 is greater than the on-resistance of the second PMOS transistor MP2, and point C will be pulled to a high potential by the second PMOS transistor MP2. After passing through the first inverter, the first output terminal OUT1 outputs a low potential.

[0108] When the op-amp input transitions from low voltage to high voltage (upward jump), the voltage across the first capacitor C1 and the second capacitor C2 changes abruptly. The potential at point A changes abruptly as the input voltage increases, and the voltage at point A increases accordingly. After passing through the first current limiting module RX1, the potential at point B also increases. Once the voltage increase reaches the first threshold, the on-resistance of the first NMOS transistor MN1 is less than the on-resistance of the second PMOS transistor MP2, and the current flowing through the first NMOS transistor MN1 is greater than the current flowing through the second PMOS transistor MP2. The first NMOS transistor MN1 will pull point C low. After passing through the first inverter, the output signal at the first output terminal OUT1 will change from a low potential to a high potential.

[0109] In practical applications, the common-mode voltage at the op-amp input may exhibit some ripple and unclean glitches. To prevent small transitions in the common-mode voltage at the op-amp input (caused by ripple or unclean glitches), the common-mode detection circuit internally sets a first threshold to avoid false triggering in this situation. The reference current output by the first current source I1 is I... b1 Therefore, when the op-amp input is in normal operation, the current flowing through the first NMOS transistor MN1 is I. b1 Let the current mirror ratio between the second PMOS transistor MP2 and the third PMOS transistor MP3 be n, and the current flowing through the second PMOS transistor MP2 be nI. b1 Therefore, only when the voltage suddenly changes to more than (2nI) b1 / K n1 ) 1 / 2 -(2I b1 / K n4 ) 1 / 2 +V THn1 -V THn4 =(2nI b1 / K n ) 1 / 2 -(2I b1 / K n ) 1 / 2 Only when the on-resistance of the first NMOS transistor MN1 is less than the on-resistance of the second PMOS transistor MP2 will K be present; where K n1 K represents the transconductance parameter of the first NMOS transistor MN1. n4V represents the transconductance parameter of the fourth NMOS transistor MN4. THn1 V is the threshold voltage of the first NMOS transistor MN1. THn4 K is the threshold voltage of the fourth NMOS transistor MN4. n The transconductance parameters are for the NMOS transistors of the same specifications that will be used in the final application.

[0110] On the other hand, such as Figure 3 As shown, for the down-jump detection module, when the input of the op-amp is in normal condition, the potential at point B is VB = (VS - (2I) / ( ... b2 / K P ) 1 / 2 -V THp ), where I b2 K is the reference current output by the second current source I2. P V represents the transconductance parameter of the final PMOS transistor of the same specification (in this formula, it is actually the transconductance parameter of the fifth PMOS transistor MP5). THp The threshold voltage of the PMOS transistor of the same specification used in the final application (in this formula, it is actually the threshold voltage of the fifth PMOS transistor MP5); at this time, point B is at a high potential, the on-resistance of the first PMOS transistor MP1 is greater than the on-resistance of the second NMOS transistor MN2, and point C will be pulled to a low potential by the second NMOS transistor MN2. After passing through the second inverter, the second output terminal OUT2 outputs a high potential.

[0111] When the op-amp's input terminal experiences a voltage jump from high to low (downward transition), the voltage across the third capacitor C3 and the fourth capacitor C4 changes abruptly. The potential at point A will change abruptly as the input voltage decreases, and the voltage at point A will decrease accordingly. After passing through the second current limiting module RX2, the potential at point B will also decrease. Once the voltage decrease reaches the second threshold, the on-resistance of the first PMOS transistor MP1 is less than the on-resistance of the second NMOS transistor MN2, and the current flowing through the first PMOS transistor MP1 is greater than the current flowing through the second NMOS transistor MN2. The first PMOS transistor MP1 will pull point C high. After passing through the second inverter, the output signal at the second output terminal OUT2 will change from a high potential to a low potential.

[0112] In practical applications, the common-mode voltage at the op-amp input may exhibit some ripple and unclean glitches. To prevent small transitions in the common-mode voltage at the op-amp input (caused by ripple or unclean glitches), a second threshold is set internally in the common-mode detection circuit to avoid false triggering in this situation. The reference current output by the second current source I2 is I. b2 Therefore, when the op-amp input is in normal operation, the current flowing through the first PMOS transistor MP1 is I. b2Let the current mirror ratio between the second NMOS transistor MN2 and the third NMOS transistor MN3 be n, and the current flowing through the second NMOS transistor MN2 be nI. b2 Therefore, only when the voltage suddenly changes to more than (2nI) b2 / K P1 ) 1 / 2 -(2I b2 / K P4 ) 1 / 2 +V THp1 -V THp4 =(2nI b2 / K P ) 1 / 2 -(2I b2 / K P ) 1 / 2 Only when the on-resistance of the first PMOS transistor MP1 is less than the on-resistance of the second NMOS transistor MN2 will K be present; where K P1 K represents the transconductance parameter of the first PMOS transistor MP1. P4 V represents the transconductance parameter of the fourth PMOS transistor MP4. THp1 V is the threshold voltage of the first PMOS transistor MP1. THp4 K is the threshold voltage of the fourth PMOS transistor MP4. P The transconductance parameters are for the PMOS transistors of the same specifications that will be used in the final application.

[0113] See Figure 4 As shown, Figure 4 This utility model provides a schematic diagram of a control circuit. To solve the above-mentioned technical problems, this utility model also provides a control circuit, including an operational amplifier 3, a first controllable switch S1, a second controllable switch S2, and a common-mode detection circuit as described above;

[0114] The output terminal of the common-mode detection circuit is connected to the control terminal of the first controllable switch S1 and the control terminal of the second controllable switch S2, respectively. The first terminal of the first controllable switch S1 is connected to the input terminal of the common-mode detection circuit and the first terminal of the measuring resistor Rm, respectively, and the second terminal is connected to the non-inverting input terminal of the operational amplifier 3. The first terminal of the second controllable switch S2 is connected to the input terminal of the common-mode detection circuit and the second terminal of the measuring resistor Rm, respectively, and the second terminal is connected to the inverting input terminal of the operational amplifier 3.

[0115] The first controllable switch S1 is used to turn off when the common-mode detection circuit detects that the voltage jump amplitude is greater than a preset threshold within a preset time period.

[0116] The second controllable switch S2 is used to turn off when the common-mode detection circuit detects that the voltage jump amplitude is greater than the preset threshold within a preset time period.

[0117] It is understandable that the suppression strategy of the op-amp after receiving the common-mode detection signal can also be implemented in the control circuit by adding a first controllable switch S1 and a second controllable switch S2 in the peripheral circuit. When there is no common-mode voltage change at the op-amp input or the common-mode voltage change is small, the impact on the op-amp output voltage is limited. At this time, the common-mode detection circuit does not function, and the stability of the op-amp output voltage can be ensured by internal adjustment through the op-amp's own feedback structure. When a large change in common-mode voltage occurs at the op-amp input, the common-mode detection circuit immediately detects the change in the common-mode signal. The common-mode detection signal output by the common-mode detection circuit can promptly control the first controllable switch S1 and the second controllable switch S2 to turn off, thereby preventing the op-amp input from receiving the input signal and achieving the effect of common-mode suppression. This application does not make any special limitations on the specific type and implementation method of the first controllable switch S1 and the second controllable switch S2.

[0118] For a description of the control circuit provided by this utility model, please refer to the above-described embodiment of the common-mode detection circuit; this utility model will not be described in detail here.

[0119] As an optional embodiment, it also includes:

[0120] The third controllable switch S3 has its first end connected to the non-inverting input terminal of the operational amplifier 3 and the second end of the first controllable switch S1, respectively. The second end is connected to a preset reference voltage and is used to turn on when the common-mode detection circuit detects that the jump amplitude is greater than a preset threshold within a preset time period.

[0121] The first terminal of the fourth controllable switch S4 is connected to the inverting input terminal of the operational amplifier 3 and the second terminal of the second controllable switch S2. The second terminal is connected to a preset reference voltage and is used to turn on when the common-mode detection circuit detects that the jump amplitude is greater than a preset threshold within a preset time period.

[0122] It is easy to understand that after controlling the op-amp's input terminal to not accept input signals based on the common-mode detection signal, the op-amp will subsequently resume operation based on the common-mode detection circuit or operational requirements. To improve the recovery speed of the op-amp when resuming operation, the common-mode detection signal output by the common-mode detection circuit, while controlling the op-amp's input terminal to not accept input signals, also controls the third controllable switch S3 and the fourth controllable switch S4 to conduct, setting the voltage at the two input terminals of the op-amp to a preset reference voltage. This preset reference voltage provides a reference voltage for the op-amp's input terminal when it stops operating, preventing voltage deviation and other abnormalities at the op-amp's input terminal when it stops operating. This application does not specifically limit the specific value or implementation method of the preset reference voltage; it can be directly implemented by the internal common-mode voltage generated within the op-amp. Similarly, this application does not specifically limit the specific type or implementation method of the third controllable switch S3 and the fourth controllable switch S4. This application does not specifically limit the specific control methods for each controllable switch. Drive signals for each controllable switch can be specifically generated by setting a drive signal generation module in the control circuit. The drive signals for the first controllable switch S1 and the second controllable switch S2 are the same drive signal, and the drive signals for the third controllable switch S3 and the fourth controllable switch S4 are the same drive signal. The drive signal for the third controllable switch S3 can directly use the non-signal of the drive signal for the first controllable switch S1, such as... Figure 4 The CTRL signal shown, which is the drive signal of the third controllable switch S3, is completely opposite to the drive signal of the first controllable switch S1.

[0123] Furthermore, this application does not impose any special limitations on the peripheral circuitry of the operational amplifier, etc., which can be set and adjusted according to actual application requirements. As a specific embodiment, such as... Figure 4As shown, taking the application scenario of the first operational amplifier U1 and the second operational amplifier U2 connected in series as an example, since the common-mode signal mainly targets the input terminal of the operational amplifier, the common-mode detection circuit only needs to be connected to the input terminal of the first operational amplifier U1. In addition to the first controllable switch S1, the second controllable switch S2, the third controllable switch S3, and the fourth controllable switch S4, the peripheral circuit can further set a fifth controllable switch S5, a sixth controllable switch S6, a seventh controllable switch S7, and an eighth controllable switch S8. The fifth controllable switch S5, the sixth controllable switch S6, the seventh controllable switch S7, and the eighth controllable switch S8 are consistent with the operating states of the first controllable switch S1 and the second controllable switch S2. When the first controllable switch S1 and the second controllable switch S2 are turned off, the fifth controllable switch S5, the sixth controllable switch S6, the seventh controllable switch S7, and the eighth controllable switch S8 are turned off, disconnecting the connection between the first operational amplifier U1 and the subsequent second operational amplifier U2, further preventing the second operational amplifier U2 from outputting a signal. Meanwhile, grounded capacitors C31 and C32 are added between the first operational amplifier U1 and the second operational amplifier U2. Capacitors C31 and C32 maintain the voltage value of the connection line between the first operational amplifier U1 and the second operational amplifier U2 after the first controllable switch S1 and the second controllable switch S2 are turned off, ensuring that the voltage of the final output signal OUT does not change abruptly with large fluctuations in the common-mode voltage. Additionally, the peripheral circuit of the second operational amplifier U2 includes resistors R1 and R2 for current limiting, and resistor R3 for feedback. The non-inverting input of the second operational amplifier U2 is connected to an external reference voltage REF through resistor R4. Capacitors C11, C12, C13, and C14 are also included in the peripheral circuit of the first operational amplifier U1 to receive the differential signal across the measuring resistor Rm.

[0124] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0125] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A common-mode detection circuit, characterized in that, It includes a first detection switch and a second detection switch, which are connected in series. The first end of the series circuit is connected to the power supply, and the second end is grounded. The control terminal of the first detection switch is connected to the input terminal of the operational amplifier, and the control terminal of the second detection switch is connected to a preset bias voltage. When the voltage at the control terminal of the first detection switch changes by a greater than a preset threshold within a preset time period, the on-resistance of the first detection switch is less than that of the second detection switch.

2. The common-mode detection circuit according to claim 1, characterized in that, The preset threshold includes a first threshold and a second threshold, and the preset bias voltage includes a first bias voltage and a second bias voltage; the first detection switch includes a first NMOS transistor and a first PMOS transistor, and the second detection switch includes a second PMOS transistor and a second NMOS transistor; The control terminal of the first NMOS transistor is connected to the input terminal of the operational amplifier, the first terminal is grounded, the second terminal is connected to the first terminal of the second PMOS transistor and serves as the first output terminal of the common-mode detection circuit, the second terminal of the second PMOS transistor is connected to the power supply, and the control terminal is connected to the first bias voltage. When the voltage at the control terminal of the first NMOS transistor increases by more than a first threshold within a preset time period, the on-resistance of the first NMOS transistor is less than the on-resistance of the second PMOS transistor; when the voltage at the control terminal of the first NMOS transistor increases by less than or equal to the first threshold within a preset time period, the on-resistance of the first NMOS transistor is greater than the on-resistance of the second PMOS transistor. The control terminal of the first PMOS transistor is connected to the input terminal of the operational amplifier, the first terminal is connected to the power supply, the second terminal is connected to the first terminal of the second NMOS transistor and serves as the second output terminal of the common-mode detection circuit, the second terminal of the second NMOS transistor is grounded, and the control terminal is connected to the second bias voltage. When the voltage at the control terminal of the first PMOS transistor decreases by a greater than a second threshold within a preset time period, the on-resistance of the first PMOS transistor is less than the on-resistance of the second NMOS transistor; when the voltage at the control terminal of the first PMOS transistor decreases by a less than or equal to the second threshold within a preset time period, the on-resistance of the first PMOS transistor is greater than the on-resistance of the second NMOS transistor.

3. The common-mode detection circuit according to claim 2, characterized in that, Also includes: The first capacitor has its first terminal connected to the non-inverting input terminal of the operational amplifier. The second capacitor has its first end connected to the inverting input terminal of the operational amplifier, and its second end connected to the second terminal of the first capacitor and the control terminal of the first NMOS transistor, respectively. The first terminal of the third capacitor is connected to the non-inverting input terminal of the operational amplifier. The fourth capacitor has its first end connected to the inverting input of the operational amplifier, and its second end connected to the second end of the third capacitor and the control terminal of the first PMOS transistor.

4. The common-mode detection circuit according to claim 2, characterized in that, Also includes: The first bias voltage generation module has its output terminal connected to the control terminal of the second PMOS transistor, and is used to output the first bias voltage. And / or, The second bias voltage generation module has its output terminal connected to the control terminal of the second NMOS transistor, and is used to output the second bias voltage.

5. The common-mode detection circuit according to claim 4, characterized in that, The first bias voltage generation module includes a first current source and a third PMOS transistor. The input terminal of the first current source is connected to the first terminal of the third PMOS transistor, the control terminal of the third PMOS transistor, and the control terminal of the second PMOS transistor. The output terminal of the first current source is grounded, and the second terminal of the third PMOS transistor is connected to the power supply. The second bias voltage generation module includes a second current source and a third NMOS transistor. The output terminal of the second current source is connected to the first terminal of the third NMOS transistor, the control terminal of the third NMOS transistor, and the control terminal of the second NMOS transistor. The second terminal of the third NMOS transistor is grounded.

6. The common-mode detection circuit according to claim 5, characterized in that, Also includes: The fourth NMOS transistor has its first terminal grounded. The first terminal of the fourth PMOS transistor is connected to the second terminal of the fourth NMOS transistor, the control terminal of the fourth NMOS transistor, the input terminal of the operational amplifier, and the control terminal of the first NMOS transistor. The control terminal is connected to the control terminal of the third PMOS transistor and the first terminal of the third PMOS transistor. The second terminal is connected to the power supply. The fifth PMOS transistor has its first terminal connected to the power supply. The fifth NMOS transistor has its first terminal connected to the second terminal of the fifth PMOS transistor, the control terminal of the fifth PMOS transistor, the input terminal of the operational amplifier, and the control terminal of the first PMOS transistor. Its control terminal is connected to the control terminal of the third NMOS transistor and the first terminal of the third NMOS transistor. Its second terminal is grounded.

7. The common-mode detection circuit according to claim 2, characterized in that, Also includes: The first current limiting module has a first terminal connected to the input terminal of the operational amplifier and a second terminal connected to the control terminal of the first NMOS transistor. And / or, The second current limiting module has its first end connected to the input terminal of the operational amplifier and its second end connected to the control terminal of the first PMOS transistor.

8. The common-mode detection circuit according to any one of claims 2 to 7, characterized in that, Also includes: The first inverter has its input terminals connected to the second terminal of the first NMOS transistor and the first terminal of the second PMOS transistor, respectively. And / or, The second inverter has its input terminals connected to the second terminal of the first PMOS transistor and the first terminal of the second NMOS transistor, respectively.

9. A control circuit, characterized in that, It includes an operational amplifier, a first controllable switch, a second controllable switch, and a common-mode detection circuit as described in any one of claims 1 to 8; The output terminal of the common-mode detection circuit is connected to the control terminal of the first controllable switch and the control terminal of the second controllable switch, respectively. The first terminal of the first controllable switch is connected to the input terminal of the common-mode detection circuit and the first terminal of the measuring resistor, respectively, and the second terminal is connected to the non-inverting input terminal of the operational amplifier. The first terminal of the second controllable switch is connected to the input terminal of the common-mode detection circuit and the second terminal of the measuring resistor, respectively, and the second terminal is connected to the inverting input terminal of the operational amplifier. The first controllable switch is used to turn off when the common-mode detection circuit detects that the voltage jump amplitude is greater than a preset threshold within a preset time period; The second controllable switch is used to turn off when the common-mode detection circuit detects that the voltage jump amplitude is greater than a preset threshold within a preset time period.

10. The control circuit according to claim 9, characterized in that, Also includes: The third controllable switch has its first end connected to the non-inverting input of the operational amplifier and the second end of the first controllable switch, respectively. The second end is connected to a preset reference voltage and is used to turn on when the common-mode detection circuit detects that the jump amplitude is greater than a preset threshold within a preset time period. The fourth controllable switch has its first end connected to the inverting input of the operational amplifier and the second end of the second controllable switch, respectively, and its second end connected to the preset reference voltage. It is used to turn on when the common-mode detection circuit detects that the jump amplitude is greater than the preset threshold within a preset time period.

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