Power converter circuit and control circuit therefor

Abstract

The power converter circuit includes a control circuit, a pulse generating circuit and a power stage circuit. The power stage circuit generates an output signal at an output node in response to a pulse signal outputted from the pulse generating circuit. The control circuit includes an error amplifier circuit, a comparison circuit, a delay circuit and a detection circuit. The error amplifier circuit outputs a compensation signal in response to a reference signal and a feedback signal related to the output signal. The comparison circuit outputs a duty signal to the pulse generating circuit in response to the compensation signal and a ramp signal. The detection circuit detects a sudden change of the output signal in response to the output signal and a delayed signal generated by the delay circuit from the delayed output signal to generate a reaction signal. The control circuit uses the reaction signal to control the error amplifier circuit or the comparison circuit to change a pulse period of the pulse signal, thereby adjusting the sudden change of the output signal. By generating the reaction signal in response to the sudden change of the output signal, the control circuit changes the pulse period of the pulse signal early to avoid the output signal from having an undershoot or an overshoot.

Description

Technical Field

[0001] This utility model relates to a control circuit, and more particularly to a control circuit for a power converter circuit. Background Technology

[0002] With the development of semiconductor technology, the instantaneous response capability of power converter circuits to load changes has become increasingly important. Some related technologies use a reference signal and a feedback signal related to the output of the power converter circuit to generate an error signal, and compare the error signal with a ramp or sawtooth wave signal to respond to load changes. However, the instantaneous response speed of these related technologies still does not meet user needs. Therefore, it is necessary to propose new circuits to solve the above problems. Utility Model Content

[0003] One embodiment of this utility model is a control circuit. This control circuit is applicable to a power converter circuit. The power converter circuit includes a pulse generation circuit and a power stage circuit. The pulse generation circuit outputs a pulse signal. The power stage circuit generates an output signal at the output node based on the pulse signal. The control circuit includes an error amplifier circuit, a comparator circuit, and an output change detection circuit. The error amplifier circuit is coupled to the output node and outputs a compensation signal based on the difference between a reference signal and a feedback signal associated with the output signal. The comparator circuit is coupled to the error amplifier circuit and outputs a task signal to the pulse generation circuit based on the compensation signal and a ramp signal. It also controls the task signal to have an enable level when the compensation signal exceeds the ramp signal. The output change detection circuit includes a delay circuit and a detection circuit. The delay circuit receives the output signal and delays it to generate a delayed signal. The detection circuit is coupled to at least one of the delay circuit, the error amplifier circuit, and the comparator circuit, and is used to detect sudden changes in the output signal based on the output signal and the delay signal, so as to generate a response signal. The output change detection circuit is used to control the error amplifier circuit or the comparator circuit using the response signal to change the pulse period of the pulse signal, thereby adjusting the sudden change in the output signal.

[0004] In some embodiments, the delay circuit includes a delay unit, and the detection circuit includes a first comparator, a first current generating circuit, and a first switching circuit. The first comparator is coupled to the delay unit and is used to receive the output signal and the delayed signal, and to compare the output signal and the delayed signal to generate a first comparison signal, wherein the first comparison signal has an enable level when the voltage level of the delayed signal is greater than the voltage level of the output signal. The first current generating circuit is coupled to a power supply voltage and is used to generate a charging current. The first switching circuit is coupled to the first current generating circuit and a first node, and is used to switch from an off state to an on state according to the first comparison signal with the enable level, wherein the charging current flows to the first node through the first switching circuit in the on state, and wherein the reaction signal is generated at the first node.

[0005] In some embodiments, the detection circuit further includes a second comparator, a second current generating circuit, and a second switching circuit. The second comparator is coupled to the delay circuit and is used to receive the output signal and the delayed signal, and to compare the output signal and the delayed signal to generate a second comparison signal, wherein the second comparison signal has an enable level when the voltage level of the output signal is greater than the voltage level of the delayed signal. The second current generating circuit is coupled to a ground terminal and is used to generate a discharge current. The second switching circuit is coupled to the second current generating circuit and the first node, and is used to switch from the off state to the on state according to the second comparison signal with the enable level, wherein the discharge current flows from the first node to the ground terminal through the second switching circuit in the on state, and wherein the response signal is the charging current or the discharging current.

[0006] In some embodiments, the delay circuit includes a sample-and-hold circuit, and the detection circuit includes a transconductance amplifier circuit. The transconductance amplifier circuit is coupled to the sample-and-hold circuit to receive the output signal and the delay signal, and to generate a charging current or a discharging current as the response signal based on the output signal and the delay signal.

[0007] In some embodiments, the response signal includes an adjustment current, wherein the control circuit further includes a current-to-voltage conversion circuit coupled to the detection circuit and used to convert the adjustment current into an adjustment voltage, wherein the adjustment voltage is used to adjust the reference signal, the feedback signal, or the ramp signal.

[0008] In some embodiments, the control circuit further includes a subtraction circuit. The subtraction circuit is coupled to one of the inverting input of the error amplifier circuit and the inverting input of the comparator circuit with the current-to-voltage conversion circuit, and is used to subtract the adjustment voltage from one of the feedback signal and the ramp signal.

[0009] In some embodiments, the control circuit further includes an adder circuit. The adder circuit is coupled to the non-inverting input of the error amplifier circuit and the current-to-voltage conversion circuit, and is used to add the adjustment voltage to the reference signal.

[0010] In some embodiments, the response signal includes an adjustment current, wherein the control circuit further includes an adder circuit coupled to the non-inverting input of the comparator circuit and the detection circuit, and is used to add the adjustment current to the error current corresponding to the compensation signal.

[0011] Another embodiment of this utility model is a power converter circuit. The power converter circuit includes a pulse generation circuit, a power stage circuit, and a control circuit. The pulse generation circuit outputs a pulse signal. The power stage circuit is coupled to the output node of the pulse generation circuit and the power converter circuit, and generates an output signal at the output node based on the pulse signal. The control circuit is coupled to the pulse generation circuit and the output node, and includes an error amplifier circuit, a comparator circuit, and an output change detection circuit. The error amplifier circuit is coupled to the output node and outputs a compensation signal based on the difference between a reference signal and a feedback signal associated with the output signal. The comparator circuit is coupled to the error amplifier circuit and outputs a task signal to the pulse generation circuit based on the compensation signal and a ramp signal, and controls the task signal to have an enable level when the compensation signal exceeds the ramp signal. The output change detection circuit includes a delay circuit and a detection circuit. The delay circuit receives the output signal and delays the output signal to generate a delayed signal. The detection circuit is coupled to at least one of the delay circuit, the error amplifier circuit, and the comparator circuit, and is used to detect sudden changes in the output signal based on the output signal and the delay signal, so as to generate a response signal. The output change detection circuit is used to control the error amplifier circuit or the comparator circuit using the response signal to change the pulse period of the pulse signal, thereby adjusting the sudden change in the output signal.

[0012] In some embodiments, the output change detection circuit is coupled to at least one of the error amplifier circuit and the comparator circuit, and is used to adjust the reference signal, the feedback signal, the compensation signal or the ramp signal with the reaction signal to change the pulse period of the pulse signal when the sudden change of the output signal is detected.

[0013] In summary, by generating a response signal in response to a sudden change in the output signal due to a change in the load state (e.g., switching to a heavy load or light load state), the control circuit can preemptively change the pulse period of the pulse signal generated by the pulse generation circuit to avoid undershooting or overshooting of the output signal. Therefore, the power converter circuit and its control circuit of this invention have advantages such as excellent instantaneous load response capability and high power supply stability. Attached Figure Description

[0014] Figure 1 This is a circuit diagram illustrating a power converter circuit according to some embodiments of the present invention.

[0015] Figure 2 This is a timing diagram illustrating some signals related to the operation of a power converter circuit according to some embodiments of the present invention.

[0016] Figure 3A This is a circuit diagram illustrating an output change detection circuit according to some embodiments of the present invention.

[0017] Figure 3B To and Figure 3A Timing diagrams of some signals related to the operation of the output change detection circuit.

[0018] Figure 4 This is a circuit diagram illustrating an output change detection circuit according to some embodiments of the present invention.

[0019] Figure 5 This is a circuit diagram illustrating an output change detection circuit according to some embodiments of the present invention.

[0020] Figure 6 This is a circuit diagram illustrating a delay circuit according to some embodiments of the present invention.

[0021] Figure 7A This is a circuit diagram illustrating an output change detection circuit according to some embodiments of the present invention.

[0022] Figure 7B To and Figure 7A Timing diagrams of some signals related to the operation of the output change detection circuit.

[0023] Figure 8 This is a circuit diagram illustrating an output change detection circuit according to some embodiments of the present invention.

[0024] Figure 9 This is a circuit diagram illustrating a fine-tuning circuit for a comparator according to some embodiments of the present invention.

[0025] Figure 10 This is a circuit diagram illustrating a fine-tuning circuit for a comparator according to some embodiments of the present invention. Detailed Implementation

[0026] The following detailed description of embodiments, in conjunction with the accompanying drawings, is provided. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this utility model.

[0027] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0028] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0029] Please see Figure 1 , Figure 1 This is a circuit diagram illustrating a power converter circuit 100 according to some embodiments of the present invention. Specifically, the power converter circuit 100 may be a DC / DC converter, such as a single-phase or multi-phase buck converter. In some embodiments, the power converter circuit 100 is used to convert the power supply voltage VCC into an output signal OUT at the output node NOUT. The output signal OUT may be a voltage signal. In this way, the power converter circuit 100 can supply power to a load device (not shown) such as a central processing unit (CPU) through the output signal OUT. It should be understood that the load device may be electrically coupled to the output node NOUT.

[0030] In some embodiments, such as Figure 1 As shown, the power converter circuit 100 includes a control circuit 10, a pulse generation circuit 20, and a power stage circuit 30. The power stage circuit 30 includes a drive circuit 310, a high-side switch M1, and a low-side switch M2. Specifically, the high-side switch M1 and the low-side switch M2 can each be implemented using a metal-oxide-semiconductor transistor, but this invention is not limited thereto. The control terminal (e.g., gate terminal) of the high-side switch M1 and the control terminal (e.g., gate terminal) of the low-side switch M2 are both coupled to the drive circuit 310. The remaining two ends of the high-side switch M1 (e.g., source and drain terminals) are respectively coupled to the power supply voltage VCC and the phase output node PHS, and the remaining two ends of the low-side switch M2 (e.g., source and drain terminals) are respectively coupled to the phase output node PHS and the ground terminal (which is used to receive the ground voltage (not shown in the figure)).

[0031] As described in the above embodiments, the drive circuit 310 of the power stage circuit 30 is coupled to the pulse generation circuit 20 and can be controlled by the pulse signal S20 (e.g., a pulse width modulation (PWM) signal) output by the pulse generation circuit 20 to generate a high-side drive signal UG and a low-side drive signal LG to the high-side switch M1 and the low-side switch M2, respectively. The high-side drive signal UG can be in phase with the pulse signal S20, while the low-side drive signal LG can be out of phase with the pulse signal S20. Accordingly, the high-side switch M1 and the low-side switch M2 are alternately turned on according to the high-side drive signal UG and the low-side drive signal LG to generate a phase output signal (not shown in the figure) at the phase output node PHS. The phase output signal can be a square waveform voltage signal, and the voltage level of this square waveform voltage signal can switch between the voltage level of the power supply voltage VCC and the voltage level of the ground voltage.

[0032] like Figure 1 As shown, the phase output node PHS is coupled to the output node NOUT via inductor L, and capacitor CO is coupled to the output node NOUT and the ground terminal. The circuit composed of inductor L and capacitor CO processes the phase output signal at the phase output node PHS, resulting in the output signal OUT being generated at the output node NOUT. As explained above regarding the pulse generation circuit 20 and the power stage circuit 30, the power stage circuit 30 generates the output signal OUT at the output node NOUT based on the pulse signal S20 output by the pulse generation circuit 20.

[0033] In some practical applications, the aforementioned load device may switch to a light-load or heavy-load state due to temporary changes in tasks (e.g., running specific applications and / or software). Compared to the light-load state, the load device in the heavy-load state requires a larger operating current in real time, which causes a sudden and significant decrease in the voltage level of the output signal OUT.

[0034] In view of the sudden decrease in the voltage level of the output signal OUT, in some embodiments, the control circuit 10 is coupled between the output node NOUT and the pulse generation circuit 20 to form a feedback loop. Through this feedback loop, the power converter circuit 100 can mitigate the sudden decrease in the output signal OUT, the principle of which will be further explained in later paragraphs.

[0035] The control circuit 10 includes an error amplifier circuit 11, a comparator circuit 12, and an output change detection circuit 13. In some embodiments, the error amplifier circuit 11 includes an error amplifier EA, a resistor R, and a capacitor C. The non-inverting input (+) of the error amplifier EA is coupled to a reference signal VREF, the inverting input (-) of the error amplifier EA is coupled to a feedback signal FB associated with the output signal OUT, and the output of the error amplifier EA is coupled to node NC. Furthermore, the two ends of the resistor R are coupled to node NC and capacitor C, respectively, and the two ends of the capacitor C are coupled to the resistor R and ground, respectively.

[0036] As described in the above embodiments, the reference signal VREF can be a voltage signal with a fixed voltage level. The feedback signal FB can reflect the change in the output signal OUT. For example, the feedback signal FB can be the output signal OUT or a voltage signal that is proportional to the output signal OUT. The error amplifier EA is used to amplify the result of subtracting the feedback signal FB from the reference signal VREF and convert it into an error current ICOMP. This error current ICOMP flows from node NC through resistor R and charges capacitor C, causing the compensation signal COMP to be generated at node NC. As can be seen from the description of the error amplifier circuit 11 above, the error amplifier circuit 11 is used to output the compensation signal COMP based on the difference between the reference signal VREF and the feedback signal FB.

[0037] In some embodiments, the comparator circuit 12 is implemented using a comparator. The non-inverting input (+) of the comparator circuit 12 is coupled to node NC, the inverting input (-) is coupled to the ramp signal RAMP, and the output of the comparator circuit 12 is coupled to the pulse generation circuit 20. The ramp signal RAMP can be a triangular waveform voltage signal. The comparator circuit 12 outputs a task signal DTY to the pulse generation circuit 20 based on the compensation signal COMP and the ramp signal RAMP. For example, the comparator circuit 12 compares the compensation signal COMP and the ramp signal RAMP to output a task signal DTY with an enable or disable level based on the comparison result.

[0038] As described in the above embodiments, when the voltage level of the output signal OUT decreases significantly due to the load device being under heavy load, the voltage level of the feedback signal FB also decreases significantly, causing the voltage level of the compensation signal COMP to increase. Furthermore, when the voltage level of the compensation signal COMP increases to a level greater than the voltage level of the ramp signal RAMP, the comparator circuit 12 controls the task signal DTY to have an enable level. The pulse generation circuit 20, in response to the enable level of the task signal DTY, changes the pulse period of the pulse signal S20. For example, the pulse generation circuit 20 shortens the disable period of the pulse signal S20 in each pulse period. This increases the frequency at which the high-side switch M1 and the low-side switch M2 alternately conduct, thus mitigating the sudden decrease in the output signal OUT, such as softening the decrease in the voltage level of the output signal OUT or changing the voltage level of the output signal OUT from decreasing to increasing.

[0039] As described above regarding the error amplifier circuit 11 and the comparator circuit 12, the control circuit 10 receives the reference signal VREF, the feedback signal FB related to the output signal OUT, and the ramp signal RAMP. It generates a compensation signal COMP based on the reference signal VREF and the feedback signal FB. When the compensation signal COMP exceeds the ramp signal RAMP (i.e., when the voltage level of the compensation signal COMP is greater than the voltage level of the ramp signal RAMP), it generates a task pulse signal (i.e., a task signal DTY at the enable level) to the pulse generation circuit 20 to regulate the sudden decrease of the output signal OUT. Furthermore, when the voltage level of the compensation signal COMP does not exceed the voltage level of the ramp signal RAMP due to the voltage rise of the output signal OUT, the control circuit 10 stops generating the task pulse signal to the pulse generation circuit 20 (i.e., the comparator circuit 12 outputs a task signal DTY at the disable level to the pulse generation circuit 20).

[0040] In some practical applications, the control circuit 10 is slow to generate or stop generating task pulse signals in response to changes in the output signal OUT, making the output signal OUT more prone to overshoot or undershoot. Therefore, in some embodiments, the output change detection circuit 13 is coupled to the error amplifier circuit 11 or the comparator circuit 12 to improve the overshoot or undershoot phenomenon of the output signal OUT. Specifically, the output change detection circuit 13 can generate a response signal REA when it detects a sudden change in the output signal OUT (e.g., a sudden decrease, a voltage rise, etc.) to speed up the generation or stopping of task pulse signals by the control circuit 10. The following will be discussed in conjunction with... Figure 2 Explain the function of the response signal REA in detail.

[0041] Please see Figure 2 , Figure 2This is a timing diagram illustrating the output signals OUT, compensation signal COMP, ramp signal RAMP, and task signal DTY related to the operation of the power converter circuit 100 according to some embodiments of the present invention. Furthermore, in... Figure 2 The diagram also shows the existing output signal OUTP and the existing task signal DTYP used to illustrate the role of the response signal REA. Note that both the output signal OUTP and the task signal DTYP are related to the response signal REA, while the existing output signal OUTP and the existing task signal DTYP are independent of the response signal REA.

[0042] like Figure 2 As shown, in response to a sudden decrease in the output signal OUT (i.e., the load device enters a heavy load state), the control circuit 10 switches the task signal DTY to the enable level at time point a1 by generating a reaction signal REA. Without the reaction signal REA, the existing task signal DTYP switches to the enable level at time point a2, which is later than time point a1. This time difference causes the output signal OUT to experience a voltage rise (i.e., the voltage level changes from decreasing to increasing) earlier than the existing output signal OUTP. As explained above, when the load device enters a heavy load state, the control circuit 10 uses the reaction signal REA to generate the task pulse signal earlier to avoid undershooting of the output signal OUT.

[0043] As described in the above embodiment, in response to the voltage rise of the output signal OUT (i.e., the load device switches from a heavy load state to a light load state), the control circuit 10 generates a reaction signal REA to switch the task signal DTY to the enable level for the last time at time point a3. Without the reaction signal REA, the existing task signal DTYP switches to the enable level for the last time at time point a4, which is later than time point a3. This time difference causes the output signal OUT to stop increasing its voltage earlier than the existing output signal OUTP. As explained above, when the load device switches from a heavy load state to a light load state, the control circuit 10 uses the reaction signal REA to stop generating the task pulse signal earlier, thus preventing the output signal OUT from overshooting.

[0044] In the above embodiments, the response signal REA can be an adjustment current, and the output change detection circuit 13 uses the response signal REA to control the error amplifier circuit 11 or the comparator circuit 12, so that the control circuit 10 can generate or stop generating the task pulse signal earlier or later. This will be used again in conjunction with Figure 1 Please refer to the detailed explanation. Figure 1 The control circuit 10 also includes a current-voltage conversion circuit 14[1], 14[2], or 14[3].

[0045] In some embodiments, where the control circuit 10 includes a current-to-voltage conversion circuit 14[1], it also includes an adder circuit 16[1]. The current-to-voltage conversion circuit 14[1] is coupled to the output change detection circuit 13 and is used to convert the adjustment current into an adjustment voltage. The adder circuit 16[1] is coupled to the non-inverting input of the error amplifier circuit 11 (i.e., the non-inverting input of the error amplifier EA) and the current-to-voltage conversion circuit 14[1] and is used to add the adjustment voltage to the reference signal VREF.

[0046] In some embodiments, where the control circuit 10 includes a current-to-voltage conversion circuit 14[2], it also includes a subtraction circuit 15[1]. The current-to-voltage conversion circuit 14[2] is coupled to the output change detection circuit 13 and is used to convert the adjustment current into an adjustment voltage. The subtraction circuit 15[1] is coupled to the inverting input of the error amplifier circuit 11 (i.e., the inverting input of the error amplifier EA) and the current-to-voltage conversion circuit 14[2] and is used to subtract the adjustment voltage from the feedback signal FB.

[0047] As can be seen from the above embodiments, when the output change detection circuit 13 is coupled to the error amplifier circuit 11, the output change detection circuit 13 can adjust the reference signal VREF or the feedback signal FB with the response signal REA when it detects a sudden change in the output signal OUT.

[0048] In some embodiments, where the control circuit 10 includes a current-to-voltage conversion circuit 14[3], it also includes a subtraction circuit 15[2]. The current-to-voltage conversion circuit 14[3] is coupled to the output change detection circuit 13 and is used to convert the adjustment current into an adjustment voltage. The subtraction circuit 15[2] is coupled to the inverting input of the comparator circuit 12 and the current-to-voltage conversion circuit 14[3] and is used to subtract the adjustment voltage from the ramp signal RAMP.

[0049] As can be seen from the above embodiments, when the output change detection circuit 13 is coupled to the comparator circuit 12, the output change detection circuit 13 can adjust the ramp signal RAMP with the response signal REA when it detects a sudden change in the output signal OUT.

[0050] In some embodiments, where the control circuit 10 does not include any of the current-to-voltage conversion circuits 14[1], 14[2], and 14[3], the control circuit 10 further includes an adder circuit 16[2]. The adder circuit 16[2] is coupled to the non-inverting input of the comparator circuit 12, the output change detection circuit 13, and the error amplifier circuit 11, and is used to add the adjustment current to the error current ICOMP generated by the error amplifier EA, so that the compensation signal COMP is generated not only based on the error current ICOMP but also further based on the adjustment current.

[0051] As can be seen from the above embodiments, when the output change detection circuit 13 is coupled to the error amplifier circuit 11 and the comparator circuit 12, the output change detection circuit 13 can adjust the compensation signal COMP with the response signal REA when it detects a sudden change in the output signal OUT.

[0052] Next, pair Figure 3A and Figure 3B Further explanation of the output change detection circuit 13. Figure 3A This is a circuit diagram of the output change detection circuit 13 according to some embodiments of the present invention. Figure 3B To and Figure 3A Timing diagram of some signals related to the operation of the output change detection circuit 13.

[0053] In some embodiments, such as Figure 3A As shown, the output change detection circuit 13 includes a delay circuit 131A and a detection circuit 132A. The delay circuit 131A is used to receive the output signal OUT and to delay the output signal OUT to generate a delayed signal OUT2. Specifically, the delay circuit 131A can be implemented by a delay unit DLY, but this invention is not limited thereto.

[0054] The detection circuit 132A is coupled to at least one of the delay circuit 131A and the error amplifier circuit 11 and the comparator circuit 12, and includes comparator CMP1, comparator CMP2, short pulse generator SPG1, short pulse generator SPG2, current generation circuit ISC1, current generation circuit ISC2, switching circuit SW1 and switching circuit SW2.

[0055] The non-inverting input of comparator CMP1 receives the output signal OUT, and its inverting input is coupled to delay circuit DLY to receive the delayed signal OUT2. Comparator CMP1 compares the output signal OUT and the delayed signal OUT2 to generate a comparison signal VO1. Short pulse generator SPG1 is coupled to comparator CMP1 and switching circuit SW1. Switching circuit SW1 is coupled to current generation circuit ISC1 and node O1. Furthermore, current generation circuit ISC1 is coupled to ground and used to generate discharge current ISNK.

[0056] The inverting input of comparator CMP2 receives the output signal OUT, and its non-inverting input is coupled to delay circuit DLY to receive the delayed signal OUT2. Comparator CMP2 compares the output signal OUT and the delayed signal OUT2 to generate a comparison signal VO2. Short pulse generator SPG2 is coupled to comparator CMP2 and switching circuit SW2. Switching circuit SW2 is coupled to current generation circuit ISC2 and node O1. Furthermore, current generation circuit ISC2 is coupled to the power supply voltage VCC and is used to generate charging current ISRC.

[0057] In some embodiments, when the voltage level of the output signal OUT suddenly decreases due to the load device entering a heavy load state, the voltage level of the delayed signal OUT2 has not yet begun to decrease. In this case, such as Figure 3B As shown, the voltage level of the output signal OUT at time t2 is less than the voltage level of the delayed signal OUT2. It should be understood that the voltage level of the delayed signal OUT2 at time t2 is equivalent to the voltage level of the output signal OUT at time t1. Accordingly, comparator CMP1 controls the comparison signal VO1 to have a disabled level, while comparator CMP2 controls the comparison signal VO2 to have an enabled level. Short pulse generator SPG1 does not generate a short pulse signal SP1 based on the disabled level comparison signal VO1, so that the switching circuit SW1 remains in the off state. Short pulse generator SPG2 generates a short pulse signal SP2 based on the enabled level comparison signal VO2, causing the switching circuit SW2 to switch from the off state to the on state under the control of the short pulse signal SP2. Therefore, the charging current ISRC generated by the current generation circuit ISC2 flows to node O1 through the on-state switching circuit SW2 as the response signal REA. That is, the response signal REA will be generated at node O1. In this embodiment, the aforementioned adjustment current is the charging current ISRC.

[0058] In addition, such as Figure 1As illustrated in the embodiment, node O1 can be coupled to at least one of the error amplifier circuit 11 and the comparator circuit 12. When the output change detection circuit 13 adjusts the reference signal VREF, the feedback signal FB, or the ramp signal RAMP with the response signal REA, the charging current ISRC, which is the response signal REA, is converted into a charging voltage (not shown in the figure, i.e., the adjustment voltage mentioned above). The control circuit 10 can add the charging voltage to the reference signal VREF, subtract the charging voltage from the feedback signal FB, or subtract the charging voltage from the ramp signal RAMP. Furthermore, when the output change detection circuit 13 adjusts the compensation signal COMP with the response signal REA, the control circuit 10 adds the charging current ISRC to the error current ICOMP corresponding to the compensation signal COMP. Compared to related technologies that do not generate a response signal REA, the control circuit 10 can adjust the reference signal VREF, the feedback signal FB, the compensation signal COMP, or the ramp signal RAMP through the response signal REA, so that the compensation signal COMP exceeds the ramp signal RAMP earlier, thereby adjusting the sudden decrease of the output signal OUT in advance. This avoids undershooting of the output signal OUT.

[0059] In some embodiments, when the voltage level of the output signal OUT rises due to the load switching from a heavy load state to a light load state, the voltage level of the delayed signal OUT2 has not yet begun to rise. In this case, such as Figure 3B As shown, the voltage level of the output signal OUT at time t4 is greater than the voltage level of the delayed signal OUT2. It should be understood that the voltage level of the delayed signal OUT2 at time t4 is equivalent to the voltage level of the output signal OUT at time t3. Accordingly, comparator CMP1 controls the comparator signal VO1 to have an enable level, while comparator CMP2 controls the comparator signal VO2 to have a disable level. Short pulse generator SPG1 generates a short pulse signal SP1 based on the enable level of the comparator signal VO1, causing the switching circuit SW1 to switch from the off state to the on state under the control of the short pulse signal SP1. Short pulse generator SPG2 does not generate the short pulse signal SP2 based on the disable level of the comparator signal VO2, thus keeping the switching circuit SW2 in the off state. Therefore, the discharge current ISNK generated by the current generation circuit ISC1 flows from node O1 to the ground terminal through the on-state switching circuit SW1 as the reaction signal REA. That is, the reaction signal REA will be generated at node O1. In this embodiment, the aforementioned adjustment current is the discharge current ISNK.

[0060] When the output change detection circuit 13 adjusts the reference signal VREF, feedback signal FB, or ramp signal RAMP with the response signal REA, the discharge current ISNK, which is the response signal REA, is converted into a discharge voltage (not shown in the figure, i.e., the adjustment voltage mentioned above). The control circuit 10 can add the discharge voltage to the reference signal VREF, subtract the discharge voltage from the feedback signal FB, or subtract the discharge voltage from the ramp signal RAMP. Furthermore, when the output change detection circuit 13 adjusts the compensation signal COMP with the response signal REA, the control circuit 10 adds the discharge current ISNK to the error current ICOMP corresponding to the compensation signal COMP. Compared to related technologies that do not generate a response signal REA, the control circuit 10 can adjust the reference signal VREF, feedback signal FB, compensation signal COMP, or ramp signal RAMP through the response signal REA, causing the compensation signal COMP to exceed the ramp signal RAMP earlier, thus adjusting the voltage rise of the output signal OUT in advance. In this way, overshooting of the output signal OUT can be avoided.

[0061] As can be seen from the above embodiments, the detection circuit 132A is used to detect sudden changes in the output signal OUT based on the output signal OUT and the delay signal OUT2, so as to generate a response signal REA (i.e., charging current ISRC or discharging current ISNK).

[0062] It should be understood that the comparison signal VO1, comparison signal VO2, short pulse signal SP1, short pulse signal SP2, charging current ISRC, and discharging current ISNK of this utility model are not limited to... Figure 3B The waveform shown. Figure 3A In some further embodiments, the duration of the enable level of the comparison signal VO1 is proportional to the pulse width of the short pulse signal SP1, and the duration of the enable level of the comparison signal VO2 is proportional to the pulse width of the short pulse signal SP2.

[0063] Furthermore, the output change detection circuit 13 of this utility model is not limited to... Figure 3A The circuit architecture shown will be further explained in the following paragraphs.

[0064] Please see Figure 4 , Figure 4 This is a circuit diagram illustrating the output change detection circuit 13 according to some embodiments of the present invention. Figure 4 In one embodiment, the output change detection circuit 13 includes a delay circuit 131A and a detection circuit 132B. Compared to Figure 3A The detection circuit 132A, in Figure 4In the detection circuit 132B, the current generation circuit ISC1 is also coupled to the comparator CMP1, and the current generation circuit ISC2 is also coupled to the comparator CMP2. With this configuration, the current generation circuit ISC1 can control the current level of the discharge current ISNK to be proportional to the duration for which the comparison signal VO1 has an enable level, and the current generation circuit ISC2 can control the current level of the charging current ISRC to be proportional to the duration for which the comparison signal VO2 has an enable level.

[0065] Please see Figure 5 , Figure 5 This is a circuit diagram illustrating the output change detection circuit 13 according to some embodiments of the present invention. Figure 5 In one embodiment, the output change detection circuit 13 includes a delay circuit 131A and a detection circuit 132C. Compared to Figure 3A The detection circuit 132A, in Figure 5 In the detection circuit 132C, short pulse generators SPG1 and SPG2 are omitted. Instead, switching circuit SW1 is directly coupled to comparator CMP1, and switching circuit SW2 is directly coupled to comparator CMP2. With this configuration, switching circuit SW1 is controlled by comparison signal VO1, switching from an off state to an on state according to the enable level of comparison signal VO1; similarly, switching circuit SW2 is controlled by comparison signal VO2, switching from an off state to an on state according to the enable level of comparison signal VO2. In other words, the duration of switching circuit SW1 in the on state is determined by the duration of comparison signal VO1 holding the enable level, and the duration of switching circuit SW2 in the on state is determined by the duration of comparison signal VO2 holding the enable level.

[0066] Please see Figure 6 , Figure 6 This is a circuit diagram illustrating a delay circuit 131B according to some embodiments of the present invention. In some embodiments, the delay circuit 131B can be used to replace... Figure 3A , Figure 4 and Figure 5 The delay circuit 131B includes a buffer circuit. Compared to delay circuit 131A, delay circuit 131B further includes a buffer circuit. Specifically, the buffer circuit can be constructed using operational amplifier OP2. The non-inverting input of operational amplifier OP2 is coupled to the output of delay unit DLY, and the inverting input of operational amplifier OP2 is coupled to its output. After delay unit DLY generates a delayed signal OUT2 based on the output signal OUT, the buffer circuit buffers the delayed signal OUT2, causing delay circuit 131B to output the delayed signal OUT2.

[0067] Please see Figure 7A and Figure 7B , Figure 7A This is a circuit diagram of the output change detection circuit 13 according to some embodiments of the present invention. Figure 7B To and Figure 7A Timing diagram of some signals related to the operation of the output change detection circuit 13. Figure 7A In this embodiment, the output change detection circuit 13 includes a delay circuit 131C and a detection circuit 132D. The delay circuit 131C is implemented using a sample-and-hold circuit SAH, while the detection circuit 132D is implemented using a transconductance amplifier circuit GA. The non-inverting input of the transconductance amplifier circuit GA is coupled to the output of the sample-and-hold circuit SAH. Both the inverting input of the transconductance amplifier circuit GA and the input of the sample-and-hold circuit SAH are used to receive the output signal OUT. The output of the transconductance amplifier circuit GA can be coupled to... Figure 1 The error amplifier circuit 11 or the comparator circuit 12 is used in the circuit.

[0068] The sample-and-hold circuit SAH samples and holds the output signal OUT according to a preset sampling frequency to generate a delayed signal OUT2. For example, as... Figure 7B As shown, the sample-and-hold circuit SAH samples and holds the output signal OUT at time t5. Therefore, the voltage level of the delayed signal OUT2 at time t6 is still equivalent to the voltage level of the output signal OUT at time t5. Similarly, the sample-and-hold circuit SAH samples and holds the output signal OUT at time t7. Therefore, the voltage level of the delayed signal OUT2 at time t8 is still equivalent to the voltage level of the output signal OUT at time t7. Thus, it can be seen that the delay circuit 131C, like the aforementioned delay circuits 131A or 131B, is used to delay the output signal OUT to generate the delayed signal OUT2.

[0069] The transconductance amplifier circuit GA receives the output signal OUT and the delayed signal OUT2, and uses them to generate a charging current ISRC or a discharging current ISNK as a response signal REA. If the voltage level of the output signal OUT suddenly decreases due to the load device entering a heavy load state, such as... Figure 7B As shown, the voltage level of the output signal OUT is less than the voltage level of the delayed signal OUT2 at time t6. Accordingly, the transconductance amplifier circuit GA performs voltage-to-current conversion by subtracting the positive voltage difference between the delayed signal OUT2 and the output signal OUT, generating the charging current ISRC. When the voltage level of the output signal OUT rises again due to the load switching from a heavy load to a light load state, as... Figure 7BAs shown, the voltage level of the output signal OUT is greater than the voltage level of the delayed signal OUT2 at time t8. Accordingly, the transconductance amplifier circuit GA converts the negative voltage difference between the delayed signal OUT2 and the output signal OUT into a voltage-to-current converter to generate the discharge current ISNK.

[0070] Please see Figure 8 , Figure 8 This is a circuit diagram illustrating the output change detection circuit 13 according to some embodiments of the present invention. Figure 8 In one embodiment, the output change detection circuit 13 includes a delay circuit 131A and a detection circuit 132E. Compared to Figure 3A The detection circuits 132A and 132E further include fine-tuning circuits VT1 and VT2. Fine-tuning circuit VT1 is coupled to comparator CMP1 and is used to adjust the offset of comparator CMP1 (e.g., the offset of the comparison reference) according to the output signal OUT to change its response speed. Fine-tuning circuit VT2 is coupled to comparator CMP2 and is used to adjust the offset of comparator CMP2 (e.g., the offset of the comparison reference) according to the output signal OUT to change its response speed. Fine-tuning circuits VT1 and VT2 will be discussed in the following paragraphs. Figure 9 and Figure 10 Let me explain in detail.

[0071] Please see Figure 9 , Figure 9 This is a circuit diagram illustrating fine-tuning circuits VT1 and VT2 according to some embodiments of the present invention. In some embodiments, fine-tuning circuit VT1 includes a voltage-controlled voltage source Vos1. One end of voltage-controlled voltage source Vos1 is coupled to the inverting input of comparator CMP2, and the other end is coupled to the non-inverting input of comparator CMP1. Fine-tuning circuit VT2 includes a voltage-controlled voltage source Vos2. One end of voltage-controlled voltage source Vos2 is coupled to the output of delay unit DLY and the inverting input of comparator CMP1, and the other end is coupled to the non-inverting input of comparator CMP2. Voltage-controlled voltage sources Vos1 and Vos2 are each controlled by an output signal OUT to generate corresponding fine-tuning voltages (not shown in the figure). In one embodiment, the fine-tuning voltage generated by voltage-controlled voltage source Vos1 may be equal to the fine-tuning voltage generated by voltage-controlled voltage source Vos2. In other embodiments, the fine-tuning voltage generated by voltage-controlled voltage source Vos1 is not equal to the fine-tuning voltage generated by voltage-controlled voltage source Vos2.

[0072] As described in the above embodiments, the fine-tuning voltage is used to adjust the conditions or timing under which comparator CMP1 (or comparator CMP2) controls the comparison signal VO1 (or comparison signal VO2) to have an enable level. For example, when the fine-tuning voltage generated by the voltage-controlled voltage source Vos1 is 0 volts, comparator CMP1 will control the comparison signal VO1 to have an enable level when the voltage level of the output signal OUT is greater than the voltage level of the delay signal OUT2. When the fine-tuning voltage generated by the voltage-controlled voltage source Vos1 is a positive voltage, comparator CMP1 will control the comparison signal VO1 to have an enable level when the sum of the voltage level of the output signal OUT and the fine-tuning voltage is greater than the voltage level of the delay signal OUT2. Therefore, the rise in the output signal OUT does not need to be too large to trigger the generation of the discharge current ISNK, meaning the output change detection circuit 13 can generate the response signal REA more quickly. When the fine-tuning voltage generated by the voltage-controlled voltage source Vos1 is negative, comparator CMP1 will control the comparator signal VO1 to have an enable level when the result of subtracting the fine-tuning voltage from the voltage level of the output signal OUT is greater than the voltage level of the delayed signal OUT2. Therefore, the rise in the output signal OUT must be large enough to trigger the generation of the discharge current ISNK, meaning the output change detection circuit 13 can generate the response signal REA a little later.

[0073] Furthermore, when the fine-tuning voltage generated by the voltage-controlled voltage source Vos2 is 0 volts, comparator CMP2 will enable the comparison signal VO2 when the voltage level of the delayed signal OUT2 is greater than the voltage level of the output signal OUT. When the fine-tuning voltage generated by the voltage-controlled voltage source Vos2 is positive, comparator CMP2 will enable the comparison signal VO2 when the sum of the voltage level of the delayed signal OUT2 and the fine-tuning voltage is greater than the voltage level of the output signal OUT. Therefore, the decrease in the output signal OUT does not need to be too large to trigger the generation of the charging current ISRC, meaning the output change detection circuit 13 can generate the response signal REA more quickly. When the fine-tuning voltage generated by the voltage-controlled voltage source Vos2 is negative, comparator CMP2 will enable the comparison signal VO2 when the result of subtracting the fine-tuning voltage from the voltage level of the delayed signal OUT2 is greater than the voltage level of the output signal OUT. Therefore, the output signal OUT needs to decrease by a large enough amount to trigger the generation of the charging current ISRC, which means that the output change detection circuit 13 can generate the response signal REA a little later.

[0074] Please see Figure 10 , Figure 10The diagram shows circuit schematics of fine-tuning circuits VT1 and VT2 according to some embodiments of the present invention. In some embodiments, fine-tuning circuit VT1 includes a current source I1 and a voltage-controlled resistor R1. One end of the voltage-controlled resistor R1 is coupled to the inverting input of comparator CMP2, and the other end is coupled to the non-inverting input of comparator CMP1 and one end of current source I1. The other end of current source I1 is coupled to the power supply voltage VCC. Fine-tuning circuit VT2 includes a current source I2 and a voltage-controlled resistor R2. One end of the voltage-controlled resistor R2 is coupled to the output of delay unit DLY and the inverting input of comparator CMP1, and the other end is coupled to the non-inverting input of comparator CMP2 and one end of current source I2. The other end of current source I2 is coupled to the power supply voltage VCC. Voltage-controlled resistors R1 and R2 are each controlled by the output signal OUT and have corresponding resistance values. The currents generated by current sources I1 and I2 cause corresponding fine-tuning voltages (not shown in the diagram) to be applied across voltage-controlled resistors R1 and R2, respectively. The function of the fine-tuning voltage can be found in [reference needed]. Figure 9 The description of the embodiments is analogous and will not be repeated here.

[0075] As can be seen from the above embodiments of the present invention, by generating a reaction signal REA in response to a sudden change in the load device state (e.g., switching to a heavy load or light load state) of the output signal OUT, the control circuit 10 can change the pulse period of the pulse signal S20 generated by the pulse generation circuit 20 in advance to avoid undershooting or overshooting of the output signal OUT. Therefore, the power converter circuit 100 and its control circuit 10 of the present invention have advantages such as good instantaneous load response capability and high power stability.

[0076] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0077] [Symbol Explanation]

[0078] 10: Control Circuit

[0079] 11: Error Amplifier Circuit

[0080] 12: Comparator Circuit

[0081] 13: Output Change Detection Circuit

[0082] 14: Current-to-voltage conversion circuit

[0083] 15: Subtraction Circuit

[0084] 16: Adder circuit

[0085] 20: Pulse Generation Circuit

[0086] 30: Power stage circuit

[0087] 100: Power converter circuit

[0088] 131A, 131B, 131C: Delay circuits

[0089] 132A, 132B, 132C, 132D, 132E: Detection circuit; 310: Drive circuit; a1, a2, a3, a4, t1, t2, t3, t4, t5, t6, t7, t8: Timing points; C: Capacitors; CMP1, CMP2: Comparators

[0090] CO: Capacitor

[0091] COMP: Compensation signal

[0092] DLY: Delay device

[0093] DTY: Mission Signal

[0094] DTYP: Existing mission signal

[0095] EA: Error Amplifier

[0096] FB: Feedback signal

[0097] GA: Transconductance Amplifier Circuit

[0098] L: Inductance

[0099] LG: Low-side drive signal; I1, I2: Current source; ICOMP: Error current; ISC1, ISC2: Current generation circuit.

[0100] ISNK: Discharge Current

[0101] ISRC: Charging Current

[0102] M1: High-side switch

[0103] M2: Low-side switch NC, O1: Node

[0104] NOUT: Output node

[0105] OP2: Operational amplifier

[0106] OUT: Output signal

[0107] OUT2: Delayed signal

[0108] OUTP: Existing output signal

[0109] PHS: Phase Output Node

[0110] R: Resistance

[0111] R1, R2: Voltage-controlled resistors

[0112] RAMP: Ramp signal

[0113] REA: Reaction signal

[0114] S20: Pulse signal

[0115] SAH: Sample and Hold Circuit

[0116] SP1, SP2: Short pulse signals

[0117] SPG1, SPG2: Short pulse generator

[0118] SW1, SW2: Switching circuits

[0119] UG: High-side drive signal

[0120] VCC: Power supply voltage

[0121] VO1, VO2: Comparison signals

[0122] Vos1, Vos2: Voltage-controlled voltage sources

[0123] VREF: Reference Signal

[0124] VT1, VT2: Fine-tuning circuit.

Claims

1. A control circuit, characterized in that, This is applicable to power converter circuits, wherein the power converter circuit includes a pulse generation circuit and a power stage circuit. The pulse generation circuit outputs a pulse signal, and the power stage circuit generates an output signal at the output node based on the pulse signal. The control circuit includes: An error amplifier circuit is coupled to the output node and is used to output a compensation signal based on the difference between the reference signal and the feedback signal associated with the output signal. A comparator circuit, coupled to the error amplifier circuit, is used to output a task signal to the pulse generation circuit based on the compensation signal and the ramp signal, and to control the task signal to have an enable level when the compensation signal exceeds the ramp signal; and Output change detection circuit, including: A delay circuit is used to receive the output signal and delay the output signal to generate a delayed signal; as well as A detection circuit is coupled to at least one of the delay circuit, the error amplifier circuit, and the comparator circuit, and is used to detect sudden changes in the output signal based on the output signal and the delay signal to generate a response signal. The output change detection circuit is used to control the error amplifier circuit or the comparator circuit with the response signal to change the pulse period of the pulse signal, thereby adjusting the sudden change in the output signal.

2. The control circuit according to claim 1, characterized in that, The delay circuit includes a delay unit, and the detection circuit includes: A first comparator, coupled to the delay unit, is used to receive the output signal and the delayed signal, and to compare the output signal and the delayed signal to generate a first comparison signal, wherein the first comparison signal has the enable level when the voltage level of the delayed signal is greater than the voltage level of the output signal. The first current generating circuit is coupled to the power supply voltage and is used to generate charging current. as well as A first switching circuit is coupled to the first current generating circuit and the first node, and is used to switch from an off state to an on state according to the first comparison signal of the enable level, wherein the charging current flows to the first node through the first switching circuit in the on state. The reaction signal is generated at the first node.

3. The control circuit according to claim 2, characterized in that, The detection circuit also includes: A second comparator, coupled to the delay circuit, is used to receive the output signal and the delayed signal, and to compare the output signal and the delayed signal to generate a second comparison signal, wherein the second comparison signal has an enable level when the voltage level of the output signal is greater than the voltage level of the delayed signal. The second current generating circuit is coupled to the ground terminal and is used to generate discharge current. as well as A second switching circuit, coupled to the second current generating circuit and the first node, is used to switch from the off state to the on state according to the second comparison signal of the enable level, wherein the discharge current flows from the first node to the ground terminal through the second switching circuit in the on state. The reaction signal is either the charging current or the discharging current.

4. The control circuit according to claim 1, characterized in that, The delay circuit includes a sample-and-hold circuit, and the detection circuit includes: A transconductance amplifier circuit, coupled to the sample-and-hold circuit, is used to receive the output signal and the delay signal, and to generate a charging current or a discharging current as the response signal based on the output signal and the delay signal.

5. The control circuit according to claim 1, characterized in that, The response signal includes an adjustment current. The control circuit also includes a current-to-voltage conversion circuit, which is coupled to the detection circuit and used to convert the adjustment current into an adjustment voltage. The adjustment voltage is used to adjust the reference signal, the feedback signal, or the ramp signal.

6. The control circuit according to claim 5, characterized in that, Also includes: The subtraction circuit is coupled to one of the inverting input terminals of the error amplifier circuit and the inverting input terminal of the comparator circuit, and to the current-to-voltage conversion circuit, and is used to subtract the adjustment voltage from one of the feedback signal and the ramp signal.

7. The control circuit according to claim 5, characterized in that, Also includes: An adder circuit is coupled to the non-inverting input of the error amplifier circuit and the current-to-voltage conversion circuit, and is used to add the adjustment voltage to the reference signal.

8. The control circuit according to claim 1, characterized in that, The response signal includes an adjustment current. The control circuit also includes an adder circuit, which is coupled to the non-inverting input of the comparator circuit and the detection circuit, and is used to add the adjustment current to the error current corresponding to the compensation signal.

9. A power converter circuit, characterized in that, Include: Pulse generation circuit, used to output pulse signal; A power stage circuit is coupled to the output node of the pulse generation circuit and the power converter circuit, and is used to generate an output signal at the output node according to the pulse signal. as well as A control circuit, coupled to the pulse generation circuit and the output node, includes: An error amplifier circuit is coupled to the output node and is used to output a compensation signal based on the difference between the reference signal and the feedback signal associated with the output signal. A comparator circuit, coupled to the error amplifier circuit, is used to output a task signal to the pulse generation circuit based on the compensation signal and the ramp signal, and to control the task signal to have an enable level when the compensation signal exceeds the ramp signal; and Output change detection circuit, including: A delay circuit is used to receive the output signal and delay the output signal to generate a delayed signal; as well as A detection circuit is coupled to at least one of the delay circuit, the error amplifier circuit, and the comparator circuit, and is used to detect sudden changes in the output signal based on the output signal and the delay signal to generate a response signal. The output change detection circuit is used to control the error amplifier circuit or the comparator circuit with the response signal to change the pulse period of the pulse signal, thereby adjusting the sudden change in the output signal.

10. The power converter circuit according to claim 9, characterized in that, The output change detection circuit is coupled to at least one of the error amplifier circuit and the comparator circuit, and is used to adjust the reference signal, the feedback signal, the compensation signal or the ramp signal with the reaction signal when the sudden change of the output signal is detected, so as to change the pulse period of the pulse signal.

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