Semiconductor structure

Abstract

A semiconductor structure includes a carrier layer defining an electrical connection region and a peripheral region, a first insulating layer disposed on the electrical connection region, a second insulating layer disposed on the first insulating layer, and a circuit layer interposed between the first insulating layer and the second insulating layer and defining a circuit pattern region electrically connected to the electrical connection region and a dummy pattern region surrounding the circuit pattern region. The semiconductor structure is mainly configured to have the dummy pattern region to enhance the structural strength of the semiconductor structure, avoid warping deformation of the semiconductor structure, and improve the yield of the process.

Description

Technical Field

[0001] This application relates to a semiconductor structure, and more particularly to a semiconductor structure having a redistribution layer. Background Technology

[0002] The manufacturing of semiconductor devices typically involves two complex processes: front-end processes and back-end processes. The front-end process involves forming multiple wafers on the surface of a wafer, each wafer containing circuitry formed by electrically connecting active and passive components. The back-end process involves slicing individual wafers from the completed wafer and packaging them to provide structural support and external connectivity.

[0003] With the widespread adoption of smart mobile communications and / or wearable devices, semiconductor components are actively moving towards miniaturized and multifunctional advanced process chips. Among these, improvements to the front-end process can achieve smaller chip sizes, thereby creating chips with smaller size and higher density of active and passive components. In addition, the back-end process can improve electrical interconnect materials and structures, such as fan-out redistribution layers, to provide electrical interconnections from the inside of the chip to the outside, thereby creating input / output contacts with sufficient connectivity to the outside world.

[0004] However, the advanced process chips currently developed by semiconductor manufacturers are made up of many layers of components with different materials and functions. The materials used in these components are quite complex and diverse. When stacked together, the different coefficients of thermal expansion (CTE) of each layer will cause warpage problems. Therefore, overcoming the various problems of the existing technology has become an urgent issue to be addressed. Utility Model Content

[0005] In view of the various deficiencies of the prior art, this application provides a semiconductor structure, including: a carrier layer defining an electrical connection region and a peripheral region; a first insulating layer correspondingly disposed on the electrical connection region; a second insulating layer correspondingly disposed on the first insulating layer; and a circuit layer sandwiched between the first insulating layer and the second insulating layer, and defining a circuit pattern region electrically connected to the electrical connection region and a dummy pattern region surrounding the circuit pattern region.

[0006] In the aforementioned semiconductor structure, the circuit layer is a wiring layer.

[0007] In the aforementioned semiconductor structure, a passivation layer is provided between the carrier layer and the first insulating layer.

[0008] In the aforementioned semiconductor structure, the first insulating layer and the second insulating layer also extend to the peripheral region.

[0009] In the aforementioned semiconductor structure, the circuit layer also extends between the first insulating layer and the second insulating layer above the peripheral region.

[0010] In the aforementioned semiconductor structure, the electrical connection region of the carrier layer includes a plurality of connection pads electrically connected to the circuit layer.

[0011] In the aforementioned semiconductor structure, a plurality of bump under-metal layers electrically connected to the circuit layer are formed on the second insulating layer.

[0012] In the aforementioned semiconductor structure, a conductive bump is also formed on the metal layer beneath the bump.

[0013] In the aforementioned semiconductor structure, the supporting layer is a silicon wafer.

[0014] In the aforementioned semiconductor structure, the dummy pattern region does not have electrical function.

[0015] As can be seen from the above, the semiconductor structure of this application mainly strengthens the structural strength of the semiconductor structure by setting a dummy pattern area around the circuit pattern area, thereby preventing the semiconductor structure from warping and deforming during the process and improving the yield of the process. Attached Figure Description

[0016] Figure 1 This is a top view schematic diagram of the semiconductor structure of this application.

[0017] Figure 2 This is a partial cross-sectional schematic diagram of the semiconductor structure of this application.

[0018] Explanation of reference numerals in the attached figures

[0019] 1. Semiconductor Structure

[0020] 10. Bearing layer

[0021] 11 Electrical connection area

[0022] 111 Connecting Pad

[0023] 12 Outer Zones

[0024] 20 First Insulation Layer

[0025] 30 Line Layer

[0026] 30A Line Layer Distribution Area

[0027] 31. Circuit Pattern Area

[0028] 32. Virtual Pattern Area

[0029] 40 Second Insulation Layer

[0030] 50 passivation layer

[0031] 61. Metal layer under the bump

[0032] 62. Conductive bumps. Detailed Implementation

[0033] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0034] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above" and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0035] Figure 1 This is a top view schematic diagram of the semiconductor structure 1 of this application; Figure 2 This is a partial cross-sectional schematic diagram of the semiconductor structure of this application.

[0036] like Figure 1 and Figure 2 As shown, this embodiment provides an example of a semiconductor structure 1. The semiconductor structure 1 includes a carrier layer 10, a first insulating layer 20, a second insulating layer 40, and a circuit layer 30. The carrier layer 10 is a semiconductor substrate, such as a silicon wafer. The carrier layer 10 defines an electrical connection region 11 located at its central portion, and a peripheral region 12 surrounding the electrical connection region 11. The electrical connection region 11 is the area where electronic components and circuits (not shown) are arranged. The electronic components formed in the electrical connection region 11 can be transistors, capacitors, inductors, resistors, and the circuits formed in the electrical connection region 11 include multiple connection pads 111 electrically connected to the circuit layer 30. Figure 2 Only one example is shown in the text.

[0037] A first insulating layer 20 is disposed on the electrical connection area 11. The first insulating layer 20 may be made of a flexible polymer material such as polyimide (PI) to facilitate installation, but is not limited thereto. In some embodiments, a passivation layer 50 may also be formed between the carrier layer 10 and the first insulating layer 20, exposing the connection pad 111. The passivation layer 50 may be made of a material such as silicon nitride or silicon oxide, but is not limited thereto.

[0038] The second insulating layer 40 is disposed on the first insulating layer 20, and its arrangement and shape correspond to those of the first insulating layer 20. The second insulating layer 40, like the first insulating layer 20, can also be made of a polymer material such as polyimide (PI), and its material can be the same as or different from that of the first insulating layer 20. This embodiment does not have any particular limitations in this regard.

[0039] A wiring layer 30 is sandwiched between the first insulating layer 20 and the second insulating layer 40 and is disposed in a wiring layer distribution area 30A. The shape and range of the wiring layer distribution area 30A do not exceed the shape and range of the first insulating layer 20 and the second insulating layer 40, and defines a wiring pattern area 31 electrically connected to the electrical connection area 11 and a dummy pattern area 32 surrounding the wiring pattern area 31. The shape of the dummy pattern area 32 is, for example, a frame surrounding each side of the wiring layer distribution area 30A, and the pattern contained therein (not shown) is not electrically connected to the wiring of any other layer, and therefore has no electrical function. The wiring layer 30 in the wiring pattern area 31 can be, for example, a fan-out redistribution layer, but is not limited to this.

[0040] Generally, the circuit layer 30 is made of copper or other suitable conductive metallic material. Since a dummy pattern area 32 of metallic pattern is provided around the circuit pattern area 31, the central portions of the second insulating layer 40 and the first insulating layer 20 on both the upper and lower sides of the circuit layer 30, corresponding to the electrical connection area 11 of the carrier layer 10, can be supported by the circuit layer 30 within the circuit pattern area 31, while the portions corresponding to the edges of the electrical connection area 11 of the carrier layer 10 can be supported by the dummy pattern area 32 of the circuit layer 30. Therefore, the semiconductor structure 1 shown in this embodiment is protected from warping or deformation, at least within the electrical connection area 11 of the carrier layer 10 and its corresponding area.

[0041] In some embodiments, the first insulating layer 20 and the second insulating layer 40 may further extend to the peripheral region 12 of the carrier layer 10. This can reduce the structural difference between the semiconductor structure 1 above the electrical connection region 11 and the semiconductor structure 1 above the peripheral region 12, and can further improve the effect of preventing warping and deformation of the semiconductor structure 1.

[0042] In other embodiments, the overall structural strength of the semiconductor structure 1 can be further enhanced by expanding the dummy pattern area 32 of the circuit layer 30 to the space between the first insulating layer 20 and the second insulating layer 40 above the peripheral area 12.

[0043] In some embodiments, a plurality of under bump metal (UBM) layers 61 electrically connected to the circuit layer 30 are formed on the second insulating layer 40, and a conductive bump 62, such as a solder ball, is formed on each under bump metal layer 61.

[0044] As can be seen from the above, the semiconductor structure of this application mainly strengthens the structural strength of the semiconductor structure by setting a dummy pattern area around the circuit pattern area, thereby preventing the semiconductor structure from warping and deforming during the process and improving the yield of the process.

[0045] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The supporting layer defines an electrical connection area and an outer perimeter area surrounding the electrical connection area; The first insulating layer is disposed on the electrical connection area of ​​the carrier layer; The second insulating layer is disposed on the first insulating layer. as well as The circuit layer is sandwiched between the first insulating layer and the second insulating layer, and the circuit layer defines a circuit pattern area electrically connected to the electrical connection area and a dummy pattern area surrounding the circuit pattern area.

2. The semiconductor structure as described in claim 1, characterized in that, This line layer is a rewiring layer.

3. The semiconductor structure as described in claim 1, characterized in that, A passivation layer is provided between the carrier layer and the first insulating layer.

4. The semiconductor structure as described in claim 1, characterized in that, The first insulating layer and the second insulating layer also extend to the peripheral area.

5. The semiconductor structure as described in claim 4, characterized in that, The circuit layer also extends between the first insulation layer and the second insulation layer above the outer perimeter area.

6. The semiconductor structure as described in claim 1, characterized in that, The electrical connection area of ​​the carrier layer includes multiple connection pads that are electrically connected to the circuit layer.

7. The semiconductor structure as described in claim 1, characterized in that, Multiple metal layers with bumps electrically connected to the circuit layer are formed on the second insulating layer.

8. The semiconductor structure as described in claim 7, characterized in that, A conductive bump is also formed on the metal layer beneath the bump.

9. The semiconductor structure as described in claim 1, characterized in that, The supporting layer is a silicon wafer.

10. The semiconductor structure as claimed in claim 1, characterized in that, This virtual pattern area has no electrical function.

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