A reconfigurable single board, chassis and chassis networking system for quantum computing

Abstract

The utility model discloses a kind of reconfigurable single board for quantum computing, cabinet and cabinet networking system, belong to superconducting quantum computing technical field;The reconfigurable single board includes first connector assembly, antistatic unit, second connector assembly and third connector assembly, and single board reconfiguration of hardware level is realized by passive device combination, support one divides many beam or many unifies one combined path function, realize signal transmission path switching;The reconfigurable single board is inserted in cabinet, and multiple cabinet networking is realized by external cable connection, and cabinet networking system supports the double mode operation of pure electricity mode and photoelectric mode;The utility model solves the problem that existing quantum measurement and control system is rigid in interface in cabinet expansion, development cycle is long and cost is high, has beneficial effect such as without external power supply, physical level flexible switching topology, strong expansion capability, signal transmission stability, applicable to large-scale superconducting quantum computing measurement and control system.

Claims

1. A reconfigurable single-board for quantum computing, characterized in that, The assembly includes a first connector assembly (11), an anti-static unit (12), a second connector assembly (13), and a third connector assembly (14). The second connector assembly (13) includes n+1 parallel connectors, denoted as P1 to Pn+1. The third connector assembly (14) includes x-1 parallel connectors, denoted as Pn+2 to Pn+x. The first to n+1 ports on one side of the first connector assembly (11) are respectively connected to the first to n+1 ports on one side of the anti-static unit (12), and the first to n+1 ports on the other side of the anti-static unit (12) are respectively connected to the first ends of connectors P1 to Pn+1. The first end of connector Pn+2 is respectively connected to the first ends of connectors Pn+3 to Pn+x. Wherein, n is an integer greater than or equal to 1, and x is an integer greater than or equal to 4.

2. The reconfigurable board for quantum computing according to claim 1, characterized in that, The anti-static unit (12) uses multiple TVS diodes or TVS chips arranged in parallel.

3. The reconfigurable board for quantum computing according to claim 1, characterized in that, The first connector assembly (11) uses a PXIe connector.

4. The reconfigurable board for quantum computing according to claim 1, characterized in that, The connectors in the second connector assembly (13) and the third connector assembly (14) are DP connectors.

5. A chassis, characterized in that, The chassis is fitted with a reconfigurable board for quantum computing as described in any one of claims 1 to 4.

6. The chassis according to claim 5, characterized in that, The first to the (n+1)th ports on the other side of the first connector assembly (11) in the reconfigurable board for quantum computing are connected to the back panel of the chassis.

7. A chassis, characterized in that, The chassis is equipped with a reconfigurable board for quantum computing as described in any one of claims 1 to 4, and the chassis is also equipped with an optoelectronic board.

8. The chassis according to claim 7, characterized in that, The first to the (n+1)th ports on the other side of the first connector assembly (11) in the reconfigurable board for quantum computing are connected to the back panel of the chassis.

9. A chassis networking system, characterized in that, It includes n+1 chassis as described in claim 5 or 6, one of which is a master chassis and the other n are slave chassis. The second ends of connectors P1, P2, P3...Pn in the reconfigurable board of the master chassis are respectively connected to the second ends of connectors Pn+1 in the reconfigurable board of the 1st, 2nd, 3rd...nth slave chassis.

10. A chassis networking system, characterized in that, This includes [(x-2)*n+1] chassis as described in claim 7 or 8, wherein one serves as the master chassis and n serve as the first-level slave chassis, denoted as M1, M2, M3…M n Additionally, there are (x-3)*n chassis as second-level slave chassis. These second-level slave chassis are divided into n groups, denoted as C1, C2, C3, ... Cn. n Each group of second-level slave chassis includes (x-3) chassis; the second ends of connectors P1, P2, P3...Pn in the reconfigurable boards of the main chassis are respectively connected to the M1, M2, M3...M... n The first level connects one-to-one with the second end of connector Pn+2 in the reconfigurable board of the chassis; the M1, M2, M3...M n The second end of connector Pn+3 in the reconfigurable board of the first level chassis is connected to M1, M2, M3...M respectively. n The first level connects one-to-one with the second end of connector Pn+1 in the reconfigurable board of the chassis; the M1, M2, M3...M n The first level, from connectors Pn+4 to Pn+x on the reconfigurable board of the chassis, connects to the second ends of connectors C1, C2, C3, ... C1 respectively. n The second level of the group connects one-to-one with the second end of connector Pn+1 in the reconfigurable boards of the first to (x-3) chassis.

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