Packaging structure

Abstract

The utility model provides a kind of packaging structure, comprising: first wafer;Heat pipe, located the first wafer;Radiator, located the heat pipe, wherein the heat pipe and the back of the first wafer directly contact.The utility model aims at providing a kind of packaging structure, to improve the overall heat dissipation effect of packaging structure at least.

Description

Technical Field

[0001] This utility model relates to a packaging structure. Background Technology

[0002] Figure 1 The diagram illustrates a prior art packaging structure where the heat sink 30 may fail to dissipate heat effectively due to prolonged use of the chip (first chip 11 and / or second chip 12), leading to reduced chip lifespan and processing speed due to prolonged high temperatures. The size of the heat sink 30 is determined by the chip's volume; heat sinks 30 used for high-performance, small-volume chips have poorer heat dissipation efficiency. The future trend of chips is inevitably towards smaller size and higher processing power, making them more prone to overheating anomalies. Utility Model Content

[0003] In view of the problems existing in the related technologies, the purpose of this utility model is to provide a packaging structure to at least improve the overall heat dissipation effect of the packaging structure.

[0004] To achieve the above objectives, this utility model provides a packaging structure, comprising: a first wafer; a heat pipe located on the first wafer; and a heat sink located on the heat pipe, wherein the heat pipe is in direct contact with the back side of the first wafer.

[0005] In some embodiments, the heat sink is in direct contact with the heat pipe.

[0006] In some embodiments, the packaging structure further includes: a first packaging layer that wraps the heat pipe, wherein the first packaging layer is in direct contact with the back side of the first wafer and the heat sink.

[0007] In some embodiments, the upper and lower surfaces of the heat pipe are substantially aligned with the upper and lower surfaces of the first encapsulation layer, respectively.

[0008] In some embodiments, the heat pipe has a hollow structure.

[0009] In some embodiments, the lower surface of the heat pipe has an extension extending toward the first encapsulation layer, the extension covering a portion of the lower surface of the first encapsulation layer.

[0010] In some embodiments, the extension is located between the first packaging layer and the first wafer, and is in direct contact with the back side of the first wafer.

[0011] In some embodiments, the packaging structure further includes: a second wafer, disposed at a distance from the first wafer along a first direction, and a plurality of the heat pipes disposed on the first wafer and the second wafer, wherein the heat pipes do not simultaneously contact the first wafer and the second wafer.

[0012] In some embodiments, the heat pipe extends substantially parallel to the back surface of the first wafer.

[0013] In some embodiments, the plurality of heat pipes are substantially parallel.

[0014] Embodiments of this application also provide a packaging structure, including: a first wafer and a second wafer, arranged side by side along a first direction; a plurality of heat pipes attached to the first wafer and the second wafer, the plurality of heat pipes extending along a second direction substantially perpendicular to the first direction and arranged side by side along the first direction; and a heat sink located on the plurality of heat pipes.

[0015] In some embodiments, the heat pipes in the plurality of heat pipes do not simultaneously contact the first wafer and the second wafer.

[0016] In some embodiments, the surfaces of the first wafer, the second wafer, and the plurality of heat pipes that are in direct contact are passive surfaces.

[0017] The beneficial technical effects of this utility model are as follows:

[0018] The embodiments of this application propose an enhanced heat dissipation structure. Specifically, a heat pipe layer is added to the back of the chip to significantly improve heat dissipation efficiency and overcome the problem of overheating. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It is worth noting that, according to industry standard practice, the components are not drawn to scale and are only used for illustrative purposes. In fact, for clarity of discussion, the dimensions of the components can be arbitrarily increased or decreased.

[0020] Figure 1 The packaging structure of the prior art is shown.

[0021] Figure 2 The carrier is shown.

[0022] Figure 3 The formation of the release layer is shown.

[0023] Figure 4 The formation of a heat pipe is shown.

[0024] Figure 5 The formation of the first encapsulation layer is shown.

[0025] Figure 6 The planarization process is shown to expose multiple heat pipes.

[0026] Figure 7 The image shows the chip being placed on a heat dissipation module.

[0027] Figure 8 The formation of the second encapsulation layer is shown.

[0028] Figure 9 The formation of the redistribution layer is shown.

[0029] Figure 10 The formation of solder balls is shown.

[0030] Figure 11 The structure obtained by removing the carrier and releasing the layer and flipping it is shown.

[0031] Figure 12 The packaging structure according to an embodiment of this application is shown.

[0032] Figure 13 A packaging structure according to another embodiment of this application is shown.

[0033] Figure 14 A packaging structure according to another embodiment of this application is shown.

[0034] Figure 15 A packaging structure according to another embodiment of this application is shown.

[0035] Figure 16 and Figure 17 Top views of the heat dissipation module and the first and second wafers according to different embodiments are shown respectively.

[0036] Figure 18 It shows in Figure 6 A partial top view of the heat pipe and the first encapsulation layer after the grinding steps shown. Detailed Implementation

[0037] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0038] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0039] The terms “approximately,” “generally,” “substantial,” “substantial,” “about,” and “approximately” used herein are used to indicate and explain minor variations. For example, when used in conjunction with numerical values, the above terms may refer to a range of variation less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another embodiment, the thickness of a film or layer being “substantially uniform” may refer to the average thickness of the film or layer being less than or equal to ±10% of the standard deviation, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that are within 50 μm along the same plane (such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane). If, for example, two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm, then the two components can be considered "substantially aligned." If the angle between two surfaces or components is, for example, 90° ± 10° (such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°), then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "approximately," "generally," "substantially," "materially," "about," and "approximately" can refer to the exact occurrence of the event or situation as well as the very close approximation of its occurrence.

[0040] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0041] For ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0042] Figures 2 to 12 The packaging structure 100 and its manufacturing process according to an embodiment of this application are shown.

[0043] Figure 2 The carrier 70 is shown.

[0044] Figure 3 A release layer 72 is shown formed on a carrier 70. The carrier 70 may be a glass carrier, a ceramic carrier, etc. The carrier 70 may be a wafer, thereby allowing multiple encapsulation structures 100 to be formed simultaneously on the carrier 70. The release layer 72 may be formed of a polymer-based material, which may be removed from the above structure along with the carrier 70 in subsequent steps. In some embodiments, the release layer 72 is a thermally release material based on epoxy resin that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer 72 may be a UV adhesive that loses its adhesiveness upon exposure to ultraviolet light. The release layer 72 may be a coating that is dispensed and cured in liquid form, a laminated film laminated on the carrier 70, or the like. The top surface of the release layer 72 may be horizontal and may have a high degree of flatness.

[0045] Figure 4 A plurality of heat pipes 20 are shown formed on the release layer 72. In some embodiments, the heat pipes are copper pipes.

[0046] Figure 5 A first encapsulation layer 41 is shown forming a plurality of heat pipes 20.

[0047] Figure 6 A planarization process (e.g., polishing) is shown to expose a plurality of heat pipes 20. In some embodiments, the plurality of heat pipes 20 and a first encapsulation layer 41 covering the plurality of heat pipes 20 constitute a heat dissipation module. In some embodiments, because the top surface of the heat pipes 20 is polished, the upper side of the heat pipes 20 is thinner than the lower side, that is, the side of the heat pipes 20 that subsequently faces the first wafer 11 and the second wafer 12 is thinner than the other side (the side facing the heat sink 30).

[0048] Figure 7 The diagram shows a first wafer 11 and a second wafer 12 positioned with their back surfaces (passive surfaces) facing down and their front surfaces (active surfaces) facing up on a plurality of heat pipes 20 and a first encapsulation layer 41. The back surfaces of the first wafer 11 and the second wafer 12 are in contact with the plurality of heat pipes 20 and the first encapsulation layer 41. In some embodiments, the first wafer 11 is a memory, such as high bandwidth memory (HBM), and the second wafer 12 is an application-specific integrated circuit (AS IC).

[0049] Figure 8A second packaging layer 42 is shown forming a first wafer 11 and a second wafer 12, and a planarization process (e.g., polishing) is performed to expose the first wafer 11 and the second wafer 12.

[0050] Figure 9 It shows the formation located in Figure 8 The redistribution layer 50 is shown on the structure. The redistribution layer 50 is electrically connected to the active surfaces of the first wafer 11 and the second wafer 12.

[0051] Figure 10 The solder balls 60 forming the bonding redistribution layer 50 are shown.

[0052] Figure 11 The removal was shown Figure 10 The carrier 70 and the release layer 72 are in the structure obtained by flipping them.

[0053] Figure 12 The diagram shows a heat sink 30 attached to a heat dissipation module, resulting in a package structure 100 according to an embodiment of this application. The heat sink 30 is in direct contact with a plurality of heat pipes 20 and a first encapsulation layer 41. Figures 2 to 12 A cross-sectional view perpendicular to the extension direction of the heat pipe 20 is shown. In the cross-sectional view, the heat pipe 20 has an annular shape, with both the outer and inner edges of the annular shape being rectangular. The two opposing transverse sides of the outer edge contact the heat sink 30 and the wafer / second packaging layer 42, respectively.

[0054] Figure 13 A packaging structure 100 according to another embodiment of this application is shown, and... Figure 12 The difference in the illustrated embodiment is that the heat pipe 20 between the two first wafers 11 and the second wafer 12 is removed, which prevents the heat generated by the second wafer 12 from being transferred to the first wafer 11 via the heat pipe 20. Therefore, the spacing between the heat pipes 20 can be different; for example, the spacing between two heat pipes 20 on the facing edges of the first wafer 11 and the second wafer 12 is greater than the spacing between other heat pipes 20.

[0055] Figure 14 A package structure 100 according to another embodiment of this application is shown. The package structure 100 further includes a passive element 14 disposed side-by-side with the first wafer on a redistribution layer 50. In some embodiments, the passive element 14 is a capacitor, a resistor, and / or an inductor. The passive element 14 is spaced apart from the heat dissipation module.

[0056] Figure 15 A package structure 100 according to another embodiment of this application is shown, wherein a plurality of pads 62 are provided below the redistribution layer 50 for connection to external components.

[0057] Figure 16 and Figure 17Top views of the heat dissipation module and the first chip 11 and the second chip 12 according to different embodiments are shown, wherein the first encapsulation layer 41 of the heat dissipation module is drawn as transparent and the heat pipe 20 is drawn as semi-transparent, so that the first chip 11 and the second chip 12 below the heat dissipation module can be seen. Figure 16 In the illustrated embodiment, the extending direction of the heat pipe 20 is substantially perpendicular to the first direction D in which the first wafer 11 and the second wafer 12 are arranged, and the included angle between the two directions is, for example, 90° ± 10° (such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°). Figure 17 In the illustrated embodiment, the extending direction of the heat pipe 20 is substantially parallel to the first direction D in which the first wafer 11 and the second wafer 12 are arranged, and the included angle between the two directions is, for example, 0° ± 10° (such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°). (Comparison) Figure 16 and Figure 17 Implementation examples, Figure 16 The arrangement direction of the heat pipes 20 in the illustrated embodiment is preferred. Figure 16 The embodiment shown avoids the heat pipe 20 from spanning the first wafer 11 and the second wafer 12, thus preventing the heat generated by the second wafer 12 from being transferred to the first wafer 11 via the heat pipe 20.

[0058] Figure 18 It shows in Figure 6 The partial top view of the heat pipe 20 and the first encapsulation layer 41 after the grinding step is shown. The heat pipe 20, after grinding, produces an extension 22 extending towards and covering the surface of the first encapsulation layer 41. In some embodiments, the extension 22 exhibits a burr-like microstructure, i.e., the heat pipe 20 has serrated edges. The surface of the heat pipe 20 where the extension 22 is formed is for subsequent... Figure 7 The steps shown are used to bond the surfaces of the first wafer 11 and the second wafer 12, so the extension 22 is sandwiched between the first encapsulation layer 41 and the first wafer 11 and the second wafer 12. Due to the presence of the extension 22, the contact area between the heat pipe 20 and the first encapsulation layer 41 is increased, which can enhance the fixing effect of the heat pipe 20.

[0059] Embodiments of this application provide a packaging structure 100, including: a first wafer 11; a heat pipe 20 located on the first wafer 11; and a heat sink 30 located on the heat pipe 20, wherein the heat pipe 20 is in direct contact with the back surface of the first wafer 11. Embodiments of this application propose an enhanced heat dissipation structure, specifically, adding a heat pipe 20 layer on the back surface of the wafer, significantly improving heat dissipation efficiency and overcoming overheating problems.

[0060] In some embodiments, the heat sink 30 is in direct contact with the heat pipe 20.

[0061] In some embodiments, the packaging structure 100 further includes a first packaging layer 41 that wraps around the heat pipe 20, and the first packaging layer 41 is in direct contact with the back side of the first chip 11 and the heat sink 30.

[0062] In some embodiments, the upper and lower surfaces of the heat pipe 20 are substantially aligned with the upper and lower surfaces of the first encapsulation layer 41, for example, within 50 μm along the same plane (such as within 40 μm, 30 μm, 20 μm, 10 μm or 1 μm along the same plane).

[0063] In some embodiments, the heat pipe 20 has a hollow structure.

[0064] In some embodiments, the lower surface of the heat pipe 20 has an extension 22 extending toward the first encapsulation layer 41, the extension 22 covering a portion of the lower surface of the first encapsulation layer 41.

[0065] In some embodiments, the extension 22 is located between the first packaging layer 41 and the first wafer 11, and is in direct contact with the back side of the first wafer 11.

[0066] In some embodiments, the packaging structure 100 further includes: a second wafer 12, spaced apart from the first wafer 11 along a first direction D, and a plurality of heat pipes 20 disposed on the first wafer 11 and the second wafer 12, wherein see Figure 13 The heat pipe 20 does not simultaneously contact the first wafer 11 and the second wafer 12, meaning the heat pipe 20 does not span between the first wafer 11 and the second wafer 12. This prevents heat generated by the second wafer 12 from being transferred to the first wafer 11 via the heat pipe 20, reducing the heat transfer path between the first wafer 11 and the second wafer 12. In some embodiments, the heat pipe 20 is not positioned directly above the gap between the first wafer 11 and the second wafer 12. In other embodiments, the heat pipe 20 may simultaneously cover the first wafer 11 and a portion of the second encapsulation layer 42 in the gap between the first wafer 11 and the second wafer 12; the heat pipe 20 may also simultaneously cover the second wafer 12 and a portion of the second encapsulation layer 42 in the gap between the first wafer 11 and the second wafer 12. That is, the heat pipe 20 may be present directly above the gap between the first wafer 11 and the second wafer 12, as long as the heat pipe 20 does not simultaneously cover the first wafer 11 and the second wafer 12. In a preferred embodiment, the width of the heat pipe 20 (along the first direction D) is smaller than the width of the gap between the first wafer 11 and the second wafer 12, so as to avoid the heat pipe 20 bridging the first wafer 11 and the second wafer 12 and to avoid heat transfer between the first wafer 11 and the second wafer 12.

[0067] In some embodiments, the heat pipe 20 extends substantially parallel to the back surface of the first wafer 11, with an angle between them of, for example, 0° ± 10° (such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°).

[0068] In some embodiments, the plurality of heat pipes 20 are substantially parallel, and the angle between the extension directions of any two heat pipes 20 is, for example, 0° ± 10° (such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1° or ± 0.05°).

[0069] Embodiments of this application also provide a packaging structure 100, including: a first wafer 11 and a second wafer 12, arranged side-by-side along a first direction D; a plurality of heat pipes 20, located on the first wafer 11 and the second wafer 12, and extending in contact with the first wafer 11 and the second wafer 12, the plurality of heat pipes 20 extending along a second direction R substantially perpendicular to the first direction D (see...). Figure 16 The heat sink 30 is located on the plurality of heat pipes 20. The heat sink 30 extends (to reduce or avoid heat transfer between the first wafer 11 and the second wafer 12) and is arranged side by side along the first direction D.

[0070] In some embodiments, the heat pipes 20 in the plurality of heat pipes 20 do not simultaneously contact the first wafer 11 and the second wafer 12.

[0071] In some embodiments, the surfaces of the first wafer 11, the second wafer 12, and the plurality of heat pipes 20 that are in direct contact are passive surfaces.

[0072] The embodiments of this application increase the heat dissipation efficiency and cooling effect of the packaging structure 100 by combining the heat pipe 20 and packaging technology. The embodiments of this application can be applied to all chips and extended to all products.

[0073] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A packaging structure, characterized in that, include: First chip; The heat pipe is located on the first wafer; The heat sink is located on the heat pipe. The heat pipe is in direct contact with the back side of the first wafer.

2. The packaging structure according to claim 1, characterized in that, The heat sink is in direct contact with the heat pipe.

3. The packaging structure according to claim 1, characterized in that, Also includes: A first encapsulation layer encapsulates the heat pipe, and the first encapsulation layer is in direct contact with the back side of the first chip and the heat sink.

4. The packaging structure according to claim 3, characterized in that, The upper and lower surfaces of the heat pipe are substantially aligned with the upper and lower surfaces of the first encapsulation layer, respectively.

5. The packaging structure according to claim 1, characterized in that, The heat pipe has a hollow structure.

6. The packaging structure according to claim 3, characterized in that, The lower surface of the heat pipe has an extension that extends toward the first encapsulation layer, and the extension covers a portion of the lower surface of the first encapsulation layer.

7. The packaging structure according to claim 6, characterized in that, The extension is located between the first packaging layer and the first wafer, and is in direct contact with the back side of the first wafer.

8. The packaging structure according to claim 1, characterized in that, Also includes: A second wafer is disposed at a distance from the first wafer along a first direction, and a plurality of the heat pipes are disposed on the first wafer and the second wafer. The heat pipe does not contact the first wafer and the second wafer simultaneously.

9. The packaging structure according to claim 1, characterized in that, The heat pipe extends substantially parallel to the back surface of the first wafer.

10. A packaging structure, characterized in that, include: The first wafer and the second wafer are arranged side by side along a first direction; A plurality of heat pipes are attached to the first wafer and the second wafer, the plurality of heat pipes extending along a second direction substantially perpendicular to the first direction and arranged side by side along the first direction; Heat sinks are located on the plurality of heat pipes.

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