A semiconductor structure and electronic device

Abstract

This utility model provides a semiconductor structure and an electronic device. The semiconductor structure includes a substrate having a first device composite layer comprising at least a first dielectric layer, a second dielectric layer, and a first metal layer stacked sequentially. A portion of the first device composite layer forms a platform region with a first preset size in a functional edge region. Corresponding to the functional edge region, the first device composite layer has a sidewall layer and a conductive pillar filled in a conductive contact hole and in contact with the first metal layer. The conductive contact hole penetrates the sidewall layer, the first dielectric layer, and the second dielectric layer, or the conductive contact hole penetrates the sidewall layer, the first dielectric layer, the second dielectric layer, and a portion of the first metal layer. The projected size of the conductive contact hole on the substrate is greater than or equal to 70% of the first preset size, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a semiconductor structure and electronic device. Background Technology

[0002] With the continuous development of the semiconductor industry, higher requirements are being placed on the semiconductor process structure. In semiconductor processes, especially in TFAP (Thin Film Acoustic Package) processes, the conductive pillars formed based on contact holes suffer from poor interfacial bonding due to process limitations, thereby reducing the overall electrical performance of the semiconductor structure.

[0003] Therefore, how to improve the interfacial bonding force of conductive pillars to enhance the overall electrical performance of semiconductor structures has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] In view of this, the present invention provides a semiconductor structure and electronic device to improve the interfacial bonding force of conductive pillars and thereby improve the overall electrical performance of the semiconductor structure.

[0005] The first aspect of this utility model provides a semiconductor structure, including:

[0006] A substrate having a first device composite layer thereon, wherein a portion of the first device composite layer forms a platform region with a first preset size in the functional edge region;

[0007] The first device composite layer includes at least a first dielectric layer, a second dielectric layer, and a first metal layer stacked sequentially. Corresponding to the functional edge region, the first device composite layer is provided with conductive pillars, which fill conductive contact holes and contact the first metal layer. The conductive contact holes penetrate the first dielectric layer and the second dielectric layer, or the conductive contact holes penetrate the first dielectric layer, the second dielectric layer, and a portion of the first metal layer. The projected size of the conductive contact holes on the substrate is greater than or equal to 70% of the first preset size.

[0008] Optionally, the conductive contact hole is obtained using etching and electroplating processes.

[0009] Optionally, the projected size of the conductive contact hole on the substrate is 30 micrometers to 50 micrometers.

[0010] Optionally, the thickness of the first metal layer exposed by the conductive contact hole is 0 to 500 angstroms.

[0011] Optionally, the thickness of the first dielectric layer is less than 600 angstroms, and the thickness of the second dielectric layer is less than 600 angstroms.

[0012] Optionally, the material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or titanium dioxide;

[0013] The material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or titanium dioxide.

[0014] Optionally, the first device composite layer further includes a second metal layer; the first metal layer conformally covers the second metal layer.

[0015] Optionally, the semiconductor structure further includes a support layer and a second device composite layer located on the substrate;

[0016] The support layer conformally covers the edge of the second device composite layer and extends in a direction away from the second device composite layer to form a platform area with a second preset size, the second preset size being greater than or equal to the first preset size;

[0017] The second metal layer is located on the support layer and part of the second device composite layer, and the first metal layer is located on the support layer and the second device composite layer.

[0018] Optionally, the second device composite layer includes at least an interdigitated electrode layer, a piezoelectric layer, a low-velocity layer, and a trap-rich layer stacked sequentially.

[0019] A second aspect of this utility model provides an electronic device, including the semiconductor structure described in the first aspect.

[0020] The semiconductor structure of this utility model embodiment includes a substrate, on which a first device composite layer is disposed. A portion of the first device composite layer forms a platform region with a first size in a functional edge region. The first device composite layer includes at least a first dielectric layer, a second dielectric layer, and a first metal layer stacked sequentially. Corresponding to the functional edge region, the first device composite layer is provided with a sidewall layer and a conductive pillar. The conductive pillar fills a conductive contact hole and contacts the first metal layer. The conductive contact hole penetrates the sidewall layer, the first dielectric layer, and the second dielectric layer, or the conductive contact hole penetrates the sidewall layer, the first dielectric layer, the second dielectric layer, and a portion of the first metal layer. The projected size of the conductive contact hole on the substrate is greater than or equal to 70% of the first preset size.

[0021] As can be seen, when the projected size of the conductive contact hole on the substrate in the embodiment of this utility model is greater than or equal to 70% of the first preset size, the conductive contact hole can have a larger contact window, which effectively improves the interfacial bonding force of the conductive pillars filling the conductive contact hole, and increases its contact area with the first metal layer, reduces the contact impedance with the first metal layer, and improves the overall electrical performance of the semiconductor structure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0023] Figure 1 This is an optional schematic diagram of a semiconductor structure;

[0024] Figure 2 This is another possible schematic diagram of a semiconductor structure;

[0025] Figure 3 This is a partially enlarged schematic diagram of a conductive contact hole in a semiconductor structure.

[0026] Figure 4 This is a top view of a conductive contact hole in a semiconductor structure.

[0027] Figure 5 Optional schematic diagram of the semiconductor structure provided in the embodiments of this utility model;

[0028] Figure 6 Another optional schematic diagram of the semiconductor structure provided in this embodiment of the present invention;

[0029] Figure 7 A partially enlarged schematic diagram of a conductive contact hole in a semiconductor structure provided for an embodiment of this utility model;

[0030] Figure 8 This is a top view of a conductive contact hole in a semiconductor structure provided in an embodiment of the present invention. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0032] As described in the background section, in semiconductor processes, especially in TFAP (Thin Film Acoustic Package) processes, the conductive pillars formed based on contact holes suffer from poor interfacial adhesion due to process limitations. This increases the contact impedance between the conductive pillars and the metal layer, thereby reducing the overall electrical performance of the semiconductor structure. Figure 1 An exemplary schematic diagram of an optional semiconductor structure is shown.

[0033] like Figure 1 As shown, the semiconductor structure includes: a substrate 10, and a functional layer 11 located on the substrate. The functional layer 11 can be formed by stacking different layer structures in sequence to obtain a semiconductor device with corresponding functions.

[0034] The functional layer 11 may include at least a first dielectric layer 111, a second dielectric layer 112, and a first metal layer 113. In an optional implementation, the functional layer 11 may further include a second metal layer 114, the material of which may differ from that of the first metal layer 113. For example, the first metal layer 113 may be made of gold (Au), and the second metal layer 114 may be made of an aluminum-copper alloy (AlCu). The first metal layer 113 and the second metal layer 114 can serve as PAD layers (i.e., solder pad layers) to achieve electrical interconnection of the semiconductor structure. To achieve electrical interconnection of the semiconductor structure, a bump structure 115 is also provided on the functional layer. The bump structure 115 is electrically connected to the first metal layer 113 based on conductive posts 115'. As an optional implementation, the bump structure 115 may be a solder ball or a metal interconnect structure located on the conductive posts 115'. The conductive posts 115' are obtained by filling conductive contact holes.

[0035] In another alternative implementation, based on the bump structure 115, the functional layer 11 may also include a protective layer 116, which is used to protect the bump structure 115 from damage.

[0036] It should be noted that functional layer 11 is divided into functional edge areas ( Figure 1 The number of the sub-subject is "Ⅰ") and the effective functional area ( Figure 1 (Referring to the designation "Ⅱ"), the effective functional area is used to set corresponding functional structures, such as interdigitated electrodes, and is the core area for realizing the function of the semiconductor device; the functional edge area is located outside the effective functional area and is used to ensure the electrical performance of the effective functional area. The conductive contact holes are correspondingly set based on the functional edge area, and corresponding to the conductive contact holes, the functional layer also includes a sidewall layer 117, which may be located above the first dielectric layer 111, and the protective layer 116 may be located above the sidewall layer 117.

[0037] correspond Figure 1 , Figure 2 An exemplary schematic diagram of another alternative semiconductor structure is shown. See also Figure 2 As shown, the semiconductor structure has a conductive contact hole 118. In one optional implementation, due to the presence of the sidewall layer 117, the conductive contact hole 118 can penetrate the sidewall layer 117, the first dielectric layer 111, and the second dielectric layer 112. In another optional implementation, the conductive contact hole 118 can penetrate the sidewall layer 117, the first dielectric layer 111, the second dielectric layer 112, and a portion of the first metal layer 113. The specific configuration of the conductive contact hole 118 can be selected according to actual requirements. Figure 1 and Figure 2 The example shown is only the conductive contact hole 118 penetrating the sidewall layer 117, the first dielectric layer 111, the second dielectric layer 112 and part of the first metal layer 113.

[0038] The conductive contact hole 118 can be obtained by etching, specifically by wet etching, by etching the first dielectric layer 111, the second dielectric layer 112 and the sidewall layer 117, or by etching the first dielectric layer 111, the second dielectric layer 112 and part of the first metal layer 113 and the sidewall layer 117.

[0039] It should be noted that when forming the conductive contact hole 118 using a wet etching process, due to the limitations of the wet etching process, during the etching of the first dielectric layer, not only is a portion of the first dielectric layer 111 etched vertically, but also a portion of the sidewall layer 117 is etched horizontally. This makes the interface between the sidewall layer 117 and the first dielectric layer 111 prone to lateral concavity near the conductive contact hole 118 (e.g., Figure 1 (The portion with medium to coarse coiling). Therefore, to avoid lateral concavity, the window size of the conductive contact hole 118 obtained by etching is generally small relative to the first metal layer 113, typically controlled to be below 30 micrometers.

[0040] correspond Figure 1 , Figure 3 An exemplary, partially enlarged schematic diagram of the conductive contact hole 118 in this semiconductor structure is shown. Wherein, Figure 3 For the corresponding Figure 1 The diagram shows a partially enlarged view of the portion circled in the middle dashed circle, and also illustrates the conductive contact hole 118 clearly. Figure 3 This represents the state when the conductive contact hole is not filled with conductive material. (Corresponding...) Figure 3 , Figure 4 An exemplary top view of the conductive contact hole in this semiconductor structure is shown. See also Figure 3 and Figure 4As shown, the window size of the conductive contact hole 118 is smaller than that of the first metal layer 113. Furthermore, when the conductive contact hole 118 is filled to form a conductive pillar, the conductive pillar will come into contact with the first dielectric layer 111. The material of the first dielectric layer 111 is generally a non-metallic material. Therefore, due to the material limitation of the first dielectric layer 111, the interfacial bonding force between the conductive pillar and the conductive contact hole 118 is reduced, resulting in a decrease in the electrical performance of the semiconductor structure.

[0041] In view of this, the present invention provides an improved semiconductor structure. By optimizing the window size of the conductive contact hole relative to the metal layer, that is, the projected size of the conductive contact hole on the substrate is greater than or equal to 70% of the first preset size, the window size of the conductive contact hole relative to the metal layer is larger, which effectively improves the interfacial bonding force of the conductive pillar filling the conductive contact hole, and increases its contact area with the metal layer, reduces the contact impedance with the metal layer, and improves the overall electrical performance of the semiconductor structure.

[0042] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0043] Figure 5 A schematic diagram of the semiconductor structure provided for an embodiment of this utility model, as shown below. Figure 5 As shown, the semiconductor structure includes a substrate 20, on which a first device composite layer 21 is disposed.

[0044] Among them, a portion of the first device composite layer 21 is located in the functional edge region, such as... Figure 5 In an optional example, the area indicated by the label "Ⅰ" in the functional edge region may have a stepped topography for the first device composite layer 21, and a portion of the first device composite layer 21 may form a platform region with a first preset size X in the functional edge region. The first preset size X is as follows: Figure 5 As shown.

[0045] The first device composite layer 21 includes at least a first dielectric layer 211, a second dielectric layer 212, and a first metal layer 213 stacked sequentially. Furthermore, corresponding to the functional edge region, the first device composite layer 21 also includes a sidewall layer 214 and conductive pillars 215, the conductive pillars 215 filling conductive contact holes. Figure 5 (Not shown), and is in contact with the first metal layer 213.

[0046] It should be noted that, based on the electrical interconnection characteristics of the semiconductor structure, a bump structure 216 and a protective layer 217 for protecting the bump structure 216 may also be provided on the first device composite layer 21. The contents of the bump structure 216 and the protective layer 217 can be found in the description of the bump structure 115 and the protective layer 116 mentioned above, and will not be repeated here.

[0047] correspond Figure 5 , Figure 6 An exemplary schematic diagram of another alternative semiconductor structure in an embodiment of the present invention is shown. See also Figure 6 As shown, the semiconductor structure has conductive contact holes 218 for filling conductive material to form conductive pillars 215. These conductive contact holes 218 can penetrate the sidewall layer 214, the first dielectric layer 211, and the second dielectric layer 212; alternatively, they can penetrate the sidewall layer 214, the first dielectric layer 211, the second dielectric layer 212, and a portion of the first metal layer 213. The specific configuration of the conductive contact holes 218 can be selected according to actual needs, and this embodiment of the invention does not impose any limitations on this selection. Figure 5 and Figure 6 The example shown only includes the section penetrating the sidewall layer 214, the first dielectric layer 211, the second dielectric layer 212, and a portion of the first metal layer 213. Furthermore, in this embodiment, the projected size of the conductive contact hole 218 on the substrate is greater than or equal to 70% of the first preset size X. For example, the projected size of the conductive contact hole 218 on the substrate is 70%, 73%, 75%, 80%, or 85% of the first preset size X. This embodiment does not limit this to a specific value.

[0048] It should be noted that, corresponding Figure 5 , Figure 7 An exemplary, partially enlarged schematic diagram of a conductive contact hole in a semiconductor structure according to an embodiment of the present invention is shown. Wherein, Figure 7 for Figure 5 The diagram shows a partially enlarged view of the portion circled in the dashed circle, and also illustrates the conductive contact hole 218 clearly. Figure 7 This represents the state when the conductive contact hole is not filled with conductive material. (Corresponding...) Figure 7 , Figure 8 An exemplary top view of a conductive contact hole in a semiconductor structure according to an embodiment of the present invention is shown.

[0049] contrast Figure 7 and Figure 3 ,as well as Figure 8 and Figure 4 As can be seen, the embodiments of this utility model Figure 7 or Figure 8 The conductive contact hole 218 in the semiconductor structure shown is compared to Figure 3 or Figure 4 The window size of the conductive contact hole 118 in the semiconductor structure shown is significantly increased; see details below. Figure 8 The dimensions of L2 and Figure 4 The size of L1, meaning the area of ​​the first metal layer 213 exposed in the conductive contact hole 218 is relatively large, increases the contact area between the conductive post filling the conductive contact hole 218 and the first metal layer 213. This reduces the contact impedance between the conductive post and the first metal layer 213, which is beneficial for improving the electrical performance of the semiconductor structure. Furthermore, because the conductive contact hole has a large contact window, the conductive post filling the conductive contact hole does not contact the first dielectric layer, thereby improving the interfacial bonding force of the conductive post.

[0050] Due to limitations in the etching process, as an optional implementation, the conductive contact hole in this embodiment can be obtained by combining etching and electroplating processes. That is, the window size of the conductive contact hole relative to the first metal layer is limited by the etching process, resulting in a relatively small window size. To meet the requirement in this embodiment that the projected size of the conductive contact hole on the substrate is greater than or equal to 70% of the first preset size X, this embodiment can further remove a portion of the first dielectric layer and a portion of the second dielectric layer, or a portion of the first dielectric layer, a portion of the second dielectric layer, and a portion of the first metal layer, based on the small window obtained by the etching process. This avoids lateral concavity of the conductive contact hole while also meeting the requirement for a larger contact window size relative to the first metal layer.

[0051] In a specific example, the projected size of the conductive contact hole 218 on the substrate in this embodiment of the invention can be from 30 micrometers to 50 micrometers, for example, 30 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, and 50 micrometers are all acceptable. To ensure the device performance of the semiconductor structure, the projected size of the conductive contact hole on the substrate in this embodiment of the invention can be set according to the actual device requirements. This embodiment of the invention only uses 30 micrometers to 50 micrometers as an example, and does not limit the window size of the conductive contact hole.

[0052] In an alternative example where the conductive contact hole 218 penetrates the first dielectric layer 211, the second dielectric layer 212, and a portion of the first metal layer 213, the thickness of the first metal layer 213 exposed by the conductive contact hole 218 can be from 0 to 500 angstroms.

[0053] In an optional example where the conductive contact hole 218 penetrates the first dielectric layer 211 and the second dielectric layer 212, the thickness of the first dielectric layer 211 can be less than 600 angstroms, and the thickness of the second dielectric layer 212 can be less than 600 angstroms. However, to meet the overall size requirements of the semiconductor device, in one specific implementation, the sum of the thicknesses of the first dielectric layer 211 and the second dielectric layer 212 is less than 600 angstroms.

[0054] It should be noted that, with the development of semiconductor devices, in order to adapt to smaller feature sizes, the thicknesses of the first dielectric layer, the second dielectric layer, and the first metal layer in this embodiment can be set according to the actual device requirements. For example, the thickness of the first dielectric layer is less than 600 angstroms, the thickness of the second dielectric layer is less than 600 angstroms, and the thickness of the exposed first metal layer is 0 to 500 angstroms. This does not limit the thickness of the first dielectric layer, the second dielectric layer, and the first metal layer.

[0055] In some embodiments, the material of the first dielectric layer may include one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or titanium dioxide, such as silicon oxide. The material of the second dielectric layer may include one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or titanium dioxide, such as silicon nitride.

[0056] See also Figure 5 As shown, in some embodiments, in order to meet the functional requirements of semiconductor devices, the first device composite layer in this embodiment may further include a second metal layer 219, and the first metal layer 213 conformally covers the second metal layer 219.

[0057] The semiconductor structure in this embodiment may further include a second device composite layer 22 and a support layer 23 located on the substrate 20.

[0058] The support layer 23 can conformally cover the edge of the second device composite layer 22 and extend in a direction away from the second device composite layer 22 to form a platform area with a second preset size Y, wherein the second preset size Y is greater than or equal to the first preset size X.

[0059] The second metal layer 219 is located on the support layer 23 and part of the second device composite layer 22, and the first metal layer 213 is located on the support layer 23 and the second device composite layer 22.

[0060] In some embodiments, the second device composite layer may include at least an interdigitated electrode layer 221, a piezoelectric layer 221, a low-velocity layer 223, and a trap-rich layer 224 stacked sequentially. The piezoelectric layer 221 may be made of lithium tantalate, and the low-velocity layer 223 may be made of silicon dioxide.

[0061] As can be seen, in the embodiments of this utility model, when the projected size of the substrate is greater than or equal to 70% of the first preset size, the conductive contact hole can have a larger contact window, which effectively improves the interfacial bonding force of the conductive pillars filling the conductive contact hole, and increases its contact area with the first metal layer, reduces the contact impedance with the first metal layer, and improves the overall electrical performance of the semiconductor structure.

[0062] As another optional implementation of the disclosure of the present invention, the present invention provides an electronic device that includes the semiconductor structure provided in any of the above embodiments.

[0063] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0064] While the embodiments of this utility model have been disclosed above, this utility model is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this utility model; therefore, the scope of protection of this utility model should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first device composite layer thereon, wherein a portion of the first device composite layer forms a platform region with a first preset size in the functional edge region; The first device composite layer includes at least a first dielectric layer, a second dielectric layer, and a first metal layer stacked sequentially. Corresponding to the functional edge region, the first device composite layer is provided with a sidewall layer and conductive pillars. The conductive pillars fill conductive contact holes and are in contact with the first metal layer. The conductive contact holes penetrate the sidewall layer, the first dielectric layer, and the second dielectric layer, or the conductive contact holes penetrate the sidewall layer, the first dielectric layer, the second dielectric layer, and a portion of the first metal layer. The projected size of the conductive contact holes on the substrate is greater than or equal to 70% of the first preset size.

2. The semiconductor structure according to claim 1, characterized in that, The conductive contact holes are obtained using etching and electroplating processes.

3. The semiconductor structure according to claim 2, characterized in that, The projected size of the conductive contact hole on the substrate is 30 micrometers to 50 micrometers.

4. The semiconductor structure according to claim 2, characterized in that, The thickness of the first metal layer exposed by the conductive contact hole is 0 to 500 angstroms.

5. The semiconductor structure according to claim 2, characterized in that, The thickness of the first dielectric layer is less than 600 angstroms, and the thickness of the second dielectric layer is less than 600 angstroms.

6. The semiconductor structure according to claim 2, characterized in that, The material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or titanium dioxide; The material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or titanium dioxide.

7. The semiconductor structure according to claim 1, characterized in that, The first device composite layer further includes a second metal layer; the first metal layer conformally covers the second metal layer.

8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes a support layer and a second device composite layer located on the substrate; The support layer conformally covers the edge of the second device composite layer and extends in a direction away from the second device composite layer to form a platform area with a second preset size, the second preset size being greater than or equal to the first preset size; The second metal layer is located on the support layer and part of the second device composite layer, and the first metal layer is located on the support layer and the second device composite layer.

9. The semiconductor structure according to claim 8, characterized in that, The second device composite layer includes at least an interdigitated electrode layer, a piezoelectric layer, a low-velocity layer and a trap-rich layer stacked sequentially.

10. An electronic device, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 9.

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