Gate drive chip with negative voltage output, driving device and electronic equipment

Abstract

The utility model relates to the technical field of integrated circuit, especially to a gate drive chip with negative pressure output, driving device, electronic equipment, the gate drive chip with negative pressure output includes at least one drive channel, and each drive channel includes: input side terminal group, at least including signal input terminal, the signal input terminal is used to receive input signal, output side terminal group includes power terminal, signal output terminal, ground terminal, wherein, the power terminal is used to receive power voltage, the signal output terminal is used to output drive signal to the gate of the transistor to be driven, and the ground terminal is used for grounding, negative pressure generates subassembly, sets up in the output side, is used to provide negative current and adjusts drive signal that the signal output terminal exports, the utility model embodiment can reduce the cost, reduces the area of occupation, to adapt the scene of switch speed more and more fast.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a gate driver chip, driver device, and electronic device with negative voltage output. Background Technology

[0002] Power semiconductor driver circuits are primarily used for driving and controlling power semiconductor switching devices such as silicon carbide, silicon, and gallium nitride. They are widely used in the design of power converters, including AC / DC (alternating current to direct current) converters, DC / DC (direct current to direct current) converters, and DC / DC (direct current to AC) converters. End devices include power supplies, motor drives, solar power conversion systems, and new energy vehicles. Current power switch driver chips often require an external negative voltage generator chip to produce negative voltage, resulting in higher costs, larger footprint, and an inability to adapt to increasingly faster switching speeds. Utility Model Content

[0003] In view of this, the present invention proposes a gate driver chip with negative voltage output, wherein the gate driver chip with negative voltage output includes at least one driving channel, and each driving channel includes:

[0004] An input-side terminal group includes at least a signal input terminal, which is used to receive an input signal;

[0005] The output-side terminal group includes a power supply terminal, a signal output terminal, and a ground terminal, wherein the power supply terminal is used to receive power supply voltage, the signal output terminal is used to output a drive signal to the gate of the transistor to be driven, and the ground terminal is used for grounding;

[0006] A negative voltage generating component includes a negative voltage capacitor, the negative voltage terminal of which is connected to the signal output terminal. The first and second terminals of the negative voltage generating component are respectively connected to the positive and negative voltage terminals of the negative voltage capacitor. The positive voltage terminal of the negative voltage capacitor is connected to a drive signal. The negative voltage generating component is used to provide a negative current to regulate the drive signal output by the signal output terminal.

[0007] In one possible implementation, the gate driver chip with negative voltage output includes one driving channel, wherein,

[0008] The number of terminals in the input-side terminal group is at least two, including one signal input terminal and one ground terminal;

[0009] The output-side terminal group has three terminals, including one power terminal, one signal output terminal, and one ground terminal.

[0010] In one possible implementation, the gate driver chip with negative voltage output includes two driving channels, wherein,

[0011] Each drive channel includes one signal input terminal.

[0012] The gate driver chip also includes at least one ground terminal on the input side;

[0013] The gate driver chip also includes at least one power supply terminal and one ground terminal on the output side.

[0014] In one possible implementation, the gate driver chip further includes:

[0015] A signal isolator, connected to the signal input terminal of the input-side terminal group, is used to achieve electrical isolation and signal transmission between the input side and the output side;

[0016] The system includes a driving logic circuit and a power amplifier. The driving signal is input to the input terminal of the driving logic circuit through the signal isolator. The output terminal of the driving logic circuit is connected to the input terminal of the power amplifier, and the output terminal of the power amplifier is connected to the positive terminal of the negative voltage capacitor.

[0017] In one possible implementation, the signal isolator includes at least one of a capacitive isolator, an inductive isolator, and an optocoupler isolator.

[0018] In one possible implementation, the negative voltage generating component includes an oscillator, a first inverter, a second inverter, a first capacitor, a second capacitor, a first diode, a second diode, a first transistor, a second transistor, and a current mirror, wherein:

[0019] The input terminal of the first inverter is connected to the output terminal of the oscillator.

[0020] The input terminal of the second inverter is connected to the output terminal of the first inverter and the first terminal of the first capacitor.

[0021] The first capacitor and the first diode are connected in series between the input terminal of the second inverter and ground.

[0022] The second capacitor and the second diode are connected in series between the output of the second inverter and ground.

[0023] The drain of the first transistor is connected to the common node of the gate of the second transistor, the first capacitor, and the first diode.

[0024] The drain of the second transistor is connected to the common node of the gate of the first transistor, the second capacitor, and the second diode.

[0025] The source of the first transistor and the source of the second transistor are connected to the ground of the current mirror, and the output terminal of the current mirror outputs the negative current to the signal output terminal.

[0026] In one possible implementation, the current mirror includes a first current mirror transistor, a second current mirror transistor, a third current mirror transistor, and a preset current source, wherein,

[0027] The first current mirror transistor has its drain used to receive the preset reference current output by the preset current source and connected to its gate, and its source is connected to the source of the first transistor and the source of the second transistor.

[0028] The third current mirror transistor has its drain used to output the negative current, its gate grounded, and its source connected to the drain of the second current mirror transistor.

[0029] The second current mirror transistor has its gate connected to the gate of the first current mirror transistor, and its source connected to the source of the first transistor and the source of the second transistor.

[0030] According to one aspect of the present invention, a driving device is provided, the driving device comprising the aforementioned gate driving chip with negative voltage output.

[0031] According to one aspect of the present invention, an electronic device is provided, the electronic device including the aforementioned driving device.

[0032] In one possible implementation, the electronic device includes a power supply device and an electric drive device.

[0033] This utility model embodiment integrates a negative voltage generating component inside the gate driver chip and sets up a negative voltage capacitor. The negative voltage end of the negative voltage capacitor is connected to the signal output terminal, and the positive voltage end of the negative voltage capacitor is connected to the drive signal. The negative voltage generating component is used to provide negative current to regulate the drive signal output by the signal output terminal, which can reduce costs and reduce the occupied area to adapt to scenarios with increasingly faster switching speeds.

[0034] Other features and aspects of the present invention will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0035] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of the present invention together with the specification and serve to explain the principles of the present invention.

[0036] Figure 1 A schematic diagram of a gate driver chip with negative voltage output according to an embodiment of the present invention is shown.

[0037] Figure 2 A circuit structure diagram of the negative pressure generating component 30 according to an embodiment of the present invention is shown.

[0038] Figure 3 A schematic diagram of a gate driver chip with negative voltage output according to an embodiment of the present invention is shown.

[0039] Figure 4 A schematic diagram of a gate driver chip with negative voltage output according to an embodiment of the present invention is shown. Detailed Implementation

[0040] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0041] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0042] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0043] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of this inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0044] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0045] Furthermore, to better illustrate this utility model, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this utility model can be implemented even without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail, in order to highlight the main points of this utility model.

[0046] Please see Figure 1, Figure 1 A schematic diagram of a gate driver chip with negative voltage output according to an embodiment of the present invention is shown.

[0047] like Figure 1 As shown, the gate driver chip with negative voltage output includes at least one driving channel 10, and each driving channel 10 includes:

[0048] The input-side terminal group 110 includes at least a signal input terminal 1110, which is used to receive an input signal (such as Vin).

[0049] The output terminal group 120 includes a power supply terminal 2110, a signal output terminal 2120, and a ground terminal 2130. The power supply terminal 2110 is used to receive a power supply voltage (such as VDD), the signal output terminal 2120 is used to output a drive signal (negative voltage drive signal) to the gate of the transistor to be driven (not shown), and the ground terminal 2130 is used for grounding.

[0050] The negative pressure generating component 30 includes a negative pressure capacitor C11. The negative pressure terminal of the negative pressure capacitor C11 is connected to the signal output terminal 2120. The first and second terminals of the negative pressure generating component 30 are respectively connected to the positive and negative pressure terminals of the negative pressure capacitor C11. The positive pressure terminal of the negative pressure capacitor C11 is connected to a drive signal. The negative pressure generating component 30 is used to provide a negative current NEG to regulate the drive signal output by the signal output terminal 2120.

[0051] This embodiment of the invention integrates a negative voltage generating component 30 inside the gate driver chip and sets up a negative voltage capacitor C11. The negative voltage end of the negative voltage capacitor C11 is connected to the signal output terminal 2120, and the positive voltage end of the negative voltage capacitor C11 is connected to the drive signal (Vout). The negative voltage generating component 30 is used to provide a negative current NEG to regulate the drive signal (Vout) output by the signal output terminal 2120. This can reduce costs and reduce the area occupied, in order to adapt to scenarios with increasingly faster switching speeds.

[0052] This utility model embodiment does not limit the specific number of terminals of the drive channel 10, the input side terminal group 110, and the output side terminal group 120. The input side terminal group 110 includes at least one signal input terminal 1110, and the output side terminal group 120 includes at least one power terminal 2110, one signal output terminal 2120, and a ground terminal 2130. Of course, other terminals may also be included, as long as they match the number of pins in the existing package.

[0053] This embodiment of the invention does not limit the specific implementation of the negative pressure generating component 30. Those skilled in the art can use appropriate hardware circuits to implement it according to actual conditions and needs. The following is an exemplary description.

[0054] Please see Figure 2 , Figure 2 A circuit structure diagram of the negative pressure generating component 30 according to an embodiment of the present invention is shown.

[0055] In one possible implementation, such as Figure 2 As shown, the negative pressure generating component 30 includes an oscillator 902, a first inverter 904, a second inverter 906, a first capacitor C1, a second capacitor C2, a first diode D1, a second diode D2, a first transistor Q1, a second transistor Q2, and a current mirror 310, wherein:

[0056] The input terminal of the first inverter 904 is connected to the output terminal of the oscillator 902.

[0057] The input terminal of the second inverter 906 is connected to the output terminal of the first inverter 904 and the first terminal of the first capacitor C1.

[0058] The first capacitor C1 and the first diode D1 are connected in series between the input terminal of the second inverter 906 and ground.

[0059] The second capacitor C2 and the second diode D2 are connected in series between the output terminal of the second inverter 906 and ground.

[0060] The drain of the first transistor Q1 is connected to the common node of the gate of the second transistor Q2, the first capacitor, and the first diode D1.

[0061] The drain of the second transistor Q2 is connected to the common node of the gate of the first transistor Q1, the second capacitor, and the second diode D2.

[0062] The source of the first transistor Q1 and the source of the second transistor Q2 are connected to the ground of the current mirror 310, and the output terminal of the current mirror 310 outputs the negative current NEG to the signal output terminal 2120.

[0063] This embodiment of the invention does not limit the specific implementation of the current mirror 310, such as... Figure 2 As shown, in one possible implementation, the current mirror 310 may include a first current mirror transistor M1, a second current mirror transistor M2, a third current mirror transistor M3, and a preset current source 908, wherein...

[0064] The drain of the first current mirror transistor M1 is used to receive the preset reference current output by the preset current source 908 and is connected to its gate, and its source is connected to the source of the first transistor Q1 and the source of the second transistor Q2.

[0065] The third current mirror transistor M3 has its drain used to output the negative current, its gate grounded, and its source connected to the drain of the second current mirror transistor M2.

[0066] The gate of the second current mirror transistor M2 is connected to the gate of the first current mirror transistor M1, and its source is connected to the source of the first transistor Q1 and the source of the second transistor Q2.

[0067] The source of the first current mirror transistor M1 and the source of the second current mirror transistor M2 are connected together to serve as the ground of the current mirror 310.

[0068] For example, the current mirror may further include a charge pump, and the source of the first transistor Q1 and the source of the second transistor Q2 are also connected to the negative voltage terminal of the charge pump.

[0069] For example, the first transistor Q1, the second transistor Q2, the first current mirror transistor M1, the second current mirror transistor M2, and the third current mirror transistor M3 can all be MOSFET transistors.

[0070] It should be understood that, although this utility model is based on Figure 2 The negative pressure generating component 30 has been described by way of example, but the present invention is not limited to this. The negative pressure generating component 30 can also be implemented in other ways. For example, the number of the first inverter 904 and the second inverter 906 can also be set to other odd numbers to achieve the buffering function of the oscillation signal generated by the oscillator 902.

[0071] This utility model embodiment is illustrated by using one or two drive channels 10 as examples. It should be understood that this exemplary description should not be regarded as a limitation of the utility model embodiment.

[0072] Please see Figure 3 , Figure 3 A schematic diagram of a gate driver chip with negative voltage output according to an embodiment of the present invention is shown.

[0073] In one possible implementation, such as Figure 3 As shown, the gate driver chip with negative voltage output includes one driving channel 10, wherein,

[0074] The input-side terminal group 110 has at least two terminals, including one signal input terminal 1110 and one ground terminal 1130;

[0075] The output terminal group 120 has three terminals, including one power terminal 2110, one signal output terminal 2120, and one ground terminal 2130.

[0076] For example, the gate driver chip with negative voltage output includes 6 terminals, such as the input-side terminal group 110, which may also include a preset function terminal 1120. Figure 3 (Not shown) The specific function of the preset function terminal 1120 is not limited in this embodiment of the utility model, and those skilled in the art can set it according to actual conditions and needs.

[0077] For example, such as Figure 3 As shown, the positive terminal of the negative voltage capacitor C11 is also connected to the negative voltage generating component 30.

[0078] Please see Figure 4 , Figure 4 A schematic diagram of a gate driver chip with negative voltage output according to an embodiment of the present invention is shown.

[0079] In one possible implementation, such as Figure 4 As shown, the gate driver chip with negative voltage output includes two driving channels 10, wherein,

[0080] Each drive channel 10 includes one signal input terminal 1110.

[0081] The gate driver chip also includes a ground terminal 1170 on the input side;

[0082] The gate driver chip also includes at least one power supply terminal 2110 and one ground terminal 2130 on the output side.

[0083] For example, such as Figure 4 As shown, each drive channel 10's output side terminal group 120 may include one signal output terminal 2120, one power supply terminal 2110, and one ground terminal 2130.

[0084] The present invention does not limit the specific number of terminals of the gate driver chip. Those skilled in the art can set it according to actual conditions and needs. For example, the gate driver chip with negative voltage output includes 16 terminals.

[0085] For example, the gate driver chip may further include a power supply terminal 1100 on the input side. Figure 4 (Not shown).

[0086] For example, such as Figure 4As shown, the gate driver chip may also include two preset functional terminals (2140, 2150) on the output side.

[0087] In one possible implementation, such as Figure 3 As shown, the gate driver chip may further include:

[0088] Signal isolator 150 is connected to signal input terminal 1110 of input side terminal group 110 and is used to realize electrical isolation and signal transmission between input side and output side;

[0089] The driving logic circuit 160 and the power amplifier 170 are configured such that the driving signal is input to the input terminal of the driving logic circuit 160 through the signal isolator 150, the output terminal of the driving logic circuit 160 is connected to the input terminal of the power amplifier 170, and the output terminal of the power amplifier 170 is connected to the positive terminal of the negative voltage capacitor C11.

[0090] In one possible implementation, the signal isolator 150 includes at least one of a capacitive isolator, an inductive isolator, an optocoupler isolator, or other devices capable of providing isolation. Of course, the gate driver chip in this embodiment also includes other devices (not shown) to implement the gate driving function of a typical gate driver chip.

[0091] This embodiment of the invention does not change the package definition of the gate driver chip and does not require adding pins. By integrating the negative voltage generating component 30 and the negative voltage capacitor C11 into the gate driver chip, the negative voltage output function of the gate driver chip can be added.

[0092] This embodiment of the invention does not limit the specific implementation of the driving logic circuit and the power amplifier. Those skilled in the art can refer to relevant technologies for implementation. In one example, the driving logic circuit 30 may include a processing component. Exemplarily, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Internally, the processor may be implemented using hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0093] For example, in this embodiment of the present invention, a power amplifier is used to implement the power amplification function. The power amplifier can be used to amplify the input signal Vin received from the driving logic circuit, and output the driving signal to the gate of the target power switch through the signal output port, thereby controlling the conduction and cutoff of the target power switch.

[0094] According to one aspect of the present invention, a driving device is provided, the driving device comprising the aforementioned gate driving chip with negative voltage output.

[0095] According to one aspect of the present invention, an electronic device is provided, the electronic device including the aforementioned driving device.

[0096] In one possible implementation, the electronic device includes a power supply device and an electric drive device.

[0097] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A gate driver chip with negative voltage output, characterized in that, The gate driver chip with negative voltage output includes at least one driving channel, and each driving channel includes: An input-side terminal group includes at least a signal input terminal, which is used to receive an input signal; The output-side terminal group includes a power supply terminal, a signal output terminal, and a ground terminal, wherein the power supply terminal is used to receive power supply voltage, the signal output terminal is used to output a drive signal to the gate of the transistor to be driven, and the ground terminal is used for grounding; A negative voltage generating component includes a negative voltage capacitor, the negative voltage terminal of which is connected to the signal output terminal. The first and second terminals of the negative voltage generating component are respectively connected to the positive and negative voltage terminals of the negative voltage capacitor. The positive voltage terminal of the negative voltage capacitor is connected to a drive signal. The negative voltage generating component is used to provide a negative current to regulate the drive signal output by the signal output terminal.

2. The gate driver chip with negative voltage output according to claim 1, characterized in that, The gate driver chip with negative voltage output includes one driving channel, wherein, The number of terminals in the input-side terminal group is at least two, including one signal input terminal and one ground terminal; The output-side terminal group has three terminals, including one power terminal, one signal output terminal, and one ground terminal.

3. The gate driver chip with negative voltage output according to claim 1, characterized in that, The gate driver chip with negative voltage output includes two driving channels, wherein, Each drive channel includes one signal input terminal. The gate driver chip also includes at least one ground terminal on the input side; The gate driver chip also includes at least one power supply terminal and one ground terminal on the output side.

4. The gate driver chip with negative voltage output according to claim 1, characterized in that, The gate driver chip also includes: A signal isolator, connected to the signal input terminal of the input-side terminal group, is used to achieve electrical isolation and signal transmission between the input side and the output side; The system includes a driving logic circuit and a power amplifier. The driving signal is input to the input terminal of the driving logic circuit through the signal isolator. The output terminal of the driving logic circuit is connected to the input terminal of the power amplifier, and the output terminal of the power amplifier is connected to the positive terminal of the negative voltage capacitor.

5. The gate driver chip with negative voltage output according to claim 4, characterized in that, The signal isolator includes at least one of a capacitive isolator, an inductive isolator, and an optocoupler isolator.

6. The gate driver chip with negative voltage output according to any one of claims 1 to 5, characterized in that, The negative pressure generating assembly includes an oscillator, a first inverter, a second inverter, a first capacitor, a second capacitor, a first diode, a second diode, a first transistor, a second transistor, and a current mirror, wherein: The input terminal of the first inverter is connected to the output terminal of the oscillator. The input terminal of the second inverter is connected to the output terminal of the first inverter and the first terminal of the first capacitor. The first capacitor and the first diode are connected in series between the input terminal of the second inverter and ground. The second capacitor and the second diode are connected in series between the output terminal of the second inverter and ground. The drain of the first transistor is connected to the common node of the gate of the second transistor, the first capacitor, and the first diode. The drain of the second transistor is connected to the common node of the gate of the first transistor, the second capacitor, and the second diode. The source of the first transistor and the source of the second transistor are connected to the ground of the current mirror, and the output terminal of the current mirror outputs the negative current to the signal output terminal.

7. The gate driver chip with negative voltage output according to claim 6, characterized in that, The current mirror includes a first current mirror transistor, a second current mirror transistor, a third current mirror transistor, and a preset current source, wherein... The first current mirror transistor has its drain used to receive the preset reference current output by the preset current source and connected to its gate, and its source is connected to the source of the first transistor and the source of the second transistor. The third current mirror transistor has its drain used to output the negative current, its gate grounded, and its source connected to the drain of the second current mirror transistor. The second current mirror transistor has its gate connected to the gate of the first current mirror transistor, and its source connected to the source of the first transistor and the source of the second transistor.

8. A driving device, characterized in that, The driving device includes a gate driving chip with negative voltage output as described in any one of claims 1-7.

9. An electronic device, characterized in that, The electronic device includes the driving device as described in claim 8.

10. The electronic device according to claim 9, characterized in that, The electronic device includes a power supply device and an electric drive device.

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