Control circuit for laser seed pulse shape editing

Abstract

This utility model relates to a control circuit for editable laser seed pulse shape, comprising an MCU, an FPGA, a high-speed DAC, and a shaping driver module. The host computer sends pulse amplitude, pulse width resolution, and pulse address instructions to the MCU via a communication interface. After parsing the instructions, the MCU sends the corresponding address and data to the FPGA's data processing module. Triggered by the repetition frequency signal output from the selector, the data processing module outputs the pulse amplitude data and conversion clock at the corresponding frequency to the high-speed DAC, generating the edited pulse waveform. Instructions are sent to modify the pulse amplitude and pulse width at the corresponding address, allowing for real-time online editing. The FPGA implements fast logic judgment and high-speed timing waveform output, while the MCU executes the laser application program and communicates with the host computer. The shape of the optical pulse is changed directly by altering the electrical pulse shape, allowing for real-time online editing of the optical pulse waveform. The pulse amplitude is adjustable, and the pulse width and waveform can be arbitrarily edited.

Description

Technical Field

[0001] This utility model relates to a control circuit with editable laser seed pulse shape. Background Technology

[0002] In the field of laser processing, especially with the increasingly widespread application of MOPA (Master Oscillator Power-Amplifier) ​​fiber lasers and the ever-increasing laser power, the shape of the seed pulse directly affects the efficiency of subsequent amplification stages. At the same time, the pulse shape has a significant impact on the processing technology. Unshaped seed pulses are prone to Raman effects after high-power amplification, which can burn out the optical fiber in severe cases, thus directly affecting production capacity and increasing maintenance costs.

[0003] Currently, seed light pulse editing uses an acousto-optic modulator (AOM), which changes the shape of the light pulse by altering the radio frequency power. This method is costly and not very stable. Therefore, there is a need to develop a control circuit with editable laser seed pulse shape. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a control circuit with an editable laser seed pulse shape.

[0005] The objective of this utility model is achieved through the following technical solution:

[0006] The control circuit for programmable laser seed pulse shape features: an MCU, FPGA, high-speed DAC, and shaping driver module; a communication interface connected to the MCU's communication terminal; the MCU's reset output port connected to the FPGA's global reset input; the MCU's address line output port connected to the FPGA's input pin, which in turn connects to the input of its data processing module; the MCU's data line output port connected to the FPGA's input pin, which in turn connects to the input of the data processing module; the MCU's resolution setting data output port connected to the FPGA's input pin, which in turn connects to the input of the data processing module; the MCU's gating output port connected to the FPGA's input pin, which in turn connects to the input of the selector; and the MCU's frequency division data output port connected to the FPGA's input pin, which in turn connects to... The frequency divider's input is connected to the MCU's start output port, which is connected to the FPGA's input pin and thus to the frequency divider's input. The frequency divider's output is connected to the selector's input. The selector's output is connected to the data processing module's trigger input. The external frequency interface is connected to the FPGA's input pin and thus to the selector's input. The crystal oscillator is connected to the FPGA's input pin and thus to the phase-locked loop (PLL) frequency multiplier module's input. The PLL frequency multiplier module's output is connected to both the FPGA's data processing module and the frequency divider's clock input. The data processing module's clock output port is connected to the high-speed DAC's clock input. The data processing module's data output port is connected to the high-speed DAC's data input port. The high-speed DAC's output is connected to the shaping driver module's input.

[0007] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, the crystal oscillator is a 50MHz crystal oscillator.

[0008] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, the high-speed DAC is a DAC908.

[0009] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, the FPGA is an XC6SLX4 FPGA.

[0010] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, the shaping drive module includes a resistor, an operational amplifier, a capacitor, a capacitor, a seed laser diode, and a high-frequency MOSFET. One end of resistor one is connected to the positive input terminal of the operational amplifier, and the other end of resistor one is connected to reference ground. The negative input terminal of the operational amplifier is connected to resistors two and three, as well as one end of capacitor one. The other end of resistor two is connected to reference ground. Resistor three and the other end of capacitor one are connected and connected to the output terminal of the operational amplifier. One end of resistor four is connected to the output terminal of the operational amplifier. The other end of resistor four is connected to one end of capacitor two. The other end of capacitor two is connected to reference ground. The negative terminal of the seed laser diode is connected to the drain of the high-frequency MOSFET. The gate of the high-frequency MOSFET is connected to the output terminal of the operational amplifier. The source of the high-frequency MOSFET is connected to one end of the sampling resistor. The other end of the sampling resistor is connected to reference ground.

[0011] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, the positive terminal of the seed laser diode is connected to a 5V power supply.

[0012] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, the resistance of resistor one is 50 ohms, the resistance of resistor two is 2k ohms, the resistance of resistor three is 500 ohms, the resistance of resistor four is 50 ohms, and the resistance of the sampling resistor is 2 ohms.

[0013] Furthermore, in the aforementioned control circuit for editable laser seed pulse shape, capacitor one has a capacitance value of 10pF, and capacitor two has a capacitance value of 22pF.

[0014] Compared with the prior art, this utility model has significant advantages and beneficial effects, specifically reflected in the following aspects:

[0015] This invention allows for real-time online editing of optical pulse waveforms, enabling not only adjustable pulse amplitude but also arbitrary editing of pulse width and waveform. Narrow and wide pulses are achieved by adjusting the pulse width resolution, with a minimum resolution pulse width of 10 ns achieved using a high-speed DAC. The design includes smoothing filtering of the editable pulse voltage signal and a high-speed drive circuit for the seed laser diode. It allows for switching between internal and external triggering, with the repetition frequency adjustable in real-time during internal triggering. A Field-Programmable Gate Array (FPGA) is used for fast timing logic judgment and high-speed timing waveform output, while a Microcontroller Unit (MCU) handles laser application program execution and communication with the host computer. By directly changing the shape of the electrical pulse to alter the shape of the optical pulse, the method is simple, reliable, and low-cost, effectively preventing fiber optic damage during use.

[0016] Other features and advantages of this invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing specific embodiments of the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 : Circuit diagram of the control circuit of this utility model;

[0019] Figure 2 : Circuit diagram of the shaping drive module;

[0020] Figure 3 : Timing diagram of 50MHz clock, frequency multiplier clock, and frequency division;

[0021] Figure 4 : Timing diagram of stepped pulse signal;

[0022] Figure 5 Schematic diagram of stepped pulse and smooth pulse. Detailed Implementation

[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this utility model, directional and ordinal terms are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] For MOPA fiber lasers, the pulse width needs to be adjusted according to different processing requirements. Lasers of different powers, especially high-power lasers, can have very high single-pulse energy even at very low repetition rates. With a wide seed pulse width, the energy transfer within the fiber after amplification varies significantly depending on the pulse shape. In particular, if the pulse initiation segment is not modified, Raman effects can occur within the fiber, causing energy to concentrate within the fiber instead of being output as amplified signal light, easily burning out the fiber. This invention proposes a control circuit with an editable laser seed pulse shape to directly modify the optical pulse shape by altering the electrical pulse shape.

[0026] like Figure 1 As shown, the control circuit for editable laser seed pulse shape includes MCU2, FPGA3, high-speed DAC6, and shaping drive module 7. Communication interface 1 is connected to the communication terminal of MCU2; the reset output port of MCU2 is connected to the global reset input terminal of FPGA3; the address line output port of MCU2 is connected to the input pin of FPGA3, which in turn is connected to the input terminal of its data processing module 301; the data line output port of MCU2 is connected to the input pin of FPGA3, which in turn is connected to the input terminal of data processing module 301; the resolution setting data output port of MCU2 is connected to the input pin of FPGA3, which in turn is connected to the input terminal of data processing module 301; the gating output port of MCU2 is connected to the input pin of FPGA3, which in turn is connected to the input terminal of selector 303; the frequency division data output port of MCU2 is connected to the input pin of FPGA3, which in turn is connected to the input terminal of frequency divider 302. The MCU2's start output port is connected to the FPGA3's input pin, which in turn connects to the input of the frequency divider 302. The output of the frequency divider 302 is connected to the input of the selector 303. The output of the selector 303 is connected to the trigger input of the data processing module 301. The external frequency interface 4 is connected to the FPGA3's input pin, which in turn connects to the selector 303. The crystal oscillator 5 is connected to the FPGA3's input pin, which in turn connects to the input of the phase-locked loop frequency multiplier module 304. The output of the phase-locked loop frequency multiplier module 304 is connected to the clock inputs of the FPGA3's data processing module 301 and the frequency divider 302, respectively. The clock output port of the data processing module 301 is connected to the clock input of the high-speed DAC6. The data output port of the data processing module 301 is connected to the data input port of the high-speed DAC6. The output of the high-speed DAC6 is connected to the input of the shaping drive module 7.

[0027] The bridge section of the entire circuit is FPGA3, which is a Xilinx XC6SLX4 FPGA. It includes a data processing module 301, a frequency divider 302, a selector 303, and a phase-locked loop frequency multiplier module 304. It has many digital input and output pins and a maximum clock rate of 220MHz.

[0028] The high-speed DAC (Digital to Analog Converter) 6 uses TI's DAC908, a current-mode output with 8-bit resolution, 256 signal amplitude changes (minimum amplitude 0, maximum amplitude 255 units), and requires only 2 clock cycles to complete the conversion. Its maximum conversion rate reaches 100MHz, allowing for a minimum signal width of 10ns. The signal is a pulse; for a wider pulse width, multiple pulses can be continuously spliced ​​together. For example, a 100ns pulse requires 10 pulses. By setting the amplitude data for each pulse in the high-speed DAC 6, a stepped pulse signal is generated.

[0029] The data processing module 301 transmits 8-bit data, i.e., sets the pulse amplitude of the high-speed DAC6; it also enables the splicing of multiple pulses. Taking 16 pulses as an example, 4 address lines are used, with each address corresponding to a specific pulse; the pulse width resolution is set. Since a wide pulse width is required in practical applications, and the total width of 16 pulses is 160ns, this invention adjusts the width of a single pulse output from the high-speed DAC6. Taking a 3-bit resolution width as an example, since the 200MHz multiplier clock period is 5ns, the minimum pulse width resolution is 10ns, and the maximum pulse width resolution is 10 + 7 * 5 = 45ns, the maximum pulse width achieved is 16 * 45 = 720ns. In practical applications, the pulse width resolution is set as needed.

[0030] like Figure 2The shaping drive module 7 includes resistor R1, operational amplifier U1, capacitor C1, capacitor C2, seed laser diode LD, and high-frequency MOSFET Q1. One end of resistor R1 is connected to the positive input terminal of operational amplifier U1, i.e., the input terminal of shaping drive module 7; the other end of resistor R1 is connected to reference ground. The negative input terminal of operational amplifier U1 is connected to resistors R2 and R3, as well as one end of capacitor C1; the other end of resistor R2 is connected to reference ground; the other end of resistor R3 and capacitor C1 are connected and connected to the output terminal of operational amplifier U1; one end of resistor R4 is connected to the output terminal of operational amplifier U1; the other end of resistor R4 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to reference ground; the positive terminal of seed laser diode LD is connected to a 5V power supply, and the negative terminal of seed laser diode LD is connected to the drain of high-frequency MOSFET Q1; the gate of high-frequency MOSFET Q1 is connected to the output terminal of operational amplifier U1; the source of high-frequency MOSFET is connected to one end of sampling resistor R5; the other end of sampling resistor R5 is connected to reference ground. The host computer sends instructions to the MCU2 through communication interface 1 to set parameters. The MCU2 interacts with the data processing module 301 and frequency divider 302 of the FPGA3. The FPGA3 performs logic timing control and quickly changes the data settings of the high-speed DAC6 at each repetition frequency beat. The high-speed DAC6 outputs a corresponding stepped current signal to the shaping drive module 7, and generates a stepped voltage signal to the operational amplifier U1 under the action of resistor R1 in the shaping drive module 7. After amplification and smoothing filtering, the voltage signal controls the high-frequency MOS transistor Q1 to drive the laser diode LD to emit light. The seed laser diode LD generates pulse light with adjustable repetition frequency and editable waveform.

[0031] Among them, the resistance of resistor 1 R1 is 50 ohms, the resistance of resistor 2 R2 is 2k ohms, the resistance of resistor 3 R3 is 500 ohms, the capacitance of capacitor 1 C1 is 10pF, the resistance of resistor 4 R4 is 50 ohms, the capacitance of capacitor 2 C2 is 22pF, and the resistance of sampling resistor R5 is 2 ohms.

[0032] MCU2 outputs a low-level reset signal (at the microsecond level) to FPGA3. FPGA3 then resets all registers using the clock signal input from crystal oscillator 4. Crystal oscillator 5 is a 50MHz crystal oscillator. The 50MHz frequency signal generated by crystal oscillator 5 is input to the frequency multiplier phase-locked loop module 304 within FPGA3, where it is multiplied by 4 to output a 200MHz multiplied clock signal. By default, the strobe signal of MCU2 is low, meaning that selector 303 selects the frequency signal output from frequency divider 302. This is an internal control trigger mode. The laser operates at different repetition frequencies, and the corresponding frequencies are set. The host computer sends frequency parameters to MCU2 via communication interface 1. MCU2 converts the frequency parameters into corresponding data and sends them to frequency divider 302. Simultaneously, MCU2 sends a start signal to frequency divider 302. Frequency divider 302 divides the 200MHz multiplier clock and outputs the repetition frequency signal to the selection input port of selector 303. Selector 303 outputs the repetition frequency signal to data processing module 301. The timing sequence of the 50MHz crystal oscillator clock, the 200MHz multiplier clock, and the repetition frequency output by frequency divider 302 is as follows: Figure 3 As shown.

[0033] The host computer sends an external control mode command to MCU2, and the working mode is switched to external control trigger mode. When the MCU2 outputs a high level strobe signal, selector 303 selects the repetition frequency signal input from external frequency interface 4 and outputs it to data processing module 301.

[0034] The host computer sends pulse amplitude instructions, pulse width resolution instructions, and pulse address instructions to MCU2 through communication interface 1. After MCU2 parses the instructions, it sends the corresponding address and data to data processing module 301. Under the triggering of the repetition frequency signal output by selector 303, data processing module 301 outputs the corresponding pulse amplitude data and conversion clock to high-speed DAC6 to generate the edited pulse waveform; it also sends instructions to modify the pulse amplitude and pulse width of the corresponding address, enabling real-time online editing.

[0035] Taking the concatenation of three pulses as an example, data transmission and the generation of stepped pulses are achieved. Of the 16 pulses, the amplitude values ​​of the first three pulses are set, and the amplitude values ​​of the rest are set to 0. After the trigger signal arrives, the data processing module 301, at a 200MHz clock cycle, first outputs the data of the first pulse amplitude to the input data terminal of the high-speed DAC6, then outputs a clock pulse to the clock terminal of the high-speed DAC6 for data latching. After one cycle (5ns), it outputs another clock pulse to the DAC6, simultaneously outputting the data of the second pulse amplitude. After 5ns, the high-speed DAC6 outputs the first pulse amplitude, and the data processing module 301 again outputs a clock pulse to the clock terminal of the high-speed DAC6 for data latching. After one cycle, it outputs another pulse to the high-speed DAC6, simultaneously outputting the data of the third pulse amplitude. After 5ns, the high-speed DAC6 outputs the first pulse amplitude. The data processing module 301 then outputs another clock pulse to the clock terminal of the high-speed DAC6 for data latching. After one cycle, it outputs another pulse to the high-speed DAC6, simultaneously outputting the data of the third pulse amplitude. After 5ns, the high-speed DAC6 outputs the first pulse amplitude. DAC6 outputs the second pulse amplitude, and the third pulse amplitude is output in the same way. The amplitude of the fourth pulse starts at 0, resulting in a stepped pulse signal composed of three pulses with varying amplitudes. Each pulse amplitude is maintained for 10 ns. When only one pulse amplitude is set, and the rest are 0, a minimum pulse width of 10 ns is obtained. After the data processing module 301 continuously sends two clock pulses to the high-speed DAC6, it inserts N wait periods. The high-speed DAC6 will maintain this amplitude value after completing the conversion and outputting the corresponding signal amplitude until the data processing module 301 sends pulse amplitude data and clock pulses to the high-speed DAC6 again after the N wait periods. This wait period is the pulse width resolution; the larger the resolution value, the longer each step is maintained, and the wider the final stepped pulse signal. The data processing module 301 performs data transmission and conversion on the high-speed DAC6 at a 200MHz clock and finally forms the stepped pulse signal timing diagram, as shown below. Figure 4 .

[0036] The aforementioned stepped pulse is input to the shaping driver module 7. The high-speed DAC6 is current-driven; when the amplitude setting for the high-speed DAC6 is 0, the output current I = 0. When the amplitude setting is 255, the output current is at its maximum. The stepped pulse is actually the change in the stepped pulse current I. After passing through resistor R1, the current forms a stepped voltage signal Ui, where Ui = R1 * I. Ui is input to a proportional operational amplifier circuit composed of resistors R2 and R3, and operational amplifier U1 for amplification. The amplification factor is F = 1 + R3 / R2. The operational amplifier U1... The output voltage is Uo = (1 + R3 / R2)Ui, and capacitor C1 is used for high-frequency filtering; the maximum output current I of the high-speed DAC6 is 20mA; R1 = 50 ohms, R2 = 2k ohms, R3 = 500 ohms, and C1 = 10pF; the amplified stepped voltage signal output by operational amplifier 6 is smoothed by a smoothing filter composed of resistor R4 and capacitor C2, with R4 = 50 ohms and C2 = 22pF, thus obtaining a relatively smooth pulse voltage signal. The system operates at a set repetition frequency, thereby outputting pulses with the corresponding repetition frequency, such as... Figure 5 .

[0037] The smoothed and filtered pulse voltage Uo is input to the control gate of the high-frequency MOSFET Q1, which rapidly controls the pulse current output between the drain and source of the high-frequency MOSFET Q1, forming a waveform consistent with the control voltage Uo, which is the pulse current waveform flowing through the laser diode LD. This current waveform makes the shape of the seed light pulse emitted by the laser diode LD consistent with the current pulse waveform. Resistor R5 is a high-power resistor used to limit the current and ensure that the laser diode LD is not damaged by overcurrent. R5 = 2 ohms. Changing the amplitude value of the spliced ​​pulse can change the height of the light pulse. At the same time, changing the number of spliced ​​pulses or changing the pulse width resolution can change the width of the light pulse. The host computer sets parameters to MCU2 through communication interface 1 and edits the light pulse in real time online.

[0038] In summary, this invention enables real-time online editing of optical pulse waveforms, allowing not only adjustable pulse amplitude but also arbitrary editing of pulse width and waveform. Narrow and wide pulses are achieved by adjusting the pulse width resolution, with a minimum resolution pulse width of 10 ns achieved using a high-speed DAC. The design includes smoothing filtering of the editable pulse voltage signal and a high-speed drive circuit for the seed laser diode. It allows switching between internal and external triggering, with the repetition frequency adjustable in real-time during internal triggering. A Field-Programmable Gate Array (FPGA) is used for fast timing logic judgment, and a Microcontroller Unit (MCU) is used to execute the laser application program and communicate with the host computer. Directly changing the shape of the electrical pulse to alter the shape of the optical pulse is simple, reliable, and low-cost, effectively preventing fiber optic damage during use.

[0039] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures.

[0040] The above are merely specific embodiments of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, utility model, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, utility model, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, utility model, article, or apparatus that includes said element.

Claims

1. A control circuit with editable laser seed pulse shape, characterized in that: Includes MCU (2), FPGA (3), high-speed DAC (6), and shaping driver module (7); the reset output port of MCU (2) is connected to the global reset input of FPGA (3); the address line output port of MCU (2) is connected to the input pin of FPGA (3) and then to the input of its data processing module (301); the data line output port of MCU (2) is connected to the input pin of FPGA (3) and then to the input of data processing module (301); the resolution setting data output port of MCU (2) is connected to the input pin of FPGA (3) and then to the input of data processing module (301); the gating output port of MCU (2) is connected to the input pin of FPGA (3) and then to the input of selector (303); the frequency division data output port of MCU (2) is connected to the input pin of FPGA (3) and then to the input of frequency divider (302); the start output port of MCU (2) is connected to the FPGA (6) and then to the input of frequency divider (302); the start output port of MCU (2) is connected to the FPGA (6) and then to the input of FPGA (7). 3) The input pins are connected to the input of the frequency divider (302); the output of the frequency divider (302) is connected to the input of the selector (303); the output of the selector (303) is connected to the trigger input of the data processing module (301); the external frequency interface (4) is connected to the input pin of the FPGA (3) and then to the input of the selector (303); the crystal oscillator (5) is connected to the input pin of the FPGA (3) and then to the input of the phase-locked loop frequency multiplier module (304); the output of the phase-locked loop frequency multiplier module (304) is connected to the clock input of the data processing module (301) and the frequency divider (302) of the FPGA (3) respectively; the clock output port of the data processing module (301) is connected to the clock input of the high-speed DAC (6); the data output port of the data processing module (301) is connected to the data input port of the high-speed DAC (6); the output of the high-speed DAC (6) is connected to the input of the shaping drive module (7).

2. The control circuit with editable laser seed pulse shape according to claim 1, characterized in that: The crystal oscillator (5) is a 50MHz crystal oscillator.

3. The control circuit with editable laser seed pulse shape according to claim 1, characterized in that: The FPGA (3) is an FPGA of model XC6SLX4.

4. The control circuit with editable laser seed pulse shape according to claim 1, characterized in that: The shaping drive module (7) includes a resistor (R1), an operational amplifier (U1), a capacitor (C1), a capacitor (C2), a seed laser diode (LD), and a high-frequency MOSFET (Q1). One end of the resistor (R1) is connected to the positive input terminal of the operational amplifier (U1), and the other end of the resistor (R1) is connected to a reference ground. The negative input terminal of the operational amplifier (U1) is connected to one end of the resistors (R2) and (R3) and the capacitor (C1). The other end of the resistor (R2) is connected to a reference ground. The other end of the resistor (R3) and the capacitor (C1) are connected to a reference ground. One end of the resistor is connected to the output of the operational amplifier (U1); one end of the resistor (R4) is connected to the output of the operational amplifier (U1); the other end of the resistor (R4) is connected to one end of the capacitor (C2); the other end of the capacitor (C2) is connected to the reference ground; the negative terminal of the seed laser diode (LD) is connected to the drain of the high-frequency MOSFET (Q1); the gate of the high-frequency MOSFET (Q1) is connected to the output of the operational amplifier (U1); the source of the high-frequency MOSFET is connected to one end of the sampling resistor (R5); the other end of the sampling resistor (R5) is connected to the reference ground.

5. The control circuit with editable laser seed pulse shape according to claim 4, characterized in that: The positive terminal of the seed laser diode (LD) is connected to a 5V power supply.

6. The control circuit with editable laser seed pulse shape according to claim 4, characterized in that: The resistance of resistor 1 (R1) is 50 ohms, the resistance of resistor 2 (R2) is 2k ohms, the resistance of resistor 3 (R3) is 500 ohms, the resistance of resistor 4 (R4) is 50 ohms, and the resistance of sampling resistor (R5) is 2 ohms.

7. The control circuit with editable laser seed pulse shape according to claim 4, characterized in that: The capacitance of capacitor 1 (C1) is 10pF, and the capacitance of capacitor 2 (C2) is 22pF.

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