Clock synchronization circuit, audio device, and audio system

Abstract

The application relates to a clock synchronization circuit, an audio device and an audio system. When there is no clock signal input, the clock synchronization circuit can generate an internal clock signal by a self-control circuit, and a synchronous clock signal with consistent clock frequency can be obtained based on the internal clock signal. The synchronous clock signal is used for an external device, so that the device is clock-synchronized with the external device based on the internal clock signal. When there is an external clock signal input, the device uses the external clock signal to obtain a clock synchronization signal with consistent clock frequency, which is used for the external device, so that the device is clock-synchronized with the external device based on the external clock signal. The application can maintain clock synchronization among multiple audio devices while simplifying the circuit and reducing the circuit volume.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a clock synchronization circuit, an audio device, and an audio system. Background Technology

[0002] Typically, when multiple devices work together online, clock asynchrony can lead to system errors. For example, when multiple audio devices are recording synchronously, if their clocks are out of sync, data packets will be misaligned, causing sample point loss or overlap, resulting in harsh popping noises. However, there are many word clock synchronization circuit components on the market, and to ensure high-precision clock synchronization, the circuit design and layout are complex, resulting in a large circuit size. Utility Model Content

[0003] The purpose of this application is to provide a clock synchronization circuit, audio device, and audio system, aiming to solve the problems of numerous components, complex layout, and large size of word clock synchronization circuits in related technologies.

[0004] In a first aspect, embodiments of this application provide a clock synchronization circuit, including: A clock transmission circuit, connected to an input interface and an output interface, is used to receive an external clock signal or an internal clock signal from the input interface, and output a synchronous clock signal with the same clock frequency from the output interface based on the external clock signal or the internal clock signal. A control circuit, connected to the clock transmission circuit, is used to generate the internal clock signal or receive and output the external clock signal; A clock configuration circuit, connected to the control circuit, is used to configure a target clock signal according to the external clock signal or the internal clock signal; The synchronous clock signal, the external clock signal, and the internal clock signal all have the same clock frequency.

[0005] In one embodiment, the clock transmission circuit includes: The clock transmission circuit includes a level converter, which includes: The first input terminal is connected to the input interface; The first output terminal is connected to the first input terminal and is also connected to the input port of the control circuit. The second input terminal is connected to the first output port of the control circuit to receive the internal clock signal, and the second output port of the control circuit is connected to the clock configuration circuit. The second output terminal is connected to the second input terminal and is also connected to the output interface; Wherein, the first output terminal is connected to the second input terminal; or, the control circuit is used to forward the external clock signal received by the input port to the first output port.

[0006] In one embodiment, the clock transmission circuit further includes a buffer connected between the second output of the level converter and the output interface.

[0007] In one embodiment, both the input interface and the output interface are equipped with filters and electrostatic discharge protectors.

[0008] In one embodiment, the clock configuration circuit includes: A phase-locked loop circuit, wherein the signal input terminal of the phase-locked loop circuit is connected to the control circuit, and is used to configure at least one clock signal according to the external clock signal or the internal clock signal, wherein the target clock signal includes the at least one clock signal; A crystal oscillator circuit is connected to the crystal input terminal of the phase-locked loop circuit and is used to provide a crystal oscillator signal to the phase-locked loop circuit.

[0009] In one embodiment, the control circuit further includes a detection port, which is used to shut down the output of the internal clock signal of the first output port when the external clock signal is connected to the input port.

[0010] In one embodiment, the detection port and input port of the control circuit are the same port.

[0011] Secondly, embodiments of this application provide an audio device, including an audio sampling circuit and the aforementioned clock synchronization circuit, wherein the audio sampling circuit is connected to the clock synchronization circuit and is used to perform audio sampling based on the target clock signal.

[0012] In one embodiment, the control circuit further includes: The data output port is connected to the data port of the clock configuration circuit and is used to configure the parameters of the target clock signal.

[0013] A transmission configuration port is connected to the configuration port of the clock configuration circuit and is used to configure the transmission of the data output port.

[0014] Thirdly, this application provides an audio system including multiple audio devices as described above, wherein the clock synchronization circuits of each audio device are connected in series, wherein the input interface of the clock synchronization circuit of the subsequent audio device is connected to the output interface of the clock synchronization circuit of the preceding audio device, and the synchronization clock signal output by the clock synchronization circuit of the preceding audio device is input as an external clock signal to the clock transmission circuit of the subsequent audio device.

[0015] The beneficial effects of this application embodiment compared with related technologies are as follows: The clock synchronization circuit provided in this application embodiment includes a clock transmission circuit, a control circuit, and a clock configuration circuit. The clock transmission circuit is used to receive an external clock signal or an internal clock signal from the input interface, and output a synchronous clock signal from the output interface based on the external clock signal or the internal clock signal. The control circuit is connected to the clock transmission circuit and is used to generate an internal clock signal, or receive an external clock signal and output it. The clock configuration circuit is connected to the control circuit and is used to configure a target clock signal according to the external clock signal or the internal clock signal. The clock frequencies of the synchronous clock signal, the external clock signal, and the internal clock signal are consistent. The clock synchronization circuit provided in this application can generate an internal clock signal by its own control circuit when there is no clock signal input, and obtain a synchronized clock signal with the same clock frequency based on the internal clock signal. This synchronized clock signal is used by external devices, so the device is synchronized with the clock of the external device based on the internal clock signal. When there is an external clock signal input, the device uses the external clock signal to obtain a clock synchronization signal with the same clock frequency, which is used by the external device. So the device is synchronized with the clock of the external device based on the external clock signal. This proposal can maintain clock synchronization between multiple audio devices while simplifying the circuit and reducing the circuit size. Attached Figure Description

[0016] Figure 1 A schematic diagram of the structure of an audio system and its clock synchronization circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the clock transmission circuit of a clock synchronization circuit provided in an embodiment of this application; Figure 3 A schematic diagram of the clock transmission circuit of a clock synchronization circuit provided in an embodiment of this application; Figure 4 A schematic diagram of the clock transmission circuit of a clock synchronization circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the clock configuration circuit of a clock synchronization circuit provided in an embodiment of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0020] When multiple audio devices are recording, asynchronous audio clocks can lead to misaligned data packets, resulting in lost or overlapping sampling points and producing harsh popping noises. However, ensuring high-precision clock synchronization circuit design and layout requires a compact size. Therefore, this application provides a clock synchronization circuit that can simultaneously satisfy audio clock synchronization requirements and achieve a small footprint.

[0021] Please see Figure 1 This application provides an audio system including multiple audio devices 10, each audio device 10 including a clock synchronization circuit 100, and the clock synchronization circuits 100 of each audio device 10 are connected in series. The input interface 101 of the clock synchronization circuit 100 of the subsequent audio device 10 is connected to the output interface 102 of the clock synchronization circuit 100 of the preceding audio device 10, and the synchronization clock signal output by the clock synchronization circuit 100 of the preceding audio device 10 is input as an external clock signal to the clock transmission circuit 110 of the subsequent audio device 10.

[0022] In this serial clock synchronization circuit 100, if an external clock signal Clk1 is input to the input interface 101 (e.g., from the first clock synchronization circuit 100), each clock synchronization circuit 100 can synchronize clocks based on this external clock signal Clk1 at the same clock frequency. If there is no external clock signal Clk1 input, the first clock synchronization circuit 100 in the serial clock synchronization circuit 100 can be configured to generate an internal clock signal Clk2, and output a synchronization clock signal Clk3 at the same clock frequency to its output interface 102 based on this internal clock signal Clk2, serving as the reference for clock synchronization of all remaining clock synchronization circuits 100. In this way, multiple audio devices 10 recording audio at the same clock frequency will not cause data packet misalignment leading to sample point loss or overlap, thus preventing the generation of harsh popping noise.

[0023] The audio device 10 is, for example, a microphone, a recording device including a microphone, or a conferencing device including a microphone. In some scenarios, the multiple audio devices 10 are cascaded to record audio in the same or different areas.

[0024] Please see Figure 1 One embodiment of this application provides a clock synchronization circuit 100, including a clock transmission circuit 110, a control circuit 120, and a clock configuration circuit 130.

[0025] Clock transmission circuit 110 is connected to input interface 101 and output interface 102, and is used to receive external clock signal Clk1 or internal clock signal Clk2 from input interface 101, and output a synchronous clock signal Clk3 with the same clock frequency from output interface 102 based on external clock signal Clk1 or internal clock signal Clk2. Control circuit 120 is connected to clock transmission circuit 110, and is used to generate internal clock signal Clk2, or receive external clock signal Clk1 and output it. Clock configuration circuit 130 is connected to control circuit 120, and is used to configure target clock signal Clk4 according to external clock signal Clk1 or internal clock signal Clk2.

[0026] When the input interface 101 receives an external clock signal Clk1, the clock transmission circuit 110 outputs a synchronous clock signal Clk3 at the same clock frequency as the external clock signal Clk1 at the output interface 102. When the output interface 102 does not receive the external clock signal Clk1, the control circuit 120 generates an internal clock signal Clk2 and outputs it to the clock transmission circuit 110. The clock transmission circuit 110 then outputs a synchronous clock signal Clk3 at the same clock frequency as the internal clock signal Clk2 at the output interface 102. It can be understood that the synchronous clock signal Clk3 output by the output interface 102 serves as the external clock signal Clk1 of the external synchronous clock circuit. For example, the frequency of the internal clock signal Clk2 depends on the sampling rate of the audio signal by the audio device 10.

[0027] The internal clock signal Clk2 generated by the control circuit 120 is output to the clock configuration circuit 130 for use by the device. For example, when the clock synchronization circuit 100 is used by the audio device 10, the clock configuration circuit 130 is also connected to the audio sampling circuit. The audio sampling circuit will perform audio sampling based on the target clock signal Clk4, so that each audio device 10 can perform audio sampling based on a clock signal with the same clock frequency.

[0028] Please see Figure 2 and Figure 3 In one embodiment, the clock transmission circuit 110 includes a level converter 111, which includes a first input terminal A1, a first output terminal B1, a second input terminal B2, and a second output terminal A2.

[0029] The first input terminal A1 is connected to the input interface 101 and is used to receive the external clock signal Clk1. The first output terminal B1 is connected to the first input terminal A1 and is connected to the input port TP1 of the control circuit 120.

[0030] For example, the level converter 111 can limit (e.g., reduce) the external clock signal Clk1 input to the first input terminal A1 and output it from the second output terminal A2 to the input port TP1 of the control circuit 120, for example, reducing it to 3.3VPP (peak-to-peak voltage) to suit the input range of the control circuit 120 so as to prevent damage to the control circuit 120.

[0031] The second input terminal B2 is connected to the first output port TP2 of the control circuit 120 to receive the internal clock signal Clk2. The second output port TP3 of the control circuit 120 is connected to the clock configuration circuit 130 to output the internal clock signal Clk2 or the external clock signal Clk1 to the clock configuration circuit 130. The second output terminal A2 is connected to the second input terminal B2 and is also connected to the output interface 102.

[0032] In one embodiment, when input interface 101 receives an external clock signal Clk1, see [reference]. Figure 2 The first output terminal B1 is connected to the second input terminal B2, and the first output terminal B1 inputs the external clock signal Clk1 to the second input terminal B2. (See also...) Figure 3 In one embodiment, the control circuit 120 is used to forward the external clock signal Clk1 received at the input port TP1 to the first output port TP2, and output the received external clock signal Clk1 to the second input terminal B2 of the level converter 111 through the first output port TP2.

[0033] For example, the level converter 111 can limit (e.g., amplify) the internal clock signal Clk2 or the external clock signal Clk1 input to the second input terminal B2 and output it as a synchronization clock signal Clk3 from the second output terminal A2 to the output interface 102, for example, amplifying it to 5VPP, to adapt to the input range of the subsequent circuit, such as the external clock synchronization circuit 100, thereby improving the reliability and stability of the clock synchronization signal transmission. It is understood that the clock signal output from the first output terminal B1 of the level converter 111 and the clock signal output from the second output terminal A2 have the same clock frequency, but their amplitudes may be different.

[0034] Please see Figure 3 In one embodiment, the clock transmission circuit 110 further includes a buffer 112. The buffer 112 is connected between the second output terminal A2 of the level converter 111 and the output interface 102.

[0035] For example, buffer 112 is used to enhance the driving capability of the output synchronous clock signal Clk3, so as to facilitate the identification and cascading of the next-level audio device 10.

[0036] Please see Figure 4 In one embodiment, the input interface 101 and output interface 102 of the clock transmission circuit 110 are both equipped with filters and electrostatic discharge protectors.

[0037] For example, the electrostatic discharge protector includes TVS diodes D1 and D2, which are respectively connected between the first input terminal A1 of the clock transmission circuit 110 and the ground terminal. The first output terminal B1 of the clock transmission circuit 110 is used for electrostatic discharge protection.

[0038] For example, the filter includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The first resistor R1 and the second resistor R2 are connected in series at the first input terminal A1 and the first output terminal B1 of the clock transmission circuit 110, respectively. The first capacitor C1 and the second capacitor C2 are connected between the first input terminal A1 of the clock transmission circuit 110 and ground. The first output terminal B1 of the clock transmission circuit 110, the first resistor R1, and the first capacitor C1 constitute a first RC filter for input filtering and impedance matching. The second resistor R2 and the second capacitor C2 constitute a second RC filter for output filtering and impedance matching.

[0039] Please see Figure 5 In one embodiment, the clock configuration circuit 130 includes a phase-locked loop circuit 131 and a crystal oscillator circuit 132.

[0040] The signal input terminal of the phase-locked loop circuit 131 is connected to the first output port TP2 of the control circuit 120, and is used to configure at least one clock signal according to the external clock signal Clk1 or the internal clock signal Clk2. The target clock signal Clk4 includes at least one clock signal. The crystal oscillator circuit 132 is connected to the crystal oscillator input terminal of the phase-locked loop circuit 131, and is used to provide a crystal oscillator signal to the phase-locked loop circuit 131.

[0041] The phase-locked loop circuit 131 includes a frequency synthesizer. For example, at least one clock signal includes a first clock signal LRCK and a second clock signal BCLK, which are in phase with either an external clock signal Clk1 or an internal clock signal Clk2. The frequency of the first clock signal LRCK is an integer multiple of the frequency of the second clock signal BCLK. These first clock signals LRCK and BCLK are typically used for clock synchronization of the audio sampling circuit of the audio device 10.

[0042] For example, at least one clock signal also includes a third clock signal MCLK, the phase and frequency of which are inconsistent with the first clock signal LRCK, and the frequency is a non-integer multiple. The third clock signal MCLK is generally used to provide a reference for circuits other than the audio sampling circuit of the audio device 10.

[0043] In one embodiment, the control circuit 120 further includes: Data output ports TP4 / TP5 are connected to the data port of clock configuration circuit 130 and are used to configure the parameters of the target clock signal Clk4. The transmission configuration port TP6 is connected to the configuration port of the clock configuration circuit 130 and is used to configure the transmission of data output ports TP4 / TP5.

[0044] For example, data output ports TP4 / TP5 and transmission configuration port TP6 are ports of the frequency synthesizer. Transmission configuration port TP6 is used to output configuration signals to configure the data protocol for data transmission between control circuit 120 and clock configuration circuit 130, such as using the SPI protocol or I... 2 C protocol. For example, I... 2 C protocol, then control circuit 120 enables I 2 Communication between the data output ports TP4 / TP5 of C and the clock configuration circuit 130.

[0045] It is understandable that the control circuit 120 configures the parameters of the target clock signal Clk4 according to the system requirements of the device. For example, it configures the phase and frequency of the first clock signal LRCK, the second clock signal BCLK, and the third clock signal MCLK.

[0046] In one embodiment, the control circuit 120 further includes a detection port, which is used to shut down the output of the internal clock signal Clk2 of the first output port TP2 and switch to clock synchronization based on the external clock signal Clk1 when the input is disconnected and an external clock signal Clk1 is connected. For example, the audio device 10 adjusts the audio sampling rate to match the external clock signal Clk1.

[0047] In one embodiment, the detection port and input port TP1 of the control circuit 120 are the same port, thereby saving ports of the control circuit 120.

[0048] For example, the control circuit 120 includes a control chip, such as an MCU (microprocessor). When the clock synchronization circuit 100 is applied to the audio device 10, any of the main control chips in the audio device 10 can be directly used as the control circuit 120.

[0049] This application also provides an audio device 10, including an audio sampling circuit and a clock synchronization circuit 100 of any of the above embodiments. The audio sampling circuit is connected to the clock synchronization circuit 100 and is used to perform audio sampling based on the target clock signal Clk4.

[0050] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A clock synchronization circuit, characterized by, include: A clock transmission circuit, connected to an input interface and an output interface, is used to receive an external clock signal or an internal clock signal from the input interface, and output a synchronous clock signal with the same clock frequency from the output interface based on the external clock signal or the internal clock signal. A control circuit, connected to the clock transmission circuit, is used to generate the internal clock signal or receive and output the external clock signal; A clock configuration circuit, connected to the control circuit, is used to configure a target clock signal according to the external clock signal or the internal clock signal.

2. The clock synchronization circuit as described in claim 1, characterized in that, The clock transmission circuit includes a level converter, which includes: The first input terminal is connected to the input interface; The first output terminal is connected to the first input terminal and is also connected to the input port of the control circuit. The second input terminal is connected to the first output port of the control circuit to receive the internal clock signal, and the second output port of the control circuit is connected to the clock configuration circuit. The second output terminal is connected to the second input terminal and is also connected to the output interface; Wherein, the first output terminal is connected to the second input terminal; or, the control circuit is used to forward the external clock signal received by the input port to the first output port.

3. The clock synchronization circuit of claim 2, wherein, The clock transmission circuit also includes a buffer connected between the second output terminal of the level converter and the output interface.

4. The clock synchronization circuit of claim 2, wherein, Both the input interface and the output interface are equipped with filters and electrostatic discharge protectors.

5. The clock synchronization circuit of any one of claims 1 to 4, wherein, The clock configuration circuit includes: A phase-locked loop circuit, wherein the signal input terminal of the phase-locked loop circuit is connected to the control circuit, and is used to configure at least one clock signal according to the external clock signal or the internal clock signal, wherein the target clock signal includes the at least one clock signal; A crystal oscillator circuit is connected to the crystal input terminal of the phase-locked loop circuit and is used to provide a crystal oscillator signal to the phase-locked loop circuit.

6. The clock synchronization circuit of claim 2, wherein, The control circuit further includes a detection port, which is used to shut down the output of the internal clock signal of the first output port when the external clock signal is connected to the input port.

7. The clock synchronization circuit of claim 6, wherein, The detection port and input port of the control circuit are the same port.

8. An audio device, comprising: It includes an audio sampling circuit and a clock synchronization circuit as described in any one of claims 1 to 7, wherein the audio sampling circuit is connected to the clock synchronization circuit and is used to perform audio sampling based on the target clock signal.

9. The audio device of claim 8, wherein, The control circuit also includes: The data output port is connected to the data port of the clock configuration circuit and is used to configure the parameters of the target clock signal; A transmission configuration port is connected to the configuration port of the clock configuration circuit and is used to configure the transmission of the data output port.

10. An audio system, characterized by The device includes multiple audio devices as described in claim 8 or 9, wherein the clock synchronization circuits of each audio device are connected in series, wherein the input interface of the clock synchronization circuit of the subsequent audio device is connected to the output interface of the clock synchronization circuit of the preceding audio device, and the synchronization clock signal output by the clock synchronization circuit of the preceding audio device is input as an external clock signal to the clock transmission circuit of the subsequent audio device.

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